Power ceramic circuit board

Abstract

The utility model discloses a power ceramic circuit board, which comprises a ceramic substrate, a top surface circuit layer and a bottom surface heat dissipation layer, the top surface circuit layer comprises a top surface circuit, the bottom surface heat dissipation layer comprises a bottom surface circuit, and a pattern projected by the top surface circuit on the ceramic substrate and a pattern projected by the bottom surface circuit on the ceramic substrate are basically the same and basically coincide; and the thickness of the top surface circuit layer is basically the same as that of the bottom surface heat dissipation layer. According to the utility model, the thermal stress generated by the top surface circuit and the thermal stress generated by the bottom surface circuit are basically the same and opposite in direction, and can be mutually compensated, counteracted and balanced, so that when thermal shock occurs, the ceramic plate cannot generate larger deformation and brittle fracture due to the thermal stress, and the transmission capacity of heat conduction can be effectively maintained.

Description

Technical Field

[0001] The utility model relates to a ceramic circuit board, in particular to a power ceramic circuit board. Background Art

[0002] A power ceramic circuit board is a ceramic circuit board specifically used for power electronic applications. Since a power ceramic circuit board needs to carry a large current, the copper thickness of the top surface circuit layer is usually larger than that of the circuit layer of an ordinary circuit board. Therefore, a power ceramic board is a thick copper-clad circuit board, and the copper thickness of the circuit layer is usually greater than 100 micrometers (μm). The top surface of a traditional power ceramic circuit board is a die bonding circuit layer, and the bottom surface is a heat dissipation layer, which is usually a large-area copper layer. When the power ceramic circuit board is subjected to a thermal shock, due to the inconsistent structures of the upper and lower layers, different thermal stresses are generated between the upper and lower layers. When the copper-clad layer on the ceramic substrate is relatively thick, this thermal effect will become prominent. Moreover, the stress difference increases with the increase in the copper thickness. When the copper thickness exceeds a certain value, the thermal stress difference between the upper and lower layers may cause the ceramic substrate to deform or even crack brittlely.

[0003] The method for a traditional power ceramic circuit board to prevent the ceramic substrate from deforming and cracking brittlely due to thermal stress is to set the copper thicknesses on both sides of the circuit board to be different. The large-area copper layer is thinner, and the small-area copper layer is thicker. The thickness of the copper layer is determined by experiments, or by calculating the areas and volumes of the upper and lower copper layers, and finally corrected through tests. Although this method is helpful for improving the stress balance between the upper and lower surfaces, it does not fundamentally solve the difference in thermal stress between the upper and lower surfaces. When the power ceramic circuit board undergoes multiple thermal shocks, this thermal stress difference will still appear, and the ceramic substrate will still deform due to the imbalance of the upper and lower thermal stresses, and may even cause the ceramic to crack brittlely, making it difficult to achieve the expected effect. Summary of the Invention

[0004] The technical problem to be solved by the utility model is to provide a power ceramic circuit board that can prevent the ceramic substrate from cracking brittlely due to the imbalance of upper and lower thermal stresses.

[0005] To solve the above technical problem, the technical solution adopted by the utility model is that a power ceramic circuit board includes a ceramic substrate, a top surface circuit layer, and a bottom surface heat dissipation layer. The top surface circuit layer includes a top surface circuit, and the bottom surface heat dissipation layer includes a bottom surface circuit. The pattern projected by the top surface circuit on the ceramic substrate is substantially the same as and substantially coincides with the pattern projected by the bottom surface circuit on the ceramic substrate; the thickness of the top surface circuit layer is substantially the same as the thickness of the bottom surface heat dissipation layer.

[0006] For the above-mentioned power ceramic circuit board, calculated by the projected area of the pattern, the non-coincidence degree of the pattern projected by the top surface circuit on the ceramic substrate and the pattern projected by the bottom surface circuit on the ceramic substrate is less than 20%, and the error between the thickness of the top surface circuit layer and the thickness of the bottom surface heat dissipation layer is not greater than 20%.

[0007] For the power ceramic circuit board described above, the grooves of the bottom heat dissipation layer are filled with a first resin, and the first resin is a heat dissipation resin or a conductive heat dissipation resin.

[0008] For the power ceramic circuit board described above, the bottom heat dissipation layer includes an electroplated heat dissipation layer, and the electroplated heat dissipation layer is plated on the bottom surface of the first resin and the bottom surface of the bottom circuit.

[0009] For the power ceramic circuit board described above, the grooves of the top circuit layer are filled with a second resin, and the second resin is an insulating heat dissipation resin.

[0010] For the power ceramic circuit board described above, the conductive heat dissipation resin is a mixture of resin and conductive powder, and the conductive powder includes conductive carbon powder, graphite powder, and / or metal powder.

[0011] For the power ceramic circuit board described above, the insulating heat dissipation resin is a mixture of resin and insulating metal oxide or diamond powder or ceramic powder.

[0012] For the power ceramic circuit board described above, the thickness of the electroplated heat dissipation layer is 0.5 microns to 20 microns.

[0013] For the power ceramic circuit board described above, that the pattern projected by the top circuit on the ceramic substrate is substantially the same as and substantially coincident with the pattern projected by the bottom circuit on the ceramic substrate means that calculated by the projected area of the pattern, the non - coincidence degree between the pattern projected by the top circuit on the ceramic substrate and the pattern projected by the bottom circuit on the ceramic substrate is less than 20%; that the thickness of the top circuit layer is substantially the same as the thickness of the bottom heat dissipation layer means that the error between the thickness of the top circuit layer and the thickness of the bottom heat dissipation layer is not more than 20%.

[0014] For the power ceramic circuit board of the present utility model, the thermal stress generated by the top circuit is substantially the same as the thermal stress generated by the bottom circuit, and the directions are opposite, so they can be mutually compensated and balanced. When thermal shock occurs, the ceramic board will not have large deformation and brittle fracture due to thermal stress, and can effectively maintain the heat conduction transfer ability. [Description of the Drawings]

[0015] The present utility model will be further described in detail below in conjunction with the drawings and specific embodiments.

[0016] Figure 1 It is a front - view structural schematic diagram of the power ceramic circuit board of Embodiment 1 of the present utility model.

[0017] Figure 2 It is a rear - view structural schematic diagram of the power ceramic circuit board of Embodiment 1 of the present utility model.

[0018] Figure 3 Is isFigure 1 The A-A sectional view in

[0019] Figure 4 is a schematic cross-sectional structure diagram of the power ceramic circuit board of Embodiment 2 of the present utility model.

[0020] Figure 5 is a schematic cross-sectional structure diagram of the power ceramic circuit board of Embodiment 3 of the present utility model.

[0021] Figure 6 is a schematic cross-sectional structure diagram of the power ceramic circuit board of Embodiment 4 of the present utility model.

[0022] Figure 7 is a schematic cross-sectional structure diagram of the power ceramic circuit board of Embodiment 5 of the present utility model. [Specific implementation manner]

[0023] The structure of the power ceramic circuit board of Embodiment 1 of the present utility model is as Figures 1 to 3 shown, including a ceramic substrate 10, a top surface circuit layer 20, and a bottom surface heat dissipation layer 30. The top surface circuit layer 20 includes a top surface circuit 21, and the bottom surface heat dissipation layer 30 includes a bottom surface circuit 31. The pattern projected by the top surface circuit 21 on the ceramic substrate 10 is the same as and coincides with the pattern projected by the bottom surface circuit 31 on the ceramic substrate 10. The thickness H2 of the top surface circuit layer 20 is equal to the thickness H3 of the bottom surface heat dissipation layer 30.

[0024] When the bottom surface heat dissipation layer 30 includes the bottom surface circuit 31. The pattern projected by the top surface circuit 21 on the ceramic substrate 10 is the same as and coincides with the pattern projected by the bottom surface circuit 31 on the ceramic substrate 10. And the thickness H2 of the top surface circuit layer 20 is equal to the thickness H3 of the bottom surface heat dissipation layer 30, the thermal stress generated by the top surface circuit 21 is exactly the same as the thermal stress generated by the bottom surface circuit 31. When a thermal shock occurs, their stresses are exactly equal and can completely compensate and offset each other, and the ceramic plate will not deform or crack due to thermal stress.

[0025] In the structure of the power ceramic circuit board of Embodiment 1 of the present utility model, it is the most ideal situation. In some cases, the pattern of the top surface circuit 21 projected on the ceramic substrate 10 is substantially the same as and substantially coincides with the pattern of the bottom surface circuit 31 projected on the ceramic substrate 10, and it is only necessary that the thickness H2 of the top surface circuit layer 20 is substantially the same as the thickness H3 of the bottom surface heat dissipation layer 30. That the pattern of the top surface circuit 21 projected on the ceramic substrate 10 is substantially the same as and substantially coincides with the pattern of the bottom surface circuit 31 projected on the ceramic substrate 10 means that calculated by the projected area of the pattern, the non - coincidence degree of the pattern of the top surface circuit 21 projected on the ceramic substrate 10 and the pattern of the bottom surface circuit 31 projected on the ceramic substrate 10 is less than 20%. That the thickness H2 of the top surface circuit layer 20 is substantially the same as the thickness H3 of the bottom surface heat dissipation layer 30 means that the error between the thickness H2 of the top surface circuit layer 20 and the thickness H3 of the bottom surface heat dissipation layer 30 is not greater than 20%. When the pattern of the top surface circuit 21 projected on the ceramic substrate 10 is substantially the same as and substantially coincides with the pattern of the bottom surface circuit 31 projected on the ceramic substrate 10, and the thickness H2 of the top surface circuit layer 20 is substantially the same as the thickness H3 of the bottom surface heat dissipation layer 30, the thermal stress generated by the top surface circuit 21 is substantially the same as the thermal stress generated by the bottom surface circuit 31. When thermal shock occurs, their stresses are substantially equal and opposite in direction, and better compensation and cancellation can be achieved, and the ceramic board will not be deformed or cracked due to thermal stress.

[0026] In a slightly better case, the non - coincidence degree of the pattern of the top surface circuit 21 projected on the ceramic substrate 10 and the pattern of the bottom surface circuit 31 projected on the ceramic substrate 10 is less than 10%, and the error between the thickness H2 of the top surface circuit layer 20 and the thickness H3 of the bottom surface heat dissipation layer 30 is not greater than 10%.

[0027] The structure of the power ceramic circuit board of Embodiment 2 of the present utility model is as Figure 4 shown. On the basis of Embodiment 1, the trench of the bottom surface heat dissipation layer 30 is filled with a first resin 32, and the first resin 32 can be a heat - dissipating resin or a conductive heat - dissipating resin. The conductive heat - dissipating resin can be a mixture of resin and conductive powder, and the conductive powder includes conductive carbon powder, graphite powder, and / or metal powder.

[0028] The structure of the power ceramic circuit board of Embodiment 3 of the present utility model is as Figure 5 shown. On the basis of Embodiment 2, the bottom surface heat dissipation layer 30 includes an electroplated heat dissipation layer 33, and the electroplated heat dissipation layer 33 is plated on the bottom surface of the first resin 32 and the bottom surface of the bottom surface circuit 31. The thickness of the electroplated heat dissipation layer 33 is from 0.5 micrometers to 20 micrometers.

[0029] The structure of the power ceramic circuit board of Embodiment 4 of the present utility model is as Figure 6As shown, on the basis of Embodiment 2, the grooves of the top surface circuit layer 20 are filled with a second resin 22, and the second resin 22 is an insulating heat-dissipating resin. The insulating heat-dissipating resin includes a mixture of a resin and an insulating metal oxide or diamond powder or ceramic powder.

[0030] The structure of the power ceramic circuit board according to Embodiment 5 of the present utility model is as Figure 7 shown. On the basis of Embodiment 3, the grooves of the top surface circuit layer 20 are filled with a second resin 22, and the second resin 22 is an insulating heat-dissipating resin. The insulating heat-dissipating resin is a mixture of a resin and ceramic powder.

[0031] In the above embodiments of the present utility model, the thermal stress generated by the top surface circuit of the power ceramic circuit board and the thermal stress generated by the bottom surface circuit can be compensated and offset each other to obtain balance. When thermal shock occurs, the ceramic board will not produce large deformation and brittle fracture due to thermal stress, and can effectively maintain the heat conduction transfer ability.

Claims

1. A power ceramic circuit board, comprising a ceramic substrate, a top surface circuit layer and a bottom surface heat dissipation layer. The top surface circuit layer includes top surface circuits, and the bottom surface heat dissipation layer includes bottom surface circuits. It is characterized in that, The pattern projected by the top surface circuit on the ceramic substrate is substantially the same as and substantially coincident with the pattern projected by the bottom surface circuit on the ceramic substrate; the thickness of the top surface circuit layer is substantially the same as the thickness of the bottom surface heat dissipation layer.

2. The power ceramic circuit board according to claim 1, wherein Calculated by the projected area of the pattern, the non-coincidence degree between the pattern projected by the top surface circuit on the ceramic substrate and the pattern projected by the bottom surface circuit on the ceramic substrate is less than 20%, and the error between the thickness of the top surface circuit layer and the thickness of the bottom surface heat dissipation layer is not greater than 20%.

3. The power ceramic circuit board according to claim 1, wherein, The grooves of the bottom surface heat dissipation layer are filled with a first resin, and the first resin includes a heat dissipation resin or a conductive heat dissipation resin.

4. The power ceramic circuit board according to claim 3, characterized in that, The bottom surface heat dissipation layer includes an electroplated heat dissipation layer, and the electroplated heat dissipation layer is plated on the bottom surface of the first resin and the bottom surface of the bottom surface circuit.

5. The power ceramic circuit board according to claim 3 or 4, characterized in that, The grooves of the top surface circuit layer are filled with a second resin, and the second resin is an insulating heat dissipation resin.

6. The power ceramic circuit board according to claim 4, wherein, The thickness of the electroplated heat dissipation layer is 0.5 micrometers to 20 micrometers.

7. The power ceramic circuit board according to claim 1, wherein The fact that the pattern projected by the top surface circuit on the ceramic substrate is substantially the same as and substantially coincident with the pattern projected by the bottom surface circuit on the ceramic substrate means that calculated by the projected area of the pattern, the non-coincidence degree between the pattern projected by the top surface circuit on the ceramic substrate and the pattern projected by the bottom surface circuit on the ceramic substrate is less than 20%; the fact that the thickness of the top surface circuit layer is substantially the same as the thickness of the bottom surface heat dissipation layer means that the error between the thickness of the top surface circuit layer and the thickness of the bottom surface heat dissipation layer is not greater than 20%.

Images