Super-junction VDMOS device resistant to static breakdown

Abstract

The utility model relates to the technical field of power semiconductor devices, and discloses a super-junction VDMOS device resistant to static breakdown, which comprises a drain electrode and a grid electrode, an N + substrate is deposited on the upper surface of the drain electrode, a buffer layer is arranged above the N + substrate, a first N-epitaxial layer grows on the upper surface of the buffer layer, and a second N-epitaxial layer grows on the lower surface of the buffer layer. A first N-epitaxial layer is grown on the substrate, a P-region is formed in the first N-epitaxial layer through ion implantation diffusion, a second N-epitaxial layer grows on the first N-epitaxial layer, highly-doped P columns are arranged on the two sides in the second N-epitaxial layer, a heavily-doped region hole potential barrier region is arranged on one side of each P column, and a lightly-doped region hole potential well region is arranged on the lower side of one side of each P column. According to the VDMOS device, the thickness of the gate dielectric layer is increased, the total thickness of the gate dielectric layer is 100 nm, the single-particle shrinkage-through effect of the VDMOS device can be effectively improved, the gate dielectric layer is composed of 20 nm silicon dioxide and 80 nm trisilicon nitride, the single-particle shrinkage-through resistance characteristic of the device is further improved, and under the same gate voltage, gate-source electric leakage is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductor devices, and more specifically discloses a superjunction VDMOS device resistant to electrostatic breakdown. Background Art

[0002] Power semiconductor devices are the core devices for electric energy conversion and control. All electronic products are inseparable from power semiconductor devices, whether it is a portable terminal with a power of milliwatts or a high-speed train with a power of megawatts. Modern power semiconductor technology has been widely applied in all aspects of the national economy, from traditional industrial electronics to information communication, computers, consumer and automotive fields. New energy, rail transit, electric vehicles and smart grids are becoming powerful engines for the growth of the power semiconductor market.

[0003] The most representative product is the VDMOS acoustic effect power transistor. This double-diffused MOS device with vertical current flow is a voltage-controlled device. Under the control of an appropriate gate voltage, the semiconductor surface is inverted to form a conductive channel, enabling an appropriate amount of current to flow between the drain and the source.

[0004] In traditional VDMOS devices, under high-voltage and high-current conditions, due to uneven charge distribution, problems such as charge accumulation and electric field concentration often occur, resulting in a reduction in the reliability of the device. To solve this problem, the utility model proposes a superjunction VDMOS device resistant to electrostatic breakdown. Summary of the Invention

[0005] The utility model provides a superjunction VDMOS device resistant to electrostatic breakdown, which can solve the problems of charge accumulation and electric field concentration that often occur in traditional VDMOS devices under high-voltage and high-current conditions due to uneven charge distribution.

[0006] To solve the above technical problems, according to one aspect of the present utility model, more specifically, it is a superjunction VDMOS device resistant to electrostatic breakdown, including a drain electrode and a gate electrode. A layer of N+ substrate is deposited on the upper surface of the drain electrode. There is a buffer layer above the N+ substrate. An N-epitaxial layer 1 is grown on the upper surface of the buffer layer. And a P-region is formed by ion implantation and diffusion inside the N-epitaxial layer 1. An N-epitaxial layer 2 is grown above the N-epitaxial layer 1. High-doped P-columns are arranged on both sides inside the N-epitaxial layer 2. There is a heavily doped region hole barrier region above one side of the P-column, and a lightly doped region hole well region below one side of the P-column. And the upper part of the lightly doped region hole well region is in contact with the lower part of the heavily doped region hole barrier region. P-regions with horizontally equidistant distribution are formed by ion implantation inside the N-epitaxial layer 2. An N+ region is formed by ion implantation with the same high concentration in the middle above the P-region. A highly doped P+ region is formed by ion implantation on one side inside the P-region. The gate electrode is horizontally deposited above two adjacent N+ regions. A doped dielectric layer is below the gate electrode. And a gate dielectric layer wraps the outer sidewall of the gate electrode. A source electrode is arranged outside the gate dielectric layer. And the lower surface of the source electrode is deposited above the P-region. An anti-static layer is arranged on the upper surface of the source electrode. The anti-static layer is fixedly adhered to the source electrode.

[0007] In some embodiments, as a preferred technical solution, the buffer layer includes at least two silicon carbide thin film layers.

[0008] In some embodiments, as a preferred technical solution, the depth of the heavily doped region hole barrier region is the same as the depth of the lightly doped region hole well region.

[0009] In some embodiments, as a preferred technical solution, both the N-epitaxial layer 1 and the N-epitaxial layer 2 are N-type semiconductors, and the doping concentration of the N-epitaxial layer 1 is less than the doping concentration of the N-epitaxial layer 2.

[0010] In some embodiments, as a preferred technical solution, the dielectric layer is a high-K material.

[0011] In some embodiments, as a preferred technical solution, multiple P-columns and the adjacent N-epitaxial layer 2 form a superjunction structure.

[0012] In some embodiments, as a preferred technical solution, the total thickness of the gate dielectric layer is 100 nm.

[0013] In some embodiments, as a preferred technical solution, the gate dielectric layer is composed of 20 nm of silicon dioxide and 80 nm of silicon nitride.

[0014] The beneficial effects of the superjunction VDMOS device resistant to electrostatic breakdown of the present utility model are as follows:

[0015] In the present utility model, the traditional SiO2 is replaced with a high-k material. Without changing the device characteristics, the gate oxide thickness is increased, and the breakdown resistance characteristics of the gate-source of the device are enhanced.

[0016] The present utility model enhances the electrostatic breakdown resistance characteristics between the drain and the source. Brief Description of the Drawings

[0017] The following further describes the present utility model in detail with reference to the drawings and specific implementation methods.

[0018] Figure 1 It is a schematic structural diagram of the present utility model.

[0019] In the figure: 1. N+ substrate; 2. Drain; 3. P- region; 4. Buffer layer; 5. N- epitaxial layer I; 6. N- epitaxial layer II; 7. Lightly doped region hole potential well region; 8. Heavily doped region hole potential barrier region; 9. P pillar; 10. P- region; 11. N+ region; 12. Source; 13. Gate dielectric layer; 14. Gate; 15. Dielectric layer; 16. Antistatic layer; 17. P+ region. Specific Embodiments

[0020] The present utility model will be described in detail below with reference to the drawings and embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0021] According to the appendix Figure 1, a superjunction VDMOS device resistant to electrostatic breakdown is provided, which includes a drain 2 and a gate 14. A layer of N+ substrate 1 is deposited on the upper surface of the drain 2. There is a buffer layer 4 above the N+ substrate 1. An N- epitaxial layer one 5 is grown on the upper surface of the buffer layer 4. And a P- region 3 is formed by ion implantation and diffusion inside the N- epitaxial layer one 5. An N- epitaxial layer two 6 is grown above the N- epitaxial layer one 5. High-doped P columns 9 are arranged on both sides inside the N- epitaxial layer two 6. There is a heavily doped region hole barrier region 8 above one side of the P column 9, and a lightly doped region hole well region 7 below one side of the P column 9. And the upper part of the lightly doped region hole well region 7 is in contact with the lower part of the heavily doped region hole barrier region 8. P- regions 10 with horizontally equidistant distribution are formed by ion implantation inside the N- epitaxial layer two 6. An N+ region 11 is formed by ion implantation with the same high concentration in the middle above the P- regions 10. A highly doped P+ region 17 is formed by ion implantation on one side inside the P- regions 10. The gate 14 is horizontally deposited above two adjacent N+ regions 11. A doped dielectric layer 15 is below the gate 14. And a gate dielectric layer 13 wraps the outer sidewall of the gate 14. A source 12 is arranged outside the gate dielectric layer 13. And the lower surface of the source 12 is deposited above the P- regions 10. An anti-static layer 16 is arranged on the upper surface of the source 12. The anti-static layer 16 is fixedly adhered to the source 12. The thickness of the anti-static layer 16 is 0.3μm. The anti-static layer 16 can reduce electrostatic adsorption, thereby helping to prevent particle contamination of semiconductor devices and improving the quality and reliability of semiconductor products. The anti-static layer 16 is specifically an anti-static PEEK board, which has excellent mechanical strength, toughness, heat resistance at 250°C, and the anti-static layer 16 has a small resistance.

[0022] As Figure 1 shown, the gate oxide layer material of the device is replaced with a high-k material composed of 20nm SiO2 and 80nm Si3N4; two injection thin layers of P- and P+ are added laterally to the traditional superjunction P+ region; the epitaxial layer is divided into two layers, and the doping concentration of the epitaxial layer one is slightly higher than that of the epitaxial layer two, and a P- region is arranged in the middle of the epitaxial layer one; an anti-static layer is deposited on the entire surface of the device, and the material is an anti-static PEEK board, which has excellent mechanical strength, toughness, heat resistance up to 250°C and low resistance.

[0023] Due to its high-k characteristics, the high-k dielectric can allow the device to have a thicker oxide layer thickness, which can greatly reduce the tunneling risk of the device; the two added injection thin layers can form an electric field shield with the P- in the epitaxial layer one when suddenly electrostatically interfered between the drain and the source, absorb most of the static charges and form effective protection for the device; the setting of the anti-static layer can add a first layer of protection outside the whole device and filter out some low-voltage and low-charge electrostatic interferences.

[0024] To improve the single-event gate rupture resistance of the device, by increasing the thickness of the gate dielectric layer 13, the gate-source leakage current after radiation is reduced. The P-region 3 helps to increase the breakdown voltage.

[0025] In this embodiment, the buffer layer 4 includes at least two silicon carbide thin film layers; the buffer layer 4 provides nucleation centers for the growth of the subsequent epitaxial layer, which is beneficial to improving the growth quality of the epitaxial layer.

[0026] In this embodiment, the depth of the heavily doped region hole barrier region 8 is the same as the depth of the lightly doped region hole well region 7; by providing the heavily doped region hole barrier region 8 and the lightly doped region hole well region 7 in the N-epitaxial layer two 6, the avalanche resistance of the device can be improved, thereby enhancing the reliability of the VDMOS device.

[0027] In this embodiment, both the N-epitaxial layer one 5 and the N-epitaxial layer two 6 are N-type semiconductors, and the doping concentration of the N-epitaxial layer one 5 is less than that of the N-epitaxial layer two 6.

[0028] In this embodiment, the dielectric layer 15 is a high-K material; the dielectric layer 15 has excellent electrical properties, which can significantly improve the capacitance and stability of electronic components.

[0029] In this embodiment, multiple P-columns 9 and the adjacent N-epitaxial layer two 6 form a superjunction structure; there are multiple vertical PN junctions in the superjunction structure, achieving a low on-resistance while maintaining a high voltage.

[0030] In this embodiment, the total thickness of the gate dielectric layer 13 is 100 nm, which can effectively improve the single-event punch-through effect of the VDMOS device.

[0031] In this embodiment, the gate dielectric layer 13 is composed of 20 nm of silicon dioxide and 80 nm of silicon nitride, which can improve the single-event punch-through resistance of the device and reduce the gate-source leakage current under the same gate voltage.

[0032] The working principle of the present utility model is:

[0033] In the VDMOS device, by optimizing the structure on the epitaxial layer and introducing the dielectric layer 15 of high-K material, the charges inside the device are evenly distributed under high voltage and high current conditions, effectively solving the problems of charge accumulation and electric field concentration, and improving the reliability of the device. By increasing the thickness of the gate dielectric layer 13, with the total thickness of the gate dielectric layer 13 being 100 nm, the single-event punch-through effect of the VDMOS device can be effectively improved. Moreover, the gate dielectric layer 13 is composed of 20 nm of silicon dioxide and 80 nm of silicon nitride, further improving the single-event punch-through resistance of the device and reducing the gate-source leakage current under the same gate voltage.

[0034] All electrical components mentioned in this text are electrical components that exist in reality.

[0035] Of course, the above description is not a limitation to the present utility model, and the present utility model is not limited to the above examples. Changes, modifications, additions or substitutions made by those of ordinary skill in the art within the scope of the essence of the present utility model also belong to the protection scope of the present utility model.

Claims

1. A superjunction VDMOS device resistant to electrostatic breakdown, comprising a drain (2) and a gate (14), characterized in that: A layer of N+ substrate (1) is deposited on the upper surface of the drain (2). There is a buffer layer (4) above the N+ substrate (1). An N-epitaxial layer I (5) is grown on the upper surface of the buffer layer (4). A P-region (3) is formed by ion implantation and diffusion inside the N-epitaxial layer I (5). An N-epitaxial layer II (6) is grown above the N-epitaxial layer I (5). High-doped P-columns (9) are arranged on both sides inside the N-epitaxial layer II (6). There is a heavily doped region hole barrier region (8) above one side of the P-column (9), and a lightly doped region hole well region (7) below one side of the P-column (9). The upper part of the lightly doped region hole well region (7) is in contact with the lower part of the heavily doped region hole barrier region (8). P-regions (10) with horizontally equidistant distribution are formed by ion implantation inside the N-epitaxial layer II (6). An N+ region (11) is formed by ion implantation with the same high concentration in the middle above the P-region (10). A highly doped P+ region (17) is formed by ion implantation on one side inside the P-region (10). The gate (14) is horizontally deposited above two adjacent N+ regions (11). A doped dielectric layer (15) is arranged below the gate (14). A gate dielectric layer (13) wraps the outer sidewall of the gate (14). A source (12) is arranged outside the gate dielectric layer (13). The lower surface of the source (12) is deposited above the P-region (10). An anti-static layer (16) is arranged on the upper surface of the source (12). The anti-static layer (16) is fixedly pasted with the source (12).

2. The superjunction VDMOS device resistant to electrostatic breakdown according to claim 1, wherein: The buffer layer (4) includes at least two silicon carbide thin film layers.

3. The superjunction VDMOS device with electrostatic breakdown resistance according to claim 1, wherein: The depth of the heavily doped region hole barrier region (8) is the same as the depth of the lightly doped region hole well region (7).

4. A super junction VDMOS device resistant to electrostatic breakdown according to claim 1, characterized in that: Both the N-epitaxial layer I (5) and the N-epitaxial layer II (6) are N-type semiconductors, and the doping concentration of the N-epitaxial layer I (5) is less than the doping concentration of the N-epitaxial layer II (6).

5. A super junction VDMOS device resistant to electrostatic breakdown according to claim 1, characterized in that: The dielectric layer (15) is a high-K material.

6. The superjunction VDMOS device resistant to electrostatic breakdown according to claim 1, characterized in that: Multiple P-columns (9) and the adjacent N-epitaxial layer II (6) form a superjunction structure.

7. A super junction VDMOS device resistant to electrostatic breakdown according to claim 1, characterized in that: The total thickness of the gate dielectric layer (13) is 100 nm.

8. An electrostatic breakdown resistant superjunction VDMOS device according to claim 7, characterized in that: The gate dielectric layer (13) is composed of 20 nm silicon dioxide and 80 nm silicon nitride.

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