ESD (Electro-Static Discharge) electrostatic protection circuit and chip for dual-power supply
The dual-source ESD protection circuit addresses the limitation of single-source protection by using a novel design with dedicated discharge paths and reduced leakage, ensuring effective ESD protection for integrated circuits with multiple power supplies.
Patent Information
- Application Number
- CN202422241157.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-09-12
AI Technical Summary
The existing ESD electrostatic protection circuit can only protect a single power supply and cannot meet the needs of multi-power input chips.
An ESD electrostatic protection circuit including a delay resistor, a voltage divider, a discharge MOS tube and two ESD protection units is designed. The discharge path of negative and positive electrostatic pulses is provided through the reverse discharge branch and the forward discharge branch respectively, and the leakage current is prevented by the forward conduction voltage divider, and the leakage MOS tube and a delay resistor are used to reduce the circuit area.
The ESD electrostatic protection of the two power supplies is achieved, which avoids leakage current and reduces the circuit area, which is suitable for integrated implementation.
Smart Images
Figure CN223109659U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of ESD protection, and particularly relates to an ESD electrostatic protection circuit and a chip for dual-power supply. Background Art
[0002] In integrated circuits, the impact of Electro-Static Discharge (ESD) on the reliability of chips cannot be ignored. Especially in today's widespread application of deep sub-micron technology and nanotechnology, the destructive impact of ESD from external environments, human bodies, machinery, and radiation fields on IC chips is more significant.
[0003] In order to provide ESD electrostatic protection for chips, a great deal of research and practice has been carried out on ESD protection during the design and manufacturing process of chips. Generally, the design of ESD protection devices on chips needs to consider the following two factors. The first is that the ESD protection device should be able to discharge large currents, and the second is that the ESD protection device should be able to clamp the voltage at the chip pin end to a safe low voltage level when the chip is subjected to ESD impact.
[0004] Currently, the devices mainly used for ESD protection based on the above two design considerations are diodes, RC clamps, GGNMOS (Gate Ground NMOS, i.e., NMOS with the gate grounded), GDPMOS (Gate VDDPMOS, i.e., PMOS with the gate connected to VDD), and Silicon Controlled Rectifier (SCR).
[0005] For existing ESD electrostatic protection circuits based on ESD protection devices, most of them can only provide ESD electrostatic protection for a single power supply and cannot provide ESD electrostatic protection for two power supplies, thus unable to meet the ESD electrostatic protection requirements of chips with multiple power inputs. Summary of the Utility Model
[0006] In view of the deficiencies in the background art, the utility model provides an ESD electrostatic protection circuit and a chip for dual-power supply. The technical problem to be solved is that existing ESD electrostatic protection circuits can only provide ESD electrostatic protection for a single power supply and cannot provide ESD electrostatic protection for two power supplies, thus unable to meet the ESD electrostatic protection requirements of chips with multiple power inputs.
[0007] To solve the above technical problems, in a first aspect, the utility model provides the following technical solution: An ESD electrostatic protection circuit for dual-power supply includes a delay resistor, a voltage-dividing resistor, a discharging MOS transistor, and two ESD protection units;
[0008] The ESD protection unit includes a power supply terminal, a reverse discharge branch, a forward discharge branch, a forward conduction voltage dividing unit, a driving unit, and a delay capacitor;
[0009] The power supply terminal is electrically connected to the reverse discharge branch and the forward conduction voltage dividing unit respectively, and is electrically connected to the drain of the discharge MOS transistor through the forward discharge branch. The source of the discharge MOS transistor is grounded;
[0010] The reverse discharge branch is used to provide a reverse discharge path when a negative electrostatic pulse is input to the power supply terminal;
[0011] The forward conduction voltage dividing unit is electrically connected to one end of a voltage dividing resistor, and the other end of the voltage dividing resistor is grounded. The forward conduction voltage dividing unit is used to conduct when a positive power supply is input to the power supply terminal, and forms a voltage dividing branch together with the voltage dividing resistor;
[0012] The driving unit is electrically connected to the power supply terminal and one end of the voltage dividing resistor respectively, and sends a control signal to the forward discharge branch based on the voltage of the power supply terminal and the voltage of one end of the voltage dividing resistor. The forward discharge branch provides a forward discharge path based on the control signal;
[0013] The delay capacitor is electrically connected to the control signal output terminal of the driving unit, the other end of the delay capacitor is grounded through a delay resistor, and is electrically connected to the gate of the discharge MOS transistor.
[0014] In a certain implementation manner of the first aspect, the reverse discharge branch includes diode D1 and diode D2. The negative electrode of diode D1 is electrically connected to the power supply terminal, the positive electrode of diode D1 is electrically connected to the negative electrode of diode D2, and the positive electrode of diode D2 is grounded.
[0015] In a certain implementation manner of the first aspect, the forward conduction voltage dividing unit includes diode D3 and resistor R2. The positive electrode of diode D3 is electrically connected to the power supply terminal, and the negative electrode of diode D3 is electrically connected to the voltage dividing resistor through resistor R2.
[0016] In a certain implementation manner of the first aspect, the forward discharge branch includes MOS transistor P2. The source of MOS transistor P2 is electrically connected to the power supply terminal, the drain of MOS transistor P2 is electrically connected to the drain of the discharge MOS transistor, and the gate of MOS transistor P2 is used to input the control signal.
[0017] In a certain embodiment of the first aspect, the driving unit includes MOS transistor P1, MOS transistor P2, and resistor R1. The source of MOS transistor P1 is electrically connected to the power supply terminal. The gate of MOS transistor P1 is electrically connected to one end of the voltage-dividing resistor. The drain of MOS transistor P1 is electrically connected to the source of MOS transistor P3 through resistor R1. The source of MOS transistor P3 is the control signal output terminal of the driving unit and is electrically connected to the gate of MOS transistor P2. The gate of MOS transistor P3 is electrically connected to the power supply terminal. The drain of MOS transistor P3 is electrically connected to one end of the voltage-dividing resistor.
[0018] In a certain embodiment of the first aspect, MOS transistors P1, P2, and P3 are all PMOS transistors.
[0019] In a certain embodiment of the first aspect, the discharging MOS transistor is an NMOS transistor.
[0020] In a certain embodiment of the first aspect, the positive voltage of the power supply terminal is denoted as V1, and the voltage on the voltage-dividing resistor is greater than 0.48V1 and less than 0.52V1.
[0021] In a certain embodiment of the first aspect, the VDSS voltages of MOS transistors P2 and N1 are respectively greater than the voltage on the voltage-dividing resistor. The VDSS voltage is the maximum voltage that can be applied before the gate-source of the MOS transistor is short-circuited and the drain-source does not undergo avalanche breakdown.
[0022] In the second aspect, the present invention provides a chip, on which there is provided an ESD electrostatic protection circuit for dual-power supply as described above.
[0023] The beneficial effects of the present invention compared with the prior art are as follows:
[0024] Firstly, by setting two ESD electrostatic protection units, and each ESD electrostatic protection unit provides a discharging path for negative electrostatic pulses through a reverse discharging branch, and provides a forward discharging path through a forward discharging branch and a discharging MOS transistor, so as to perform ESD electrostatic protection on two power supplies;
[0025] Secondly, by setting a forward-conducting voltage-dividing unit to provide a unidirectional-conducting current path, leakage current will not be generated in the two ESD electrostatic protection units;
[0026] Finally, the two ESD electrostatic protection units share a discharging MOS transistor and a delay resistor, and the circuit area is reduced through the way of device sharing, which is conducive to integration implementation. Description of the Drawings
[0027] Figure 1 It is the circuit diagram of the ESD electrostatic protection circuit of the present invention in the embodiment. Detailed implementation mode
[0028] The present utility model will now be further described in detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only schematically showing the basic structure of the present utility model, so they only show the components related to the present utility model.
[0029] Embodiment 1
[0030] As Figure 1 shown, an ESD electrostatic protection circuit for dual-power supply includes a delay resistor R4, a voltage-dividing resistor R3, a discharging MOS transistor N1, and two ESD protection units 1; wherein the discharging MOS transistor N1 is an NMOS transistor;
[0031] Taking the left ESD protection unit 1 as an example, the ESD protection unit 1 includes a power supply terminal V1, a reverse discharging branch 10, a forward discharging branch 11, a forward conduction voltage-dividing unit 12, a driving unit 13, and a delay capacitor C1; it should be noted that for the convenience of distinction, Figure 1 the components at the same positions of the two ESD electrostatic protection units 1 are named differently;
[0032] In Figure 1 the left ESD electrostatic protection unit 1, the power supply terminal V1 is electrically connected to the reverse discharging branch 10 and the forward conduction voltage-dividing unit 12 respectively, and is electrically connected to the drain of the discharging MOS transistor N1 through the forward discharging branch 11, and the source of the discharging MOS transistor N1 is grounded;
[0033] The reverse discharging branch 10 is used to provide a reverse discharging path when a negative electrostatic pulse is input at the power supply terminal V1;
[0034] The forward conduction voltage-dividing unit 12 is electrically connected to one end of the voltage-dividing resistor R3, the other end of the voltage-dividing resistor R3 is grounded, and the forward conduction voltage-dividing unit 12 is used to conduct when a positive power supply is input at the power supply terminal V1, and forms a voltage-dividing branch together with the voltage-dividing resistor R3;
[0035] The driving unit 13 is electrically connected to the power supply terminal V1 and one end of the voltage-dividing resistor R3 respectively, and sends a control signal to the forward discharging branch 11 based on the voltage of the power supply terminal V1 and the voltage of one end of the voltage-dividing resistor R3, and the forward discharging branch 11 provides a forward discharging path based on the control signal;
[0036] The delay capacitor C1 is electrically connected to the control signal output terminal of the driving unit 13, the other end of the delay capacitor C1 is grounded through the delay resistor R4, and is electrically connected to the gate of the discharging MOS transistor N1.
[0037] In actual use, the utility model provides two ESD electrostatic protection units 1, and each ESD electrostatic protection unit 1 provides a discharge path for negative electrostatic pulses through a reverse discharge branch 10, and provides a forward discharge path through a forward discharge branch 11 and a discharge MOS transistor N1, so as to perform ESD electrostatic protection on two power supplies;
[0038] In addition, by providing a forward conduction voltage division unit 12 to provide a current path for unidirectional conduction, leakage current will not be generated in the two ESD electrostatic protection units 1;
[0039] Finally, the two ESD electrostatic protection units 1 share the discharge MOS transistor N1 and the delay resistor R4, and the circuit area is reduced by the way of device sharing, which is beneficial to the realization of integration.
[0040] Specifically, in this embodiment, the reverse discharge branch 10 includes a diode D1 and a diode D2. The negative electrode of the diode D1 is electrically connected to the power supply terminal V1, the positive electrode of the diode D1 is electrically connected to the negative electrode of the diode D2, and the positive electrode of the diode D2 is grounded.
[0041] In actual use, when there is a negative electrostatic pulse at the power supply terminal V1, the diodes D1 and D2 are turned on, so as to provide a discharge path for the negative electrostatic pulse.
[0042] In a certain implementation manner, the number of diodes in the reverse discharge branch 10 can be increased. Specifically, the number of diodes in the reverse discharge branch 10 can also be two, three, four or other numbers, which can be specifically set according to actual requirements.
[0043] Specifically, in this embodiment, the forward conduction voltage division unit 12 includes a diode D3 and a resistor R2. The positive electrode of the diode D3 is electrically connected to the power supply terminal V1, and the negative electrode of the diode D3 is electrically connected to the voltage division resistor R3 through the resistor R2.
[0044] In actual use, the diode D3 is used to achieve the function of forward conduction, and the resistor R2 and the voltage division resistor R3 perform voltage division; in addition, by increasing the resistance values of the resistor R2 and the voltage division resistor R3, current limiting can be performed.
[0045] Specifically, in this embodiment, the positive voltage of the power supply terminal V1 is denoted as V1, and the voltage on the voltage division resistor is greater than 0.48V1 and less than 0.52V1.
[0046] In addition, in this embodiment, the VDSS voltages of the MOS transistor P2 and the MOS transistor N1 are respectively greater than the voltage on the voltage division resistor. The VDSS voltage is the maximum voltage that can be applied before the gate-source of the MOS transistor is short-circuited and the drain-source does not undergo avalanche breakdown.
[0047] Specifically, in this embodiment, the forward discharge branch 12 includes a MOS transistor P2, where the MOS transistor P2 is a PMOS transistor. The source of the MOS transistor P2 is electrically connected to the power supply terminal V1, the drain of the MOS transistor P2 is electrically connected to the drain of the discharge MOS transistor N1, and the gate of the MOS transistor P2 is used to input a control signal.
[0048] Specifically, in this embodiment, the driving unit 13 includes a MOS transistor P1, a MOS transistor P2, and a resistor R1. The source of the MOS transistor P1 is electrically connected to the power supply terminal V1, the gate of the MOS transistor P1 is electrically connected to one end of the voltage-dividing resistor R3, the drain of the MOS transistor P1 is electrically connected to the source of the MOS transistor P3 through the resistor R1. The source of the MOS transistor P3 is the control signal output terminal of the driving unit 13 and is electrically connected to the gate of the MOS transistor P2. The gate of the MOS transistor P3 is electrically connected to the power supply terminal V1, and the drain of the MOS transistor P3 is electrically connected to one end of the voltage-dividing resistor R3. In addition, both the MOS transistor P1 and the MOS transistor P3 are PMOS transistors.
[0049] For Figure 1 the circuit shown is analyzed as follows:
[0050] First, set the voltage division ratio of the voltage-dividing resistor R3 to 0.5;
[0051] When the circuit is working normally, if the voltage of the power supply terminal V1 is 5V and the voltage of the power supply terminal V2 is 0V, the voltage of node A is 2.5V. At this time, |VDS| of the MOS transistor P1 and the MOS transistor N1 is 2.5V. Select MOS transistors P2 and N1 with VDSS greater than 2.5V;
[0052] In addition, |VGS| of the MOS transistor P1 is 2.5V, which is greater than |VTH| of the P1 transistor. The MOS transistor P1 is turned on, and the voltage of node B is pulled up to 5V. |VGS| of the MOS transistor P2 and the MOS transistor P3 is 0, and the MOS transistor P2 and the MOS transistor P3 operate in the cut-off region;
[0053] For the right ESD electrostatic protection unit 1, the voltage of the power supply terminal V2 is 0V, the voltage of node VA is 2.5V, |VGS| of the MOS transistor P6 is 2.5V, which is greater than |VTH| of the P6 transistor. The MOS transistor P6 is turned on, and the voltage of node E is pulled up to 2.5V. At this time, |VGS| of the MOS transistor P4 and the MOS transistor P5 is 0V, the MOS transistor P4 and the MOS transistor P5 operate in the cut-off region, and the diode D4 is also reverse-biased and cut off. Therefore, no leakage current is generated from the power supply terminal V1 to the power supply terminal V2. The only path from the power supply terminal V1 to the power supply ground GND is the diode D3, the resistor R2, and the voltage-dividing resistor R3. Therefore, the resistance values of the resistor R2 and the voltage-dividing resistor R3 can be appropriately increased for current limiting. Similarly, when the voltage of the power supply terminal V1 is 0V and the voltage of the power supply terminal V2 is 5V, no leakage current is generated from the power supply terminal V2 to the power supply terminal V1.
[0054] When an ESD event occurs and ESD electrostatic protection is required:
[0055] If a positive electrostatic pulse enters from the power supply terminal V1, a high potential is generated at the power supply terminal V1. After being divided by the diode D3, the resistor R2, and the voltage-dividing resistor R3, the voltage at node A is approximately V1 / 2. At this time, the MOS transistor P1 is turned on, and the MOS transistor P3 is turned off. The voltage at node B is pulled up to V1. At this time, the gate of the MOS transistor P2 is connected to V1 through the resistor R1 to form a GDPMOS (Gate VDDPMOS, that is, a PMOS with the gate connected to VDD), and the ESD large current is discharged by working through the parasitic lateral PNP transistor;
[0056] In addition, since the voltage across the capacitor C1 cannot change suddenly, the voltage at node D is also V1. At this time, the gate of the MOS transistor N1 is at a high potential, the MOS transistor N1 is turned on, and a low-resistance path formed by the MOS transistor P2 and the MOS transistor N1 discharges the ESD large current. With the attenuation of the coupling effect of the RC delay circuit composed of the delay capacitor C1 and the delay resistor R4, the voltage at node D slowly decreases, and the MOS transistor N2 is gradually turned off. Therefore, when a positive ESD electrostatic pulse enters from the input terminal V1, the ESD large current can be discharged through the MOS transistor P2 and the MOS transistor N1;
[0057] When a negative electrostatic pulse enters from the power supply terminal V1, the negative electrostatic pulse is transmitted to GND through the diode D1 and the diode D2, and the electrostatic pulse is discharged.
[0058] Similarly, when an electrostatic pulse enters from the power supply terminal V2, the principle is the same as that shown above, and no further description is given here.
[0059] Embodiment 2
[0060] This embodiment provides a chip, and an ESD electrostatic protection circuit for dual-power supply as described in Embodiment 1 is provided on the chip.
[0061] Based on the inspiration of the present invention, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.
Claims
1. An ESD electrostatic protection circuit for dual-power supply, characterized in that, It includes a delay resistor, a voltage-dividing resistor, a discharging MOS transistor, and two ESD protection units; The ESD protection unit includes a power supply terminal, a reverse discharging branch, a forward discharging branch, a forward-conducting voltage-dividing unit, a driving unit, and a delay capacitor; The power supply terminal is electrically connected to the reverse discharging branch and the forward-conducting voltage-dividing unit respectively, and is electrically connected to the drain of the discharging MOS transistor through the forward discharging branch, and the source of the discharging MOS transistor is grounded; The reverse discharging branch is used to provide a reverse discharging path when a negative static electricity pulse is input at the power supply terminal; The forward-conducting voltage-dividing unit is electrically connected to one end of the voltage-dividing resistor, the other end of the voltage-dividing resistor is grounded, and the forward-conducting voltage-dividing unit is used to conduct when a positive power supply is input at the power supply terminal, and forms a voltage-dividing branch together with the voltage-dividing resistor; The driving unit is electrically connected to the power supply terminal and one end of the voltage-dividing resistor respectively, and sends a control signal to the forward discharging branch based on the voltage at the power supply terminal and the voltage at one end of the voltage-dividing resistor, and the forward discharging branch provides a forward discharging path based on the control signal; The delay capacitor is electrically connected to the control signal output terminal of the driving unit, the other end of the delay capacitor is grounded through the delay resistor, and is electrically connected to the gate of the discharging MOS transistor.
2. The ESD electrostatic protection circuit for dual-power supply according to claim 1, wherein The reverse discharging branch includes diode D1 and diode D2, the negative electrode of diode D1 is electrically connected to the power supply terminal, the positive electrode of diode D1 is electrically connected to the negative electrode of diode D2, and the positive electrode of diode D2 is grounded.
3. The ESD electrostatic protection circuit for dual-power supply according to claim 1, wherein The forward-conducting voltage-dividing unit includes diode D3 and resistor R2, the positive electrode of diode D3 is electrically connected to the power supply terminal, and the negative electrode of diode D3 is electrically connected to the voltage-dividing resistor through resistor R2.
4. The ESD electrostatic protection circuit for dual-power supply according to claim 1, characterized in that, The forward discharging branch includes MOS transistor P2, the source of MOS transistor P2 is electrically connected to the power supply terminal, the drain of MOS transistor P2 is electrically connected to the drain of the discharging MOS transistor, and the gate of MOS transistor P2 is used to input the control signal.
5. The ESD electrostatic protection circuit for dual - power - supply according to claim 4, wherein The driving unit includes MOS transistor P1, MOS transistor P2, and resistor R1, the source of MOS transistor P1 is electrically connected to the power supply terminal, the gate of MOS transistor P1 is electrically connected to one end of the voltage-dividing resistor, the drain of MOS transistor P1 is electrically connected to the source of MOS transistor P3 through resistor R1, the source of MOS transistor P3 is the control signal output terminal of the driving unit and is electrically connected to the gate of MOS transistor P2, the gate of MOS transistor P3 is electrically connected to the power supply terminal, and the drain of MOS transistor P3 is electrically connected to one end of the voltage-dividing resistor.
6. The ESD electrostatic protection circuit for dual - power - supply according to claim 5, characterized in that, MOS transistors P1, P2, and P3 are all PMOS transistors.
7. The ESD electrostatic protection circuit for dual-power supply according to claim 1, wherein The discharging MOS transistor is an NMOS transistor.
8. The ESD electrostatic protection circuit for dual-power supply according to claim 1, characterized in that, The positive voltage at the power supply terminal is denoted as V1, and the voltage on the voltage-dividing resistor is greater than 0.48V1 and less than 0.52V1.
9. The ESD electrostatic protection circuit for dual - power - supply according to claim 8, characterized in that, The VDSS voltage of MOS transistors P2 and N1 is greater than the voltage on the voltage-dividing resistor, and the VDSS voltage is the maximum voltage that can be applied before the gate-source of the MOS transistor is short-circuited and the drain-source does not undergo avalanche breakdown.
10. A chip, characterized in that, The chip is provided with an ESD electrostatic protection circuit for dual-power supply according to any one of claims 1-9.