Monolithic integrated isolation sampling chip
The single-chip integrated isolating sampler chip addresses the high cost and space issues of separate power supplies by integrating isolation DC-DC converters and sampling components within the chip, enhancing space efficiency and reducing costs.
Patent Information
- Application Number
- CN202422321716.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-09-23
AI Technical Summary
In the prior art, the power supply scheme of the isolated sampling circuit is relatively expensive, the external sampling resistor and filtered energy storage capacitor occupy a large area, and additional power output pins are required.
It provides a monolithic integrated isolated sampling chip, which realizes on-chip power supply through a built-in isolated DC-DC conversion circuit, and integrates the output capacitor and sampling resistor of the isolated DC-DC conversion circuit inside the chip package.
Saves the overall area of the chip and output pins, reducing costs.
Smart Images
Figure CN223109997U_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present utility model relate to the field of integrated circuit technologies, and in particular, to a monolithic integrated isolation sampling chip. Background Art
[0002] In application fields such as motor drivers, photovoltaic inverters, traction inverters, charging piles, and on-vehicle chargers, a sampling circuit is usually required to sample voltage and / or current to achieve precise voltage and / or current detection. At the same time, in order to protect electronic instrument devices and personal safety, the sampling circuit needs to transmit voltage and / or current information from one power supply domain (such as the high-voltage side) to another power supply domain (such as the low-voltage side) through an isolation gate for monitoring and control. For the power supply of the isolation sampling circuit, two independent power supply circuits are usually adopted in different power supply domains, but this solution has a relatively high cost. Moreover, external sampling resistors are mostly through-hole or surface-mounted components, which will occupy a large area. In addition, the filter energy storage capacitors required for the output port of the isolated DC-DC converter are also in an external form, which not only occupies area but also requires additional power output pins. Summary of the Utility Model
[0003] Based on the above situation of the prior art, the purpose of the embodiments of the present utility model is to provide a monolithic integrated isolation sampling chip, which realizes on-chip power supply for the isolation sampling circuit by integrating an isolated DC-DC conversion circuit, and at the same time integrates the output capacitor of the isolated DC-DC conversion circuit and the sampling resistor of the isolation sampling circuit inside the chip package, saving the overall area of the chip and output pins.
[0004] To achieve the above object, according to one aspect of the present utility model, there is provided a monolithic integrated isolation sampling chip, the chip including a first die and a second die;
[0005] The first die is provided with a first conversion circuit module and a first isolation sampling circuit module, the first conversion circuit module including a rectification circuit; the first isolation sampling circuit module including an operational amplifier and a modulator connected in sequence;
[0006] The second bare die is provided with a second conversion circuit module and a second isolation sampling circuit module. The second conversion circuit module includes a drive circuit; the second isolation sampling circuit module includes a filter circuit; the first conversion circuit module and the second conversion circuit module are coupled by a transformer to form an isolated DC-DC conversion circuit, and the transformer is disposed on at least one of the first bare die and the second bare die; the first isolation sampling circuit module and the second isolation sampling circuit module are coupled by an isolation circuit to form an isolation sampling circuit; the isolation circuit includes a first isolation circuit and a second isolation circuit, the first isolation circuit is disposed on at least one of the first bare die and the second bare die, and the second isolation circuit is disposed on at least one of the first bare die and the second bare die; the isolated DC-DC conversion circuit outputs a DC supply voltage inside the chip to supply power to the isolation sampling circuit;
[0007] The isolated DC-DC conversion circuit further includes an output capacitor;
[0008] The output capacitor is a silicon capacitor formed on the first bare die, and the isolated DC-DC conversion circuit outputs a DC supply voltage inside the first bare die to supply power to the isolation sampling circuit; or,
[0009] The output capacitor is a chip capacitor integrated inside the chip package.
[0010] Further, the chip includes a first differential input terminal and a second differential input terminal;
[0011] The lead frames of the first differential input terminal and the second differential input terminal form a sampling resistor, and the first differential input terminal and the second differential input terminal receive an input signal through the sampling resistor;
[0012] The non-inverting input terminal and the inverting input terminal of the operational amplifier are respectively connected to the first differential input terminal and the second differential input terminal.
[0013] Further, the chip further includes an isolation sampling output terminal and a DC voltage input terminal;
[0014] The isolation sampling output terminal outputs a sampling output signal;
[0015] The DC voltage input terminal receives a DC input voltage, and the DC input voltage is converted into a DC supply voltage through the isolated DC-DC conversion circuit.
[0016] Further, the first isolation circuit includes a first sending circuit, a second receiving circuit and a second isolation coupling transmission structure;
[0017] The second isolation circuit includes a first receiving circuit, a first isolation coupling transmission structure and a second sending circuit;
[0018] The first transmitting circuit and the first receiving circuit are coupled through the first isolation and coupling transmission structure to form a first signal transmission circuit; the second transmitting circuit and the second receiving circuit are coupled through the second isolation and coupling transmission structure to form a second signal transmission circuit; the first signal transmission circuit transmits a signal from the first bare die to the second bare die, and the second signal transmission circuit transmits a signal from the second bare die to the first bare die.
[0019] Further, the first transmitting circuit and the second receiving circuit are disposed on the first bare die, and the first receiving circuit and the second transmitting circuit are disposed on the second bare die;
[0020] The first isolation and coupling transmission structure is disposed on at least one of the first bare die and the second bare die, and the second isolation and coupling transmission structure is disposed on at least one of the first bare die and the second bare die.
[0021] Further, the first isolation and coupling transmission structure is a transformer, a capacitor or a giant magnetoresistance, and the second isolation and coupling transmission structure is a transformer, a capacitor or a giant magnetoresistance.
[0022] Further, the filtering circuit is an analog filtering circuit, the isolation sampling output end includes a first isolation sampling output end and a second isolation sampling output end, a first differential output end of the analog filtering circuit is connected to the first isolation sampling output end, and a second differential output end is connected to the second isolation sampling output end;
[0023] The first differential output end and the second differential output end output a differential analog output signal.
[0024] Further, the filtering circuit is an analog filtering circuit, and the second isolation sampling circuit module further includes a differential-to-single-ended circuit, and the differential-to-single-ended circuit is connected to an output end of the analog filtering circuit;
[0025] An output end of the differential-to-single-ended circuit is connected to the isolation sampling output end, and the output end outputs a single-ended analog output signal.
[0026] Further, the filtering circuit is a digital filtering circuit;
[0027] An output end of the digital filtering circuit is connected to the isolation sampling output end, and the output end outputs a bit stream digital output signal.
[0028] Further, the digital filtering circuit further includes a clock input end, and the clock input end receives a clock signal.
[0029] In summary, the embodiment of the present utility model provides a monolithic integrated isolation sampling chip, which includes a first die and a second die; the first die is provided with a first conversion circuit module and a first isolation sampling circuit module, the second die is provided with a second conversion circuit module and a second isolation sampling circuit module, the first conversion circuit module and the second conversion circuit module are coupled through a transformer to form an isolated DC-DC conversion circuit, and the first isolation sampling circuit module and the second isolation sampling circuit module are coupled through an isolation circuit to form an isolation sampling circuit. The monolithic integrated isolation sampling chip provided by the embodiment of the present utility model realizes on-chip power supply for the isolation sampling circuit through the built-in isolated DC-DC conversion circuit, and at the same time integrates the output capacitor of the isolated DC-DC conversion circuit and the sampling resistor of the isolation sampling circuit inside the chip package, saving the overall chip area and output pins. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 FIG. is a schematic circuit structure diagram of a monolithic integrated isolation sampling chip provided by an embodiment of the present utility model;
[0031] Figure 2 FIG. is a schematic circuit structure diagram of a monolithic integrated isolation sampling chip provided by another embodiment of the present utility model;
[0032] Figure 3 FIG. is a schematic circuit structure diagram of a monolithic integrated isolation sampling chip provided by another embodiment of the present utility model;
[0033] Figure 4 FIG. is a schematic circuit structure diagram of a monolithic integrated isolation sampling chip provided by another embodiment of the present utility model;
[0034] Figure 5 FIG. is a schematic circuit structure diagram of a monolithic integrated isolation sampling chip provided by another embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0035] To make the objectives, technical solutions, and advantages of the present utility model clearer and more understandable, the present utility model will be further described in detail below in conjunction with the specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present utility model. In addition, in the following description, the descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present utility model.
[0036] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of the present utility model should have the ordinary meanings understood by those with ordinary skills in the field to which the present utility model belongs. The "first", "second" and similar words used in one or more embodiments of the present utility model do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
[0037] The technical solution of the present utility model will be described in detail below with reference to the drawings. An embodiment of the present utility model provides a monolithic integrated isolation sampling chip. Figure 1 Fig. shows a schematic circuit diagram of the monolithic integrated isolation sampling chip provided by the embodiment of the present utility model, as Figure 1 shown, the isolation sampling chip provided by this embodiment includes a first die 101 and a second die 102. The first die 101 and the second die 102 are integrally packaged in the same package through wire bonding, stacking package or other connection methods. A first conversion circuit module and a first isolation sampling circuit module are provided on the first die 101. The first conversion circuit module includes a rectification circuit 1011; the first isolation sampling circuit module includes an operational amplifier 1012 and a modulator 1013 connected in sequence. The operational amplifier 1012 is, for example, a differential operational amplifier. A second conversion circuit module and a second isolation sampling circuit module are provided on the second die 102. The second conversion circuit module includes a drive circuit 1021, and the second isolation sampling circuit module includes a filter circuit 1022.
[0038] The first conversion circuit module and the second conversion circuit module are coupled through a transformer 103 to form an isolated DC-DC conversion circuit. Among them, the drive circuit 1021 located on the primary side is used to convert the DC input voltage into an AC voltage, the transformer 103 is used to isolate and transmit the AC voltage, and the rectification circuit 1011 located on the secondary side converts the AC voltage into a DC output voltage. The transformer 103 is disposed on at least one of the first die 101 and the second die 102. For example, the primary coil and the secondary coil of the transformer 103 can be disposed on the first die 101, or can be disposed on the second die 102, and the first die 101 and the second die 102 are packaged by wire bonding; it is also possible to separately dispose the primary coil and the secondary coil of the transformer 103 on the first die 101 and the second die 102, and the first die 101 and the second die 102 are packaged by stacking.
[0039] The first isolation sampling circuit module and the second isolation sampling circuit module are coupled through isolation circuit 100 to form an isolation sampling circuit. This isolation sampling circuit is used to detect voltage or current. Among them, isolation circuit 100 includes a first isolation circuit and a second isolation circuit. The first isolation circuit is disposed on at least one of the first die 101 and the second die 102, and the second isolation circuit is disposed on at least one of the first die 101 and the second die 102. This isolated DC-DC conversion circuit outputs a DC supply voltage inside the chip to supply power to the isolation sampling circuit.
[0040] According to some optional embodiments, this isolated DC-DC conversion circuit further includes an output capacitor C. The output capacitor C is connected to the output terminal of the isolated DC-DC conversion circuit and is used for filtering and energy storage. Figure 2 The circuit structure diagram of a monolithic integrated isolation sampling chip provided by another embodiment of the present invention is shown in, for example, Figure 1 and Figure 2 As shown, the output capacitor C can be a silicon capacitor formed on the first die 101. At this time, the isolated DC-DC conversion circuit outputs a DC supply voltage inside the first die 101 to supply power to the isolation sampling circuit. A silicon capacitor refers to a capacitor developed using semiconductor MOS technology. By using a 3D structure, the capacitor surface area can be greatly increased. The output capacitor C can be formed by etching a three-dimensional structure (such as trenches or pores) on the silicon substrate of the die where it is located, and then depositing a conductive layer in the trenches or pores to form electrodes, forming a single MIM or multiple MIM structures (MIM refers to metal / dielectric / metal). The shape of this three-dimensional structure, the number of electrode layers, and the deposition method, etc., can be set according to the actual capacitance value requirements. Figure 3 The circuit structure diagram of a monolithic integrated isolation sampling chip provided by another embodiment of the present invention is shown in, as Figure 3 As shown, in this embodiment, the output capacitor C can also be a chip capacitor integrated inside the package of this isolation sampling chip. At this time, the isolated DC-DC conversion circuit outputs a DC supply voltage inside the chip package to supply power to the isolation sampling circuit.
[0041] According to some optional embodiments, the isolated DC-DC conversion circuit further includes a sampling resistor R, and both ends of the sampling resistor R are connected to the in-phase input terminal and the anti-phase input terminal of the operational amplifier 1012 for detecting an input signal. The sampling resistor R can be formed by the lead frame of the chip input pin. The lead frame is made of metal, such as copper, and different resistance values of the sampling resistor R can be achieved by adjusting different shapes of the metal lead frame. The voltage across the sampling resistor R is input to the operational amplifier 1012, and the output of the operational amplifier 1012 drives the modulator 1013. The modulator 1013 converts the analog signal output by the operational amplifier 1012 into a digital bit stream. The first isolation circuit and the second isolation circuit are used to perform high-frequency modulation / coding on the digital bit stream. The modulated / coded signal is isolated and transmitted through the isolation gate (i.e., the isolation coupling transmission structure), and then demodulated / decoded to restore the digital bit stream. The filter circuit 1022 is used to perform filtering processing on the received digital bit stream and output, for example, an analog differential signal. Among them, the modulator 1013 can adopt a delta-sigma modulator.
[0042] According to some optional embodiments, as Figure 2 shown, the first isolation circuit includes a first transmitting circuit 1014, a second receiving circuit 1015, and a second isolation coupling transmission structure 105; the second isolation circuit includes a first receiving circuit 1024, a first isolation coupling transmission structure 104, and a second transmitting circuit 1025; the first transmitting circuit 1014 and the first receiving circuit 1024 are coupled through the first isolation coupling transmission structure 104 to form a first signal transmission circuit; the second transmitting circuit 1025 and the second receiving circuit 1015 are coupled through the second isolation coupling transmission structure 105 to form a second signal transmission circuit. The first signal transmission circuit transmits a signal from the first die 101 to the second die 102 and can be used to transmit data signals; the second signal transmission circuit transmits a signal from the second die 102 to the first die 101 and can be used to transmit clock signals. The first transmitting circuit 1014 and the second transmitting circuit 1025 are, for example, coding circuits or modulation circuits for performing high-frequency modulation / coding on the digital bit stream, and the first receiving circuit 1024 and the second receiving circuit 1015 are, for example, decoding circuits or demodulation circuits for demodulating / decoding to restore the digital bit stream.
[0043] The first transmission circuit 1014 and the second reception circuit 1015 are disposed, for example, on the first die 101, and the first reception circuit 1024 and the second transmission circuit 1025 are disposed, for example, on the second die 102. The first isolation coupling transmission structure 104 may be a transformer, a capacitor, or a giant magnetoresistance, and the second isolation coupling transmission structure 105 may be a transformer, a capacitor, or a giant magnetoresistance. The first isolation coupling transmission structure 104 is disposed on at least one of the first die 101 and the second die 102, and the second isolation coupling transmission structure 105 is disposed on at least one of the first die 101 and the second die 102. For example, either the first isolation coupling transmission structure 104 or the second isolation coupling transmission structure 105 may be disposed on the first die 101 or on the second die 102, and the first die 101 and the second die 102 are packaged by wire bonding; alternatively, the primary side and the secondary side of either the first isolation coupling transmission structure 104 or the second isolation coupling transmission structure 105 may be respectively disposed on the first die 101 and the second die 102, and the first die 101 and the second die 102 are packaged by stacking.
[0044] The external input and output pins of the isolation sampling chip include a first differential input terminal INP, a second differential input terminal INN, a DC voltage input terminal VDD2, an isolation sampling output terminal, and an input ground terminal GND2 corresponding to the DC voltage input terminal VDD2.
[0045] The lead frames of the first differential input terminal INP and the second differential input terminal INN form a sampling resistor R, and the first differential input terminal INP and the second differential input terminal INN receive an input signal through the sampling resistor R. The non-inverting input terminal and the inverting input terminal of the operational amplifier 1012 are respectively connected to the first differential input terminal INP and the second differential input terminal INN.
[0046] The DC voltage input terminal VDD2 is used to receive a DC input voltage, and the DC input voltage VDD2 is converted into a DC supply voltage VDD1 through an isolation DC-DC conversion circuit to supply power to the isolation sampling circuit inside the chip package. An output ground terminal GND1 corresponding to the DC supply voltage VDD1 is further provided outside the isolation sampling chip.
[0047] The isolation sampling output terminal is used to output a sampling output signal. As Figure 1 - Figure 3 shown, the filtering circuit 1022 is an analog filtering circuit. At this time, the isolation sampling output terminal includes a first isolation sampling output terminal OUTP and a second isolation sampling output terminal OUTN. The first differential output terminal of the analog filtering circuit is connected to the first isolation sampling output terminal OUTP, and the second differential output terminal is connected to the second isolation sampling output terminal OUTN. The first differential output terminal and the second differential output terminal output a differential analog output signal to the first isolation sampling output terminal OUTP and the second isolation sampling output terminal OUTN.
[0048] Figure 4 The schematic circuit diagram of a monolithic integrated isolated sampling chip provided by another embodiment of the present invention is shown in, as Figure 4 shown, the filtering circuit 1022 is an analog filtering circuit, and the second isolated sampling circuit module further includes a differential-to-single-ended circuit 1023. The differential-to-single-ended circuit 1023 is connected to the output end of the analog filtering circuit, and the output end of the differential-to-single-ended circuit 1023 is connected to the isolated sampling output end. At this time, the isolated sampling output end is a single-ended output end OUT, and the output end of the differential-to-single-ended circuit 1023 outputs a single-ended analog output signal to the single-ended output end OUT.
[0049] Figure 5 The schematic circuit diagram of a monolithic integrated isolated sampling chip provided by another embodiment of the present invention is shown in, as Figure 5 shown, the filtering circuit 1022 is a digital filtering circuit, and the output end of the digital filtering circuit is connected to the isolated sampling output end. At this time, the isolated sampling output end is a digital output end DOUT, and the output end of the digital filtering circuit outputs a bit-stream digital output signal to the digital output end DOUT. The digital filtering circuit further includes a clock input terminal CLKIN, and the clock input terminal CLKIN is used to receive an external clock signal.
[0050] In summary, the embodiment of the present invention relates to a monolithic integrated isolated sampling chip, which includes a first die and a second die; the first die is provided with a first conversion circuit module and a first isolated sampling circuit module, and the second die is provided with a second conversion circuit module and a second isolated sampling circuit module. The first conversion circuit module and the second conversion circuit module are coupled through a transformer to form an isolated DC-DC conversion circuit, and the first isolated sampling circuit module and the second isolated sampling circuit module are coupled through an isolation circuit to form an isolated sampling circuit. The monolithic integrated isolated sampling chip provided by the embodiment of the present invention realizes on-chip power supply for the isolated sampling circuit through an internal isolated DC-DC conversion circuit, and at the same time integrates the output capacitor of the isolated DC-DC conversion circuit and the sampling resistor of the isolated sampling circuit inside the chip package, saving the overall chip area and output pins.
[0051] It should be understood that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present utility model (including the claims) is limited to these examples; within the concept of the present utility model, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of one or more embodiments of the present utility model as described above, and they are not provided in detail for the sake of brevity. The above specific embodiments of the present utility model are only used for exemplary illustration or explanation of the principle of the present utility model and do not constitute a limitation to the present utility model. Therefore, any modifications, equivalent replacements, improvements, etc. made without departing from the spirit and scope of the present utility model shall be included within the protection scope of the present utility model. In addition, the appended claims of the present utility model are intended to cover all variations and modifications that fall within the scope and boundaries of the appended claims or equivalent forms of such scope and boundaries.
Claims
1. A monolithic integrated isolation sampling chip, characterized in that, The chip includes a first die and a second die; The first die is provided with a first conversion circuit module and a first isolation sampling circuit module. The first conversion circuit module includes a rectification circuit; the first isolation sampling circuit module includes an operational amplifier and a modulator connected in sequence; The second die is provided with a second conversion circuit module and a second isolation sampling circuit module. The second conversion circuit module includes a drive circuit; the second isolation sampling circuit module includes a filter circuit; the first conversion circuit module and the second conversion circuit module are coupled by a transformer to form an isolated DC-DC conversion circuit, and the transformer is disposed on at least one of the first die and the second die; the first isolation sampling circuit module and the second isolation sampling circuit module are coupled by an isolation circuit to form an isolation sampling circuit; the isolation circuit includes a first isolation circuit and a second isolation circuit, the first isolation circuit is disposed on at least one of the first die and the second die, and the second isolation circuit is disposed on at least one of the first die and the second die; the isolated DC-DC conversion circuit outputs a DC supply voltage inside the chip to supply power to the isolation sampling circuit; The isolated DC-DC conversion circuit further includes an output capacitor; The output capacitor is a silicon capacitor formed on the first die, and the isolated DC-DC conversion circuit outputs a DC supply voltage inside the first die to supply power to the isolation sampling circuit; or, The output capacitor is a chip capacitor integrated inside the chip package.
2. The chip according to claim 1, characterized in that, The chip includes a first differential input terminal and a second differential input terminal; The lead frames of the first differential input terminal and the second differential input terminal form a sampling resistor, and the first differential input terminal and the second differential input terminal receive an input signal through the sampling resistor; The non-inverting input terminal and the inverting input terminal of the operational amplifier are respectively connected to the first differential input terminal and the second differential input terminal.
3. The chip according to claim 2, characterized in that, The chip further includes an isolation sampling output terminal and a DC voltage input terminal; The isolation sampling output terminal outputs a sampling output signal; The DC voltage input terminal receives a DC input voltage, and the DC input voltage is converted into a DC supply voltage through the isolated DC-DC conversion circuit.
4. The chip according to any one of claims 1 to 3, characterized in that, The first isolation circuit includes a first transmission circuit, a second reception circuit, and a second isolation coupling transmission structure; The second isolation circuit includes a first reception circuit, a first isolation coupling transmission structure, and a second transmission circuit; The first transmission circuit and the first reception circuit are coupled by the first isolation coupling transmission structure to form a first signal transmission circuit; The second transmission circuit and the second reception circuit are coupled by the second isolation coupling transmission structure to form a second signal transmission circuit; the first signal transmission circuit transmits a signal from the first die to the second die, and the second signal transmission circuit transmits a signal from the second die to the first die.
5. The chip according to claim 4, wherein The first transmission circuit and the second reception circuit are disposed on the first die, and the first reception circuit and the second transmission circuit are disposed on the second die; The first isolation coupling transmission structure is disposed on at least one of the first die and the second die, and the second isolation coupling transmission structure is disposed on at least one of the first die and the second die.
6. The chip according to claim 5, wherein The first isolation coupling transmission structure is a transformer, a capacitor, or a giant magnetoresistance, and the second isolation coupling transmission structure is a transformer, a capacitor, or a giant magnetoresistance.
7. The chip according to claim 3, characterized in that, The filtering circuit is an analog filtering circuit. The isolation sampling output terminal includes a first isolation sampling output terminal and a second isolation sampling output terminal. The first differential output terminal of the analog filtering circuit is connected to the first isolation sampling output terminal, and the second differential output terminal is connected to the second isolation sampling output terminal; The first differential output terminal and the second differential output terminal output differential analog output signals.
8. The chip according to claim 3, characterized in that, The filtering circuit is an analog filtering circuit. The second isolation sampling circuit module further includes a differential-to-single-ended circuit, and the differential-to-single-ended circuit is connected to the output terminal of the analog filtering circuit; The output terminal of the differential-to-single-ended circuit is connected to the isolation sampling output terminal, and the output terminal outputs a single-ended analog output signal.
9. The chip according to claim 3, characterized in that, The filtering circuit is a digital filtering circuit; The output terminal of the digital filtering circuit is connected to the isolation sampling output terminal, and the output terminal outputs a bitstream digital output signal.
10. The chip according to claim 9, wherein The digital filtering circuit further includes a clock input terminal, and the clock input terminal receives a clock signal.