High holding current transient voltage suppression device

Abstract

The utility model provides a high holding current transient voltage suppression device, which is characterized in that an NPN structure and a PNPN structure (SCR characteristic) are connected in parallel, the breakdown voltage of the NPN structure is lower than the breakdown voltage of the PNPN structure (SCR characteristic), the current path is the NPN structure when the current is low, and the PNPN structure (SCR characteristic) is triggered when the clamping voltage at the two ends of the NPN structure is greater than the breakdown voltage of the PNPN structure (SCR characteristic), so that the high holding current transient voltage suppression device is realized. A current path is converted from an NPN structure to a PNPN structure (SCR characteristic), so that the problems that the clamping voltage of a transient voltage suppression device with the existing diode characteristic and the traditional NPN structure characteristic is high, and the latching risk exists although the clamping voltage of the PNPN structure (SCR characteristic) is low are solved.

Description

Technical Field

[0001] Embodiments of the present application belong to the field of semiconductor technology, and particularly relate to a high-holding-current transient voltage suppression device. Background Art

[0002] Surges, static electricity, and transient voltages cause a relatively large proportion of damage to electronic products. Therefore, a transient voltage suppression device with excellent performance is crucial for the protection of electronic products. Although diode characteristics and traditional NPN-characteristic transient voltage suppression devices can discharge surges, static electricity, and transient voltages, due to their high clamping voltages, the effect on protecting the chips at the backend is not ideal, resulting in damage to the chips protected at the backend. Although the PNPN structure (SCR characteristic) has a low clamping voltage, when used at a continuously powered port, there will be a latching phenomenon after triggering the PNPN structure (SCR characteristic), leading to the failure of the backend function or damage to the transient voltage suppression device itself. Summary of the Invention

[0003] To solve or alleviate the problems in the prior art, the present application provides a high-holding-current transient voltage suppression device to solve the problems that the clamping voltages of existing diode-characteristic and traditional NPN-characteristic transient voltage suppression devices are high, and although the PNPN structure (SCR characteristic) has a low clamping voltage, there is a risk of latching.

[0004] The present application provides a high-holding-current transient voltage suppression device, including: an NPN structure and a PNPN structure;

[0005] Both the NPN structure and the PNPN structure are disposed in a silicon structure;

[0006] The NPN structure and the PNPN structure are arranged in parallel;

[0007] One end of the NPN structure and one end of the PNPN structure are respectively connected to a voltage input port, and the other end of the NPN structure and the other end of the PNPN structure are respectively connected to a ground terminal;

[0008] The breakdown voltage of the NPN structure is lower than that of the PNPN structure. When the voltage input at the voltage input end is greater than a preset voltage, the NPN structure conducts, and the current input at the voltage input end flows through the NPN structure; when the clamping voltage across the NPN structure is greater than the breakdown voltage of the PNPN structure, the PNPN structure conducts, and the current input at the voltage input end changes from flowing through the NPN structure to flowing through the PNPN structure.

[0009] As a preferred embodiment of the present application, the NPN structure includes a first well region, a first implantation region, a second implantation region, and a third implantation region;

[0010] The first implantation region and the second implantation region are arranged at intervals in the first well region. The third implantation region is arranged in the silicon structure, and the third implantation region is arranged adjacent to the first well region. The third implantation region is communicated with the voltage input terminal.

[0011] Wherein, both the first well region and the first implantation region are of a first doping type, and both the second implantation region and the third implantation region are of a second doping type.

[0012] As a preferred embodiment of the present application, the PNPN structure includes the second well region, the third well region, the fourth implantation region, the fifth implantation region and the sixth implantation region;

[0013] The fourth implantation region is arranged in the second well region. The fifth implantation region and the sixth implantation region are arranged at intervals in the third well region. The second well region and the third well region are arranged at intervals, and the second well region is arranged between the third well region and the third implantation region;

[0014] The fourth implantation region, the third well region and the sixth implantation region are all of a first doping type, and the second well region and the fifth implantation region are both of a second doping type;

[0015] Wherein, the fourth implantation region is connected to the voltage input terminal, and both the fifth implantation region and the sixth implantation region are connected to the ground terminal.

[0016] As a preferred embodiment of the present application, it further includes a seventh implantation region;

[0017] The seventh implantation region is arranged between the first well region and the third implantation region; or,

[0018] The seventh implantation region is arranged on one side of the first well region close to the third implantation region.

[0019] The seventh implantation region is of a first doping type.

[0020] As a preferred embodiment of the present application, it further includes an eighth implantation region;

[0021] The eighth implantation region is arranged between the second well region and the third well region;

[0022] The eighth implantation region is of a first doping type.

[0023] As a preferred embodiment of the present application, the first doping type is P-type, and the second doping type is N-type.

[0024] As a preferred embodiment of the present application, the silicon structure is a substrate or an epitaxial layer.

[0025] The present application provides a high-holding-current transient voltage suppression device. Specifically, an NPN structure is connected in parallel with a PNPN structure (SCR characteristic), and the breakdown voltage of the NPN structure is lower than that of the PNPN structure (SCR characteristic). When the current is small, the current path is the NPN structure. When the clamping voltage across the NPN structure is greater than the breakdown voltage of the PNPN structure (SCR characteristic), the PNPN structure (SCR characteristic) is triggered, and the current path is converted from the NPN structure to the PNPN structure (SCR characteristic), thereby solving the problem that the clamping voltage of existing diodes and traditional NPN-characteristic transient voltage suppression devices is high, and although the PNPN structure (SCR characteristic) has a low clamping voltage, there is a risk of latching. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments and descriptions thereof of the present application are used to explain the present application and do not constitute an improper limitation of the present application. Some specific embodiments of the present application will be described in detail hereinafter with reference to the drawings in an exemplary rather than restrictive manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0027] Figure 1 is a cross-sectional schematic diagram of a high-holding-current transient voltage suppression device provided by an embodiment of the present application;

[0028] Figure 2 is a cross-sectional schematic diagram of a high-holding-current transient voltage suppression device provided by an embodiment of the present application;

[0029] Figure 3 is an equivalent circuit diagram of a high-holding-current transient voltage suppression device provided by an embodiment of the present application;

[0030] Figure 4 is a comparison curve of the voltage-current relationship between a transient voltage suppression device in the prior art and the high-holding-current transient voltage suppression device provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without making creative efforts shall fall within the protection scope of the present application.

[0032] Such as Figure 1As shown in the figure, the present application provides a high-holding-current transient voltage suppression device, including: an NPN structure and a PNPN structure;

[0033] Both the NPN structure and the PNPN structure are disposed in a silicon structure;

[0034] The NPN structure and the PNPN structure are arranged in parallel;

[0035] One end of the NPN structure and one end of the PNPN mechanism are respectively connected to a voltage input port, and the other end of the NPN structure and the other end of the PNPN structure are respectively connected to a ground terminal 13;

[0036] The breakdown voltage of the NPN structure is lower than that of the PNPN structure. When the voltage input at the voltage input end is greater than a preset voltage, the NPN structure conducts, and the current input at the voltage input end flows through the NPN structure; when the clamping voltage across the NPN structure is greater than the breakdown voltage of the PNPN structure, the PNPN structure conducts, and the current input at the voltage input end changes from flowing through the NPN structure to flowing through the PNPN structure.

[0037] In an embodiment of the present application, the silicon structure is a substrate or an epitaxial layer.

[0038] Specifically, in the present application, the NPN structure is connected in parallel with the PNPN structure (SCR characteristic). At the same time, the breakdown voltage of the NPN structure is lower than that of the PNPN structure (SCR characteristic). When the current is small, the current path is the NPN structure. When the clamping voltage across the NPN structure is greater than the breakdown voltage of the PNPN structure (SCR characteristic), the PNPN structure (SCR characteristic) is triggered, and the current path is converted from the NPN structure to the PNPN structure (SCR characteristic), thereby solving the problems that the clamping voltage of the existing diode characteristic and the traditional NPN characteristic transient voltage suppression device is high, and although the clamping voltage of the PNPN structure (SCR characteristic) is low, there is a risk of latch-up.

[0039] That is to say, the present application improves the holding current of the traditional PNPN structure (SCR characteristic), so that the transient voltage suppression device can not only meet the low clamping voltage, but also does not trigger latch-up during use.

[0040] Specifically, as a preferred embodiment of the present application, the NPN structure includes a first well region 01, a first implantation region 02, a second implantation region 03, and a third implantation region 04;

[0041] The first implantation region 02 and the second implantation region 03 are arranged at intervals in the first well region 01. The third implantation region 04 is arranged in the silicon structure, and the third implantation region 04 is adjacent to the first well region 01. The third implantation region 04 is communicated with the voltage input terminal.

[0042] Wherein, the first well region 01 and the first implantation region 02 are both of the first doping type, and the second implantation region 03 and the third implantation region 04 are both of the second doping type.

[0043] As a preferred embodiment of the present application, the PNPN structure includes the second well region 05, the third well region 06, the fourth implantation region 07, the fifth implantation region 08 and the sixth implantation region 09;

[0044] The fourth implantation region 07 is arranged in the second well region 05. The fifth implantation region 08 and the sixth implantation region 09 are arranged at intervals in the third well region 06. The second well region 05 and the third well region 06 are arranged at intervals, and the second well region 05 is arranged between the third well region 06 and the third implantation region 04;

[0045] The fourth implantation region 07, the third well region 06 and the sixth implantation region 09 are all of the first doping type, and the second well region 05 and the fifth implantation region 08 are both of the second doping type;

[0046] Wherein, the fourth implantation region 07 is connected to the voltage input terminal, and the fifth implantation region 08 and the sixth implantation region 09 are both connected to the ground terminal 13.

[0047] As a preferred embodiment of the present application, it further includes a seventh implantation region 10;

[0048] The seventh implantation region 10 is arranged between the first well region 01 and the third implantation region 04;

[0049] As a preferred embodiment of the present application, it further includes an eighth implantation region 11;

[0050] The eighth implantation region 11 is arranged between the second well region 05 and the third well region 06;

[0051] The eighth implantation region 11 is of the first doping type.

[0052] As a preferred embodiment of the present application, the first doping type is P-type, and the second doping type is N-type.

[0053] As a preferred embodiment of the present application, the silicon structure is a substrate.

[0054] In the embodiment of the present application, the four-layer PNPN structure has SCR characteristics, and SCR is a thyristor.

[0055] As a preferred embodiment of the present application, it further includes a seventh implantation region 10;

[0056] The seventh implantation region 10 is disposed between the first well region 01 and the third implantation region 04; or,

[0057] The seventh implantation region 10 is disposed on a side of the first well region 01 close to the third implantation region 04.

[0058] The seventh implantation region 10 is of a first doping type.

[0059] As a preferred embodiment of the present application, it further includes an eighth implantation region 11;

[0060] The eighth implantation region 11 is disposed between the second well region 05 and the third well region 06;

[0061] The eighth implantation region 11 is of a first doping type.

[0062] As Figure 2 shown, the seventh implantation region 10 is disposed on a side of the first well region 01 close to the third implantation region 04.

[0063] The seventh implantation region 10 is of a first doping type.

[0064] In the embodiment of the present application, the seventh implantation region 10 and the eighth implantation region 11 are mainly used to adjust the voltage. When the NPN structure is triggered, the on-resistances of the NPN structure paths are respectively related to the areas of the second implantation region 03 and the third implantation region 04. Therefore, the on-resistance can be adjusted by adjusting the areas of the second implantation region 03 and the third implantation region 04, thereby adjusting the maximum holding current; or the maximum holding current can be adjusted by adjusting the trigger voltage of the PNPN structure (by adjusting the implantation concentration of the eighth implantation region 11).

[0065] In the present application, the NPN structure is connected in parallel with the PNPN structure, and the breakdown voltage of the NPN structure is lower than that of the PNPN structure. When the current is small, the current path is the NPN structure. When the clamping voltage at both ends of the NPN structure is greater than the breakdown voltage of the PNPN structure, the PNPN structure is triggered, and the current path is converted from the NPN structure to the PNPN structure.

[0066] As Figure 3 shown, it can be seen from the equivalent circuit diagram that in the present application, the NPN structure is connected in parallel with the PNPN structure (SCR characteristic), and the path of the entire device current in the forward direction from the anode to the cathode selectively passes through the NPN structure or the PNPN structure (SCR characteristic), and the path of the entire device current in the reverse direction from the cathode to the anode passes through the PN structure. As Figure 4As shown, the comparison curve of the voltage-current relationship between the traditional PNPN structure and the PNPN structure of the present application. The holding current of a high-holding-current transient voltage suppression device in the prior art is related to the PNPN structure itself, and it is difficult to achieve a very high holding current. The high-holding-current transient voltage suppression device in the present application improves the holding current through different current path conversions. The holding current of the PNPN structure provided by the embodiments of the present application is higher than that of the traditional PNPN structure, and when the clamping voltage at both ends of the NPN structure is greater than the breakdown voltage of the PNPN structure (SCR characteristic), the PNPN structure (SCR characteristic) is triggered. Therefore, the present application greatly reduces the latching risk.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A high-holding-current transient voltage suppression device, characterized in that Including: NPN structure and PNPN structure; Both the NPN structure and the PNPN structure are arranged in a silicon structure; The NPN structure and the PNPN structure are arranged in parallel; One end of the NPN structure and one end of the PNPN structure are respectively connected to a voltage input port, and the other end of the NPN structure and the other end of the PNPN structure are respectively connected to a ground terminal; The breakdown voltage of the NPN structure is lower than that of the PNPN structure. When the voltage input at the voltage input end is greater than a preset voltage, the NPN structure conducts, and the current input at the voltage input end flows through the NPN structure; when the clamping voltage across the NPN structure is greater than the breakdown voltage of the PNPN structure, the PNPN structure conducts, and the current input at the voltage input end changes from flowing through the NPN structure to flowing through the PNPN structure.

2. The high-holding-current transient voltage suppression device according to claim 1, wherein The NPN structure includes a first well region, a first implantation region, a second implantation region, and a third implantation region; The first implantation region and the second implantation region are arranged at intervals in the first well region, the third implantation region is arranged in the silicon structure, and the third implantation region is adjacent to the first well region and is in communication with the voltage input end; Wherein, both the first well region and the first implantation region are of a first doping type, and both the second implantation region and the third implantation region are of a second doping type.

3. The high-holding-current transient voltage suppression device according to claim 2, wherein The PNPN structure includes a second well region, a third well region, a fourth implantation region, a fifth implantation region, and a sixth implantation region; The fourth implantation region is arranged in the second well region, the fifth implantation region and the sixth implantation region are arranged at intervals in the third well region, the second well region and the third well region are arranged at intervals, and the second well region is arranged between the third well region and the third implantation region; The fourth implantation region, the third well region, and the sixth implantation region are all of a first doping type, and both the second well region and the fifth implantation region are of a second doping type; Wherein, the fourth implantation region is connected to the voltage input end, and both the fifth implantation region and the sixth implantation region are connected to the ground terminal.

4. The high-holding-current transient voltage suppression device according to claim 3, wherein, It further includes a seventh implantation region; The seventh implantation region is arranged between the first well region and the third implantation region; or, The seventh implantation region is arranged on one side of the first well region close to the third implantation region; The seventh implantation region is of a first doping type.

5. The high-holding-current transient voltage suppression device according to claim 3, characterized in that It further includes an eighth implantation region; The eighth implantation region is arranged between the second well region and the third well region; The eighth implantation region is of a first doping type.

6. A high-holding-current transient voltage suppression device according to any one of claims 2-5, characterized in that, The first doping type is P-type, and the second doping type is N-type.

7. The high-holding-current transient voltage suppression device according to claim 6, wherein The silicon structure is a substrate or an epitaxial layer.

Images