Large-current filtering surge voltage transient suppression circuit

Abstract

The utility model relates to the technical field of surge voltage suppression of airborne equipment, and discloses a high-current filtering surge voltage transient suppression circuit, which comprises a filter circuit connected with a power supply input end and used for filtering out common-mode interference and differential-mode interference in the circuit; the starting circuit is used for limiting surge current during starting by controlling the conduction speed of the field-effect tube; the field effect transistor control circuit is used for adjusting the conduction degree of the field effect transistor by controlling the grid voltage of the field effect transistor and realizing effective suppression on the surge current; the surge voltage sampling circuit is connected with the output end of the power supply and is used for monitoring surge voltage in the power supply in real time; according to the surge voltage suppression circuit, the input voltage is filtered, and the chip U1 is used for controlling the field effect transistor and bearing the surge voltage, so that normal work of post-stage equipment is ensured, the problem that a traditional surge voltage suppression circuit does not have a filtering function is solved, and the problem that when 20A current flows through the traditional surge voltage suppression circuit, an NMOS transistor bears too large power consumption and is easy to damage is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of surge voltage suppression for airborne equipment, and particularly to a large-current filtering surge voltage transient suppression circuit. Background Technique

[0002] With the wide use of the power supply system and electronic devices of airborne equipment, the power supply and electronic devices may be subjected to overvoltage surge impacts, and the resulting hazards have attracted a great deal of attention and discussion. During the use of a circuit, when suddenly struck by lightning, connecting or disconnecting an inductive load or other large loads, a very high instantaneous overvoltage is generated, usually within milliseconds to microseconds. This instantaneous overvoltage is called a surge voltage and is a kind of instantaneous interference. The surge voltage impact may cause data transmission distortion in a communication system or an electronic system, and even cause component damage or short circuit of electronic devices. However, inside the chip, the generation of surge voltage may cause damage to the chip and abnormal operation.

[0003] At present, among similar surge suppressor products on the market, the current is usually 10A or less and there is no filtering function. A single NMOS transistor is used to suppress the voltage signal output by the boost circuit to a predetermined range and then output to supply an external circuit. The NMOS transistor will bear an excessive load. Therefore, when a 20A current passes through, the NMOS transistor is easily damaged due to excessive power consumption.

[0004] How to design a surge voltage suppression that can withstand a larger current and has higher reliability has become the focus of attention. Therefore, we need to propose a large-current filtering surge voltage transient suppression circuit, mainly aiming at the deficiencies of the traditional surge voltage suppression circuit without a filtering function and a current-carrying capacity of 20A, to provide a circuit that can withstand a filtered large current to suppress the surge voltage, taking into account high power and circuit reliability. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a large-current filtering surge voltage transient suppression circuit, which filters the input voltage and uses the chip U1 to control the field-effect transistor to withstand the surge voltage, ensuring the normal operation of the subsequent equipment, so as to solve the problems proposed in the above background technique.

[0006] To achieve the above purpose, the utility model provides the following technical solution: A large-current filtering surge voltage transient suppression circuit, comprising:

[0007] A filtering circuit connected to the power input terminal and used to filter out common-mode interference and differential-mode interference in the circuit;

[0008] A startup circuit that limits the surge current at startup by controlling the conduction speed of the field-effect transistor;

[0009] A field effect transistor control circuit that adjusts the conduction degree of a field effect transistor by controlling the gate voltage of the field effect transistor and effectively suppresses surge current;

[0010] A surge voltage sampling circuit connected to the power supply output terminal for real-time monitoring of surge voltage in the power supply;

[0011] The filter circuit is electrically connected to the startup circuit, and both the field effect transistor control circuit and the surge voltage sampling circuit are connected to the startup circuit.

[0012] Preferably, the filter circuit includes a common mode inductor L1, a differential mode capacitor C2 is connected in parallel on one side of the common mode inductor L1, and a differential mode capacitor C3, a differential mode capacitor C4, and a series-connected common mode capacitor C5 and common mode capacitor C6 are connected in parallel on the other side of the common mode inductor L1.

[0013] Preferably, the startup circuit includes a chip U1, a resistor R8 is connected to the 1st pin of the chip U1, and one end of the resistor R8 is connected to one end of the common mode capacitor C5; a resistor R33 is connected to the 4th pin of the chip U1, and one end of the resistor R33 is connected to one end of the common mode capacitor C6.

[0014] Preferably, the field effect transistor control circuit includes a field effect transistor Q1 and a field effect transistor Q2 connected in parallel. The source S of the field effect transistor Q1 is connected to the source S of the field effect transistor Q2 and is connected to the 7th pin of the chip U1. The connection terminal after connecting the drain D of the field effect transistor Q1 and the drain D of the field effect transistor Q2 is connected to the resistor R8. The connection terminal after connecting the gate G of the field effect transistor Q1 and the gate G of the field effect transistor Q2 is connected with a resistor R1 and a resistor R2 connected in parallel, and the connection terminal of the resistor R1 and the resistor R2 is connected to the 8th pin of the chip U1.

[0015] Preferably, the surge voltage sampling circuit includes a resistor R20 and a resistor R27 respectively connected to the 6th pin of the chip U1. One end of the resistor R20 is connected to the 7th pin of the chip U1, and one end of the resistor R27 is connected to the resistor R33.

[0016] Preferably, a capacitor C14 and a capacitor C7 are connected between the 3rd pin and the 7th pin of the chip U1, and the capacitor C14 is connected to the resistor R33.

[0017] Preferably, a capacitor C1 is also connected to the 8th pin of the chip U1, and the capacitor C1 is connected to the resistor R33.

[0018] Compared with the prior art, the beneficial effects of the present utility model are:

[0019] 1. Through the design of the filter circuit, when differential-mode and common-mode interference signals and surge voltage (80V / 50ms) pass through the product, the filter circuit first filters out the common-mode and differential-mode interference signals, overcoming the problem that the traditional surge voltage suppression circuit has no filtering function.

[0020] 2. Through the design of the field-effect transistor control circuit, the voltage between the gate and drain of the field-effect transistor in the field-effect transistor control circuit decreases, the resistance between the drain and source of the field-effect transistor increases, and the field-effect transistor consumes the excess energy load; when the voltage is normal, the voltage between the gate and drain of the field-effect transistor increases, and the resistance between the drain and source of the field-effect transistor returns to normal, overcoming the problem that when the traditional surge voltage suppression circuit conducts a 20A current, the NMOS transistor is easily damaged due to excessive power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a circuit diagram of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0023] Please refer to Figure 1 , the present utility model provides a technical solution: a large-current filtering surge voltage transient suppression circuit, including:

[0024] A filter circuit connected to the power input terminal for filtering out common-mode interference and differential-mode interference in the circuit; providing a clean power signal for subsequent surge suppression.

[0025] A startup circuit that limits the surge current at startup by controlling the conduction speed of the field-effect transistor; the startup circuit plays a key role when the power supply starts up and is responsible for controlling the suppression of the surge current. The startup circuit can gradually increase the conduction time of the field-effect transistor to make the current rise gradually, thus avoiding the generation of surge current.

[0026] A field-effect transistor control circuit that adjusts the conduction degree of the field-effect transistor by controlling the gate voltage of the field-effect transistor and effectively suppresses the surge current; when a surge voltage appears, quickly adjusts the conduction state of the field-effect transistor to limit the surge voltage within a safe range. The field-effect transistor control circuit is combined with the startup circuit to achieve more precise control of the surge current.

[0027] A surge voltage sampling circuit connected to the power output terminal for real-time monitoring of surge voltage in the power supply; the surge voltage sampling circuit can also convert the monitored surge voltage into a signal that can be processed for subsequent circuit use.

[0028] By filtering the input voltage and using chip U1 to control the field effect transistor to withstand the surge voltage, the normal operation of the subsequent equipment is ensured.

[0029] The filtering circuit is electrically connected to the startup circuit, and both the field effect transistor control circuit and the surge voltage sampling circuit are connected to the startup circuit.

[0030] When there are differential-mode and common-mode interference signals and surge voltage (80V / 50ms) passing through the power supply, the filtering circuit first filters out the common-mode and differential-mode interference signals;

[0031] And the voltage between the gate and drain of the field effect transistor in the field effect transistor control circuit decreases, the resistance between the drain and source of the field effect transistor increases, and the field effect transistor consumes the excess energy load;

[0032] When the voltage is normal, the voltage between the gate and drain of the field effect transistor increases, and the resistance between the drain and source of the field effect transistor returns to normal;

[0033] When the 28V and 20A circuits are working normally, the sampling circuit of chip U1 calculates that the output voltage is normal, the field effect transistor conducts normally, and the surge voltage suppression circuit is in a conducting state.

[0034] When a surge voltage higher than the rated voltage is generated in the 28V and 20A circuits, through the voltage sampling circuit of chip U1, the obtained voltage is higher than the set reference voltage. At this time, chip U1 controls the voltage between the gate and source of the field effect transistor to decrease, the on-resistance increases, and the excess energy is consumed, so that the voltage at the output end of the circuit meets the circuit requirements.

[0035] The filtering circuit includes a common-mode inductor L1. One side of the common-mode inductor L1 is connected in parallel with a differential-mode capacitor C2, that is, one end of the differential-mode capacitor C2 is connected to the positive input terminal of the power supply, and the other end of the differential-mode capacitor C2 is connected to the negative input terminal of the power supply. The other side of the common-mode inductor L1 is connected in parallel with a differential-mode capacitor C3, a differential-mode capacitor C4, and a series-connected common-mode capacitor C5 and common-mode capacitor C6. The connection terminals of the common-mode capacitor C5 and the common-mode capacitor C6 are grounded.

[0036] When there is common-mode interference entering, the circuit composed of the common-mode capacitor C5, the common-mode capacitor C6, and the common-mode inductor L1 will play a role in filtering out the common-mode interference; when differential-mode interference enters, the differential-mode capacitor C2, the differential-mode capacitor C3, and the differential-mode capacitor C4 will play a role in filtering out the differential-mode interference.

[0037] The startup circuit includes chip U1. A resistor R8 is connected to pin 1 of chip U1, and one end of resistor R8 is connected to one end of common-mode capacitor C5. A resistor R33 is connected to pin 4 of chip U1, and one end of resistor R33 is connected to one end of common-mode capacitor C6.

[0038] The field-effect transistor control circuit includes field-effect transistors Q1 and Q2 arranged in parallel. The source S of field-effect transistor Q1 is connected to the source S of field-effect transistor Q2 and is connected to pin 7 of chip U1. The connection terminal after connecting the drain D of field-effect transistor Q1 and the drain D of field-effect transistor Q2 is connected to resistor R8. A parallel-connected resistor R1 and resistor R2 are connected to the connection terminal after connecting the gate G of field-effect transistor Q1 and the gate G of field-effect transistor Q2, and the connection terminal of resistor R1 and resistor R2 is connected to pin 8 of chip U1.

[0039] The surge voltage sampling circuit includes resistor R20 and resistor R27 respectively connected to pin 6 of chip U1. One end of resistor R20 is connected to pin 7 of chip U1, and one end of resistor R27 is connected to resistor R33.

[0040] A capacitor C14 and a capacitor C7 are connected between pin 3 and pin 7 of chip U1, and capacitor C14 is connected to resistor R33.

[0041] A capacitor C1 is also connected to pin 8 of chip U1, and capacitor C1 is connected to resistor R33.

[0042] When the 28V and 20A circuits are working normally, resistor R8 in the circuit limits the current and supplies power to chip U1. The GATE pin (pin 8) of chip U1 charges the gates G of field-effect transistors Q1 and Q2. When the gate G is charged to a certain voltage, the resistors R8 at the source S, resistor R20, and resistor R27 at the drain D can reach 1 - 9 mΩ. At this time, field-effect transistors Q1 and Q2 are in a fully conducting state. The selected field-effect transistors Q1 and Q2 can withstand at least 10A of current.

[0043] Resistor R20 and resistor R27 divide the voltage. The FB pin (pin 6) of chip U1 obtains a reference voltage and compares it with the reference voltage of chip U1. When the reference voltage of FB (pin 6) is less than the reference voltage of chip U1, the circuit is normally powered on.

[0044] When a surge voltage higher than 36V is generated in the 28V and 20A circuits, resistors R20 and R27 divide the output voltage, and the reference voltage is obtained at the pin FB (pin 6) of chip U1. This reference voltage is compared with the reference voltage of chip U1. When the reference voltage at FB (pin 6) is greater than the reference voltage of chip U1, the voltage at the GATE pin (pin 8) of chip U1 pulls down the voltage at the gate G of the NMOS transistors (field effect transistors Q1 and Q2). At this time, the resistance between the source S and the drain D increases, consuming the excess power, and the output stabilizes at 36V, protecting the subsequent circuit. When the input voltage is lower than 36V, the voltage at the gate G of field effect transistors Q1 and Q2 increases, the on-resistance decreases, and the circuit returns to normal. A reasonable resistance value can also be selected for the reference voltage to make the output voltage meet the voltage requirements specified in the circuit.

[0045] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A large current filtering and surge voltage transient suppression circuit, characterized in that, Comprising: A filtering circuit connected to the power input terminal and used to filter out common-mode interference and differential-mode interference in the circuit; A startup circuit that limits the inrush current during startup by controlling the conduction speed of the field-effect transistor; A field-effect transistor control circuit that adjusts the conduction degree of the field-effect transistor by controlling the gate voltage of the field-effect transistor and effectively suppresses the inrush current; A surge voltage sampling circuit connected to the power output terminal and used to monitor the surge voltage in the power supply in real time; The filtering circuit is electrically connected to the startup circuit, and both the field-effect transistor control circuit and the surge voltage sampling circuit are connected to the startup circuit.

2. The high-current filtering surge voltage transient suppression circuit according to claim 1, wherein: The filtering circuit includes a common-mode inductor L1, a differential-mode capacitor C2 is connected in parallel on one side of the common-mode inductor L1, a differential-mode capacitor C3, a differential-mode capacitor C4, and a series-connected common-mode capacitor C5 and common-mode capacitor C6 are connected in parallel on the other side of the common-mode inductor L1.

3. The large-current filtering surge voltage transient suppression circuit according to claim 2, wherein: The startup circuit includes a chip U1, a resistor R8 is connected to the 1st pin of the chip U1, and one end of the resistor R8 is connected to one end of the common-mode capacitor C5; a resistor R33 is connected to the 4th pin of the chip U1, and one end of the resistor R33 is connected to one end of the common-mode capacitor C6.

4. A high-current filtering surge voltage transient suppression circuit according to claim 3, characterized in that: The field-effect transistor control circuit includes a parallel-set field-effect transistor Q1 and field-effect transistor Q2. The source S of the field-effect transistor Q1 is connected to the source S of the field-effect transistor Q2 and connected to the 7th pin of the chip U1. The connection terminal after the drain D of the field-effect transistor Q1 is connected to the drain D of the field-effect transistor Q2 is connected to the resistor R8. A parallel-set resistor R1 and resistor R2 are connected to the connection terminal after the gate G of the field-effect transistor Q1 is connected to the gate G of the field-effect transistor Q2, and the connection terminal of the resistor R1 and resistor R2 is connected to the 8th pin of the chip U1.

5. A high-current filtering surge voltage transient suppression circuit according to claim 4, characterized in that: The surge voltage sampling circuit includes a resistor R20 and a resistor R27 respectively connected to the 6th pin of the chip U1. One end of the resistor R20 is connected to the 7th pin of the chip U1, and one end of the resistor R27 is connected to the resistor R33.

6. A large current filtering surge voltage transient suppression circuit according to claim 5, characterized in that: A capacitor C14 and a capacitor C7 are connected between the 3rd pin and the 7th pin of the chip U1, and the capacitor C14 is connected to the resistor R33.

7. A large-current filtering surge voltage transient suppression circuit according to claim 6, characterized in that: A capacitor C1 is also connected to the 8th pin of the chip U1, and the capacitor C1 is connected to the resistor R33.

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