Power management circuit based on low-delay low-power-consumption PWI control

Abstract

The utility model relates to the technical field of power supply circuits, in particular to a power supply management circuit based on low-delay low-power-consumption PWI control, which comprises a main processor, a power supply management unit, a voltage stabilizer and a PWI interface module, the power supply management unit comprises a power supply management circuit, and the voltage stabilizer comprises an error amplifier circuit; the error amplifier circuit comprises a voltage divider VFB and a compensation circuit, the voltage divider VFB is electrically connected with a resistor R6 and a resistor R7, and the compensation circuit comprises a triode Q1. According to the utility model, each switch mode power supply is integrated with an error amplifier, the error amplifier compares the voltage of the feedback voltage divider VFB with the internal reference voltage VREF and sets the duty ratio PWM, and the compensation network is connected between the input FB and the output COMP of the error amplifier, so that the output voltage can be well adjusted under all line and load conditions, and the output voltage can be effectively adjusted. Therefore, loss is reduced.

Description

Technical Field

[0001] The utility model relates to a power management circuit, in particular to a power management circuit based on low-delay and low-power PWI control, belonging to the technical field of power circuits. Background Art

[0002] PWI is a system-level energy management method designed specifically for battery-powered devices. It realizes adaptive voltage regulation and state control, aiming to reduce the power consumption of devices and extend the battery usage time through fine-grained power management strategies.

[0003] The power management circuit based on low-delay and low-power PWI control further optimizes the power management efficiency and reduces the response time on this basis to meet application scenarios with higher performance requirements. In the power management circuit based on low-delay and low-power PWI control, a variable or adjustable power supply voltage is required. For example, when PWM modulation is impossible due to EMI reasons, this can be the power supply for a DC motor. In particular, class A and class A / B amplifiers with only a very small load have large losses and cannot meet the usage requirements.

[0004] Therefore, it is urgent to improve the power management circuit based on low-delay and low-power PWI control to solve the above existing problems. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a power management circuit based on low-delay and low-power PWI control. Each switching-mode power supply integrates an error amplifier. The error amplifier compares the voltage of the feedback voltage divider VFB with its internal reference voltage VREF and sets the duty cycle PWM. A compensation network is connected between the input FB and the output COMP of the error amplifier, which can ensure good regulation of the output voltage under all line and load conditions, thereby reducing losses.

[0006] To achieve the above purpose, the main technical solutions adopted by the utility model include:

[0007] A power management circuit based on low-delay and low-power PWI control includes a main processor, a power management unit, a voltage regulator, and a PWI interface module. The power management unit includes a power management circuit, and the voltage regulator includes an error amplifier circuit;

[0008] The error amplifier circuit includes a voltage divider VFB and a compensation circuit. A resistor R6 and a resistor R7 are electrically connected to the voltage divider VFB. The voltage divider VFB is electrically connected to the compensation circuit through a resistor R8. The compensation circuit includes a triode Q1. The input end FB of the voltage divider VFB is electrically connected to the negative electrode end of the triode Q1.

[0009] Preferably, one end of the resistor R6 away from the voltage divider VFB is electrically connected to a voltage output terminal VOUT, one side of the resistor R6 is electrically connected to a resistor R5, and an external voltage VADJ is electrically connected to the resistor R5.

[0010] Preferably, a capacitor C8 is connected in series to the resistor R8, a capacitor C7 is connected in parallel after the resistor R8 and the capacitor C8 are connected in series, and a pulse width modulation circuit PWM is electrically connected to the lead of the triode Q1.

[0011] Preferably, the power management circuit includes a diode V2 and a field effect transistor V1 connected in series with the diode V1, and the field effect transistor V1 is electrically connected to a surface mount triode V5 through a resistor R3.

[0012] Preferably, a capacitor C1 and a capacitor C2 are connected in parallel to the diode V2, and a capacitor C3, a resistor R1, and a capacitor C4 are connected in parallel to the field effect transistor V1.

[0013] Preferably, one end of the field effect transistor V1 is electrically connected to a communication interface 5G-pwren, a capacitor C6 is electrically connected to the communication interface 5G-pwren, and a resistor R2 and a capacitor C5 are connected in parallel to the capacitor C6.

[0014] Preferably, the capacitor C5 is electrically connected to the lead 1 of the surface mount triode V5, and the lead 2 of the surface mount triode V5 is electrically connected to the resistor R3.

[0015] Preferably, a resistor R4 is electrically connected to the lead 3 of the surface mount triode V5, and the model of the surface mount triode V5 is L2SC1623.

[0016] The present utility model at least has the following beneficial effects:

[0017] 1. Each switching mode power supply integrates an error amplifier. The error amplifier compares the voltage of the feedback voltage divider VFB with its internal reference voltage VREF and sets the duty cycle PWM. Connecting a compensation network between the input FB and the output COMP of the error amplifier can ensure good regulation of the output voltage under all line and load conditions, thereby reducing losses.

[0018] 2. 5G-pwren is the high and low level of 3.3v. The diode V2 is used to prevent static electricity. For plugging and unplugging devices, the power supply is very important. The filter capacitor on the power supply is used to eliminate the ripple of the circuit. The field effect transistor V1 is a Pmos transistor, and the on-off of the s-to-d circuit is controlled by gs. Therefore, as long as there is appropriate delay control of 5G-pwren, the back-end circuit can have a delay turn-on function. Description of the Drawings

[0019] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0020] Figure 1 is the circuit schematic diagram of the present utility model;

[0021] Figure 2 is the circuit diagram of the error amplifier of the present utility model;

[0022] Figure 3 is the power management circuit diagram of the present utility model.

[0023] In the figure, 1 is the main processor; 2 is the power management unit; 201 is the power management circuit; 3 is the voltage regulator; 301 is the error amplifier circuit; 4 is the PWI interface module. Specific Embodiments

[0024] The following will describe in detail the embodiments of the present application in conjunction with the accompanying drawings and embodiments, so as to fully understand how the present application uses technical means to solve technical problems and achieve the realization process of technical effects and implement accordingly.

[0025] As Figures 1 - 3 shown, the power management circuit based on low-latency and low-power PWI control provided in this embodiment includes a main processor 1, a power management unit 2, a voltage regulator 3, and a PWI interface module 4. The power management unit 2 includes a power management circuit 201, and the voltage regulator 3 includes an error amplifier circuit 301;

[0026] In a power management circuit controlled by low-latency and low-power PWI, a variable or adjustable power supply voltage is required. For example, when PWM modulation is not possible due to EMI reasons, this can be the power supply for a DC motor. In particular, class A and class A / B amplifiers with very small loads have high losses. By reducing the power supply voltage, these losses can be significantly reduced. The error amplifier circuit 301 includes a voltage divider VFB and a compensation circuit. Resistor R6 and resistor R7 are electrically connected to the voltage divider VFB. The voltage divider VFB is electrically connected to the compensation circuit through resistor R8. The compensation circuit includes transistor Q1. The input terminal FB of the voltage divider VFB is electrically connected to the negative terminal of transistor Q1. Each switched-mode power supply integrates an error amplifier. The error amplifier compares the voltage of the feedback voltage divider VFB with its internal reference voltage VREF and sets the duty cycle PWM to make the difference zero. Since the reference voltage is usually in the range of several hundred millivolts to one volt, the output voltage is divided by resistors R6 and R7 on the feedback voltage divider. A compensation network is connected between the input FB and the output COMP of the error amplifier. With a reasonable design, it can ensure good regulation of the output voltage under all line and load conditions, thereby reducing losses;

[0027] One end of resistor R6 far from the voltage divider VFB is electrically connected to the voltage output terminal VOUT. Resistor R5 is electrically connected to one side of resistor R6. An external voltage VADJ is electrically connected to resistor R5. Capacitor C8 is connected in series to resistor R8. Capacitor C7 is connected in parallel after resistor R8 and capacitor C8 are connected in series. A pulse width modulation circuit PWM is electrically connected to the pin of transistor Q1. An external voltage VADJ is applied to the feedback of the error amplifier using the defined resistor R5, injecting an additional current. This current flows to GND through the low-side resistor R7, resulting in an additional voltage drop. The voltage on the input FB of the operational amplifier rises, and the error amplifier reduces the duty cycle to restore it to its reference voltage value. The output voltage of the power supply is proportional to the analog adjustment voltage;

[0028] When the external voltage VADJ is set to 0.0V, resistor R5 is actually in parallel with resistor R7, which means the output voltage has its maximum value. When the external voltage VADJ is set to 5.0V, resistor R5 generates an additional current that is superimposed on the current of resistor R6. In this case, the output voltage reaches its minimum value. The minimum output voltage is limited by the reference voltage and cannot be lower than this value, thus achieving the result of reducing energy consumption.

[0029] Furthermore, as Figure 3As shown, the power management circuit 201 includes a diode V2 and a field effect transistor V1 connected in series with the diode V1. The field effect transistor V1 is electrically connected to a surface mount transistor V5 through a resistor R3. A capacitor C1 and a capacitor C2 are connected in parallel on the diode V2. A capacitor C3, a resistor R1, and a capacitor C4 are connected in parallel on the field effect transistor V1. One end of the field effect transistor V1 is electrically connected to a communication interface 5G-pwren. A capacitor C6 is electrically connected to the communication interface 5G-pwren. A resistor R2 and a capacitor C5 are connected in parallel on the capacitor C6. The capacitor C5 is electrically connected to the pin 1 of the surface mount transistor V5. The pin 2 of the surface mount transistor V5 is electrically connected to the resistor R3. A resistor R4 is electrically connected to the pin 3 of the surface mount transistor V5. The model of the surface mount transistor V5 is L2SC1623. From left to right, the left side is the input, and 5G-pwren is the high and low level of 3.3V. Then analyzing the circuit, the diode V2 is used to prevent static electricity. For plugging and unplugging devices, the power supply is very important. The filter capacitor on the power supply is used to eliminate the ripple of the circuit. The field effect transistor V1 is a Pmos transistor, and the on and off of the s-to-d circuit is controlled by using gs. When VCC is 4V and the power comes in, if 5G-pwren is at a low level, then vgs = 0V and the circuit is cut off;

[0030] If 5G-pwren is at a high level, then vgs < 0V and the circuit is turned on, and the subsequent circuit can be used;

[0031] Therefore, as long as there is appropriate delay control for 5G-pwren, the subsequent circuit can have a delay turn-on function.

[0032] As Figures 1 - 3 shown, the principle of the power management circuit based on low-delay and low-power PWI control provided in this embodiment is as follows:

[0033] The power management circuit based on low-latency and low-power PWI control includes a main processor 1, a power management unit 2, a voltage regulator 3, and a PWI interface module 4. The power management unit 2 includes a power management circuit 201, and the voltage regulator 3 includes an error amplifier circuit 301. In the power management circuit based on low-latency and low-power PWI control, a variable or adjustable power supply voltage is required. For example, when PWM modulation is not possible due to EMI reasons, this can be the power supply for a DC motor. In particular, class A and class A / B amplifiers with only a small load have very high losses. By reducing the power supply voltage, these losses can be significantly reduced. The error amplifier circuit 301 includes a voltage divider VFB and a compensation circuit. A resistor R6 and a resistor R7 are electrically connected to the voltage divider VFB. The voltage divider VFB is electrically connected to the compensation circuit through a resistor R8. The compensation circuit includes a triode Q1. The input terminal FB of the voltage divider VFB is electrically connected to the negative terminal of the triode Q1. Each switching-mode power supply integrates an error amplifier. The error amplifier compares the voltage of the feedback voltage divider VFB with its internal reference voltage VREF and sets the duty cycle PWM to make the difference zero. Since the reference voltage is usually in the range of several hundred millivolts to one volt, the output voltage is divided by the resistors R6 and R7 on the feedback voltage divider. A compensation network is connected between the input FB and the output COMP of the error amplifier. With a reasonable design, it can ensure good regulation of the output voltage under all line and load conditions, thereby reducing losses.

[0034] As used in the specification and claims, certain terms are used to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the criterion for distinction. As used throughout the specification and claims, the term "comprising" is an open-ended term and should be interpreted as "including but not limited to". "Substantially" means within an acceptable error range. Those skilled in the art can solve technical problems within a certain error range and basically achieve the technical effect.

[0035] It should be noted that the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a commodity or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent in such a commodity or system. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the commodity or system including the element.

[0036] The above description shows and describes several preferred embodiments of the present utility model. However, as previously mentioned, it should be understood that the present utility model is not limited to the forms disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications, and environments, and can be altered within the scope of the inventive concept described herein through the above teachings or the techniques or knowledge in related fields. Any alterations and changes made by those skilled in the art without departing from the spirit and scope of the present utility model shall fall within the protection scope of the appended claims of the present utility model.

Claims

1. A power management circuit based on low-latency and low-power PWI control, comprising a main processor (1), a power management unit (2), a voltage regulator (3), and a PWI interface module (4), characterized in that, The power management unit (2) includes a power management circuit (201), and the voltage regulator (3) includes an error amplifier circuit (301). The error amplifier circuit (301) includes a voltage divider VFB and a compensation circuit. A resistor R6 and a resistor R7 are electrically connected to the voltage divider VFB. The voltage divider VFB is electrically connected to the compensation circuit through a resistor R8. The compensation circuit includes a triode Q1. The input terminal FB of the voltage divider VFB is electrically connected to the negative terminal of the triode Q1.

2. The power management circuit based on low-latency and low-power PWI control according to claim 1, wherein: One end of the resistor R6 away from the voltage divider VFB is electrically connected to a voltage output terminal VOUT. A resistor R5 is electrically connected to one side of the resistor R6. An external voltage VADJ is electrically connected to the resistor R5.

3. A power management circuit based on low-latency and low-power PWI control according to claim 1, characterized in that: A capacitor C8 is connected in series to the resistor R8. After the resistor R8 and the capacitor C8 are connected in series, a capacitor C7 is connected in parallel. A pulse width modulation circuit PWM is electrically connected to the lead of the triode Q1.

4. The power management circuit based on low-latency and low-power PWI control according to claim 1, wherein: The power management circuit (201) includes a diode V2 and a field effect transistor V1 connected in series with the diode V1. The field effect transistor V1 is electrically connected to a surface mount triode V5 through a resistor R3.

5. A power management circuit based on low-latency and low-power PWI control according to claim 4, characterized in that: A capacitor C1 and a capacitor C2 are connected in parallel to the diode V2. A capacitor C3, a resistor R1, and a capacitor C4 are connected in parallel to the field effect transistor V1.

6. The power management circuit based on low-latency and low-power PWI control according to claim 4, wherein: One end of the field effect transistor V1 is electrically connected to a communication interface 5G-pwren. A capacitor C6 is electrically connected to the communication interface 5G-pwren. A resistor R2 and a capacitor C5 are connected in parallel to the capacitor C6.

7. A power management circuit based on low-latency and low-power PWI control according to claim 4, characterized in that: The capacitor C5 is electrically connected to the lead 1 of the surface mount triode V5. The lead 2 of the surface mount triode V5 is electrically connected to the resistor R3.

8. A power management circuit based on low-latency and low-power PWI control according to claim 4, characterized in that: A resistor R4 is electrically connected to the lead 3 of the surface mount triode V5. The model of the surface mount triode V5 is L2SC1623.

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