Level switching circuit for increasing level switching speed and radio frequency switch
By introducing an RC delay circuit into the RF switch level conversion circuit, the capacitor C1 is connected to the gate of the MOS tube N1, the problem of slow level conversion is solved and faster level conversion is achieved.
Patent Information
- Application Number
- CN202422310286.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-09-23
AI Technical Summary
The level conversion circuit of existing RF switches is slower to convert.
The level conversion circuit is introduced to form the RC delay circuit, and the capacitor C1 is electrically connected to the gate of the MOS tube N1 to speed up the conduction speed of the MOS tube N1.
The conversion speed of the level conversion circuit is significantly accelerated by the voltage change of capacitor C1.
Smart Images
Figure CN223141902U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of level conversion of radio frequency switches, and particularly relates to a level conversion circuit and a radio frequency switch for accelerating the level switching speed. Background Technique
[0002] A radio frequency switch is the most commonly used radio frequency component, which is commonly used for channel switching and transceiver state switching in a radio frequency link, and is widely used in multiple fields such as the Internet of Things, communication base stations, small base stations, repeater stations, test instruments, radars, WiFi (Wireless Fidelity), RFID (Radio Frequency Identification), etc.
[0003] For a radio frequency switch, it mainly consists of a local oscillator, a negative voltage generation circuit, a low voltage to positive and negative voltage conversion circuit, and a switch core transistor;
[0004] Among them, the low voltage to positive and negative voltage conversion circuit needs to convert a normal control signal into a control signal in the positive and negative voltage domains, and this control signal is usually 1 time larger than the voltage of the normal control signal; at the same time, due to the usually low current driving ability of the on-chip negative voltage generation circuit, the low voltage to positive and negative voltage conversion circuit needs to have characteristics such as high reliability, low power consumption, and fast conversion speed.
[0005] For the existing low voltage to positive and negative voltage conversion circuit, assuming that the negative voltage is V1 and the positive voltage is V2, when it performs voltage switching, the voltage change often gradually changes from V1 to V2, or from V2 to V1, and the entire voltage change range reaches, resulting in a slower overall conversion speed. Summary of the Utility Model
[0006] In view of the deficiencies of the background technique, the utility model provides a level conversion circuit and a radio frequency switch for accelerating the level switching speed, and the technical problem to be solved is that the conversion speed of the existing level conversion circuit for radio frequency switches is slower.
[0007] To solve the above technical problems, in a first aspect, the utility model provides the following technical solution: A level conversion circuit for accelerating the level switching speed, including a first inverter, a second inverter, a pull-up unit, a pull-down unit, a MOS transistor P1, a MOS transistor N1, a resistor R1, and a capacitor C1; the pull-up unit includes two pull-up branches, and the pull-down unit includes two pull-down branches;
[0008] The input terminal of the first inverter is electrically connected to the gate of the MOS transistor P1; the output terminal of the first inverter is electrically connected to the output terminal of an upper pull branch and the input terminal of a lower pull branch through a first switching transistor respectively; the output terminal of the second inverter is electrically connected to the output terminal of another upper pull branch and the input terminal of another lower pull branch through a second switching transistor respectively;
[0009] The input terminal of the other upper pull branch is electrically connected to the gate of the NOS transistor N1 and one end of the capacitor C1 through the resistor R1 respectively. The drain of the MOS transistor N1 is electrically connected to the drain of the MOS transistor P1 for outputting a conversion voltage. The source of the MOS transistor P1 is used to be electrically connected to the power supply VDD. The source of the MOS transistor N1 is electrically connected to the output terminals of the two lower pull branches respectively; the other end of the capacitor C1 is used to input the signal VIP_BB, and the signal VIP_BB is obtained by processing the signal at the input terminal of the first inverter through an even number of third inverters.
[0010] In a certain implementation manner of the first aspect, the first inverter includes a MOS transistor MP1 and a MOS transistor MN5. The source of the MOS transistor MP1 is used to be electrically connected to the power supply VDD. The gate of the MOS transistor MP1 is electrically connected to the gate of the MOS transistor MN5, which is the input terminal of the first inverter. The drain of the MOS transistor MP1 and the drain of the MOS transistor MN5 are electrically connected, which is the output terminal of the first inverter. The source of the MOS transistor MN5 is grounded.
[0011] In a certain implementation manner of the first aspect, the second inverter includes a MOS transistor MP6 and a MOS transistor MN6. The source of the MOS transistor MP6 is used to be electrically connected to the power supply VDD. The gate of the MOS transistor MP6 is electrically connected to the gate of the MOS transistor MN6, which is the input terminal of the second inverter. The drain of the MOS transistor MP6 and the drain of the MOS transistor MN6 are electrically connected, which is the output terminal of the second inverter. The source of the MOS transistor MN6 is grounded.
[0012] In a certain implementation manner of the first aspect, the upper pull unit includes a MOS transistor MP2, a MOS transistor MP4, a MOS transistor MP5, and a MOS transistor MP7; the sources of the MOS transistor MP2 and the MOS transistor MP5 are used to be electrically connected to the power supply VCC; the gate of the MOS transistor MP2 is electrically connected to the drain of the MOS transistor MP5 and the source of the MOS transistor MP7 respectively. The gate of the MOS transistor MP5 is electrically connected to the drain of the MOS transistor MP2 and the source of the MOS transistor MP4 respectively. The gate of the MOS transistor MP4 is electrically connected to the gate of the MOS transistor MP7; the drain of the MOS transistor MP4 is the output terminal of one upper pull branch, and the drain of the MOS transistor MP7 is the output terminal of the other upper pull branch.
[0013] In a certain implementation manner of the first aspect, the pull-down unit includes MOS transistor MN1, MOS transistor MN2, MOS transistor MN3, and MOS transistor MN4; the drain of MOS transistor MN1 is the input end of one path of the pull-down branch, and the gates of MOS transistor MN1 and MOS transistor MN4 are both grounded; the source of MOS transistor MN1 is electrically connected to the drain of MOS transistor MN2 and the gate of MOS transistor MN4 respectively, the source of MOS transistor MN3 is electrically connected to the drain of MOS transistor MN4 and the gate of MOS transistor MN2 respectively, the source of MOS transistor MN2 is the output end of one path of the pull-down branch, and the source of MOS transistor MN4 is the output end of the other path of the pull-down branch.
[0014] In a certain implementation manner of the first aspect, the first switching transistor is MOS transistor MP3; the source of MOS transistor MP3 is electrically connected to the output end of the first inverter, the drain of MOS transistor MP3 is electrically connected to the input end of one path of the pull-down branch, and the gate of MOS transistor MP3 is grounded.
[0015] In a certain implementation manner of the first aspect, the second switching transistor is MOS transistor MP8, the source of MOS transistor MP8 is electrically connected to the output end of the second inverter, the drain of MOS transistor MP8 is electrically connected to the input end of the other path of the pull-down branch, and the gate of MOS transistor MP8 is grounded.
[0016] In a certain implementation manner of the first aspect, both MOS transistor MP3 and MOS transistor MP8 are PMOS transistors, MOS transistor P1 is a PMOS transistor, and MOS transistor N1 is an NMOS transistor.
[0017] In a certain implementation manner of the first aspect, the signal VIP_BB is obtained by processing the signal at the input end of the first inverter through two third inverters.
[0018] In the second aspect, the present invention provides a radio frequency switch, and the above-mentioned level conversion circuit for accelerating the level switching speed is provided on the radio frequency switch.
[0019] The beneficial effects of the present invention compared with the prior art are: in actual use, the present invention forms an RC delay circuit by setting a resistor R1 and a capacitor C1 at the input end of the other path of the pull-down branch, and by electrically connecting the capacitor C1 to the gate of MOS transistor N1, so that since the voltage on the capacitor C1 cannot change suddenly, the conduction of MOS transistor N1 can be accelerated through the voltage of the capacitor C1 during voltage switching, thereby being able to accelerate the conversion speed of the level conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is the circuit diagram of the circuit of the present invention in Embodiment 1;
[0021] Figure 2 For Figure 1 the simulation schematic diagram of the circuit. Specific embodiments
[0022] Now, the present utility model will be further described in detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present utility model in a schematic manner, so they only show the components related to the present utility model.
[0023] As Figure 1 shown, a level conversion circuit for accelerating the level switching speed includes a first inverter 1, a second inverter 2, a pull-up unit 3, a pull-down unit 4, a MOS transistor P1, a MOS transistor N1, a resistor R1, and a capacitor C1; the pull-up unit 1 includes two pull-up branches, and the pull-down unit 2 includes two pull-down branches;
[0024] The input terminal of the first inverter 1 is electrically connected to the gate of the MOS transistor P1; the output terminal of the first inverter 1 is respectively electrically connected to the output terminal of one pull-up branch and the input terminal of one pull-down branch through a first switch transistor 5;
[0025] The output terminal of the second inverter 2 is respectively electrically connected to the output terminal of the other pull-up branch and the input terminal of the other pull-down branch through a second switch transistor 6;
[0026] The input terminal of the other pull-up branch is respectively electrically connected to the gate of the NOS transistor N1 and one end of the capacitor C1 through the resistor R1, the drain of the MOS transistor N1 is electrically connected to the drain of the MOS transistor P1 for outputting a conversion voltage, the source of the MOS transistor P1 is used to be electrically connected to the power supply VDD, the source of the MOS transistor N1 is respectively electrically connected to the output terminals of the two pull-down branches; the other end of the capacitor C1 is used to input a signal VIP_BB, and the signal VIP_BB is obtained by processing the signal at the input terminal of the first inverter 1 through an even number of third inverters INV3.
[0027] Specifically, in this embodiment, as Figure 1 shown, the first inverter 1 includes a MOS transistor MP1 and a MOS transistor MN5, the source of the MOS transistor MP1 is used to be electrically connected to the power supply VDD, the gate of the MOS transistor MP1 is electrically connected to the gate of the MOS transistor MN5, which is the input terminal of the first inverter 1, the drain of the MOS transistor MP1 is electrically connected to the drain of the MOS transistor MN5, which is the output terminal of the first inverter 1, and the source of the MOS transistor MN5 is grounded.
[0028] Specifically, in this embodiment, as Figure 1As shown, the second inverter 2 includes MOS transistor MP6 and MOS transistor MN6. The source of MOS transistor MP6 is used to be electrically connected to the power supply VDD. The gate of MOS transistor MP6 is electrically connected to the gate of MOS transistor MN6, which is the input terminal of the second inverter 2. The drain of MOS transistor MP6 and the drain of MOS transistor MN6 are electrically connected, which is the output terminal of the second inverter 2. The source of MOS transistor MN6 is grounded.
[0029] Specifically, in this embodiment, as Figure 1 shown, the pull-up unit 3 includes MOS transistors MP2, MP4, MP5 and MP7; among them, MOS transistors MP2 and MP4 form one pull-up branch, and MOS transistors MP5 and MP7 form another pull-up branch;
[0030] The sources of MOS transistor MP2 and MOS transistor MP5 are used to be electrically connected to the power supply VCC; the gate of MOS transistor MP2 is electrically connected to the drain of MOS transistor MP5 and the source of MOS transistor MP7 respectively. The gate of MOS transistor MP5 is electrically connected to the drain of MOS transistor MP2 and the source of MOS transistor MP4 respectively. The gate of MOS transistor MP4 is electrically connected to the gate of MOS transistor MP7; the drain of MOS transistor MP4 is the output terminal of one pull-up branch, and the drain of MOS transistor MP7 is the output terminal of the other pull-up branch.
[0031] Specifically, in this embodiment, as Figure 1 shown, the pull-down unit 4 includes MOS transistors MN1, MN2, MN3 and MN4; MOS transistors MN1 and MN2 form one pull-down branch, and MOS transistors MN3 and MN4 form another pull-down branch;
[0032] The drain of MOS transistor MN1 is the input terminal of one pull-down branch. The gates of MOS transistor MN1 and MOS transistor MN4 are both grounded; the source of MOS transistor MN1 is electrically connected to the drain of MOS transistor MN2 and the gate of MOS transistor MN4 respectively. The source of MOS transistor MN3 is electrically connected to the drain of MOS transistor MN4 and the gate of MOS transistor MN2 respectively. The source of MOS transistor MN2 is the output terminal of one pull-down branch, and the source of MOS transistor MN4 is the output terminal of the other pull-down branch.
[0033] Specifically, in this embodiment, as Figure 1 shown, the first switching transistor 5 is MOS transistor MP3; the source of MOS transistor MP3 is electrically connected to the output terminal of the first inverter 1. The drain of MOS transistor MP3 is electrically connected to the input terminal of one pull-down branch. The gate of MOS transistor MP3 is grounded.
[0034] Specifically, in this embodiment, asFigure 1 As shown, the second switching transistor 6 is the MOS transistor MP8. The source of the MOS transistor MP8 is electrically connected to the output terminal of the second inverter. The drain of the MOS transistor MP8 is electrically connected to the input terminal of another pull-down branch. The gate of the MOS transistor MP8 is grounded.
[0035] Specifically, in this embodiment, as Figure 1 shown, both the MOS transistors MP3 and MP8 are PMOS transistors, the MOS transistor P1 is a PMOS transistor, and the MOS transistor N1 is an NMOS transistor.
[0036] Specifically, in this embodiment, as Figure 1 shown, the signal VIP_BB is obtained by processing the signal at the input terminal of the first inverter 1 through two third inverters INV3. In actual use, the signals VIP and VIP_BB are in phase. The two third inverters INV3 can increase the driving ability of the signal VIP_BB.
[0037] Regarding Figure 1 the first inverter 1, the second inverter 2, the pull-up unit 3, the pull-down unit 4, the MOS transistors MP3 and MP8 in
[0038] When this circuit is working, the signals VIP and VIN are a pair of differential signals, that is, one of the signals VIP and VIN is a high-level signal and the other is a low-level signal;
[0039] When the signal VIP is at a high level and the signal VIN is at a low level, the first inverter 1 inverts the signal VIP and outputs a low-level signal. At this time, the MOS transistor MP3 is not conducting; the second inverter 2 inverts the signal VIN and outputs a high-level signal, and the MOS transistor MP8 is conducting;
[0040] Then, both the MOS transistors MP2 and MP4 in the pull-up unit 3 are not conducting, and both the MOS transistors MP5 and MP7 are conducting, which pulls up the high-level signal output by the second inverter 2, and the node VOP outputs a high-level signal; the MOS transistors MN1 and MN2 in the pull-down unit 4 are conducting, and the MOS transistors MN3 and MN4 are not conducting, which pulls down the low-level signal output by the first inverter 1, and the node VON outputs a low-level signal.
[0041] When the signal VIP is at a low level and the signal VIN is at a high level, the working state of the circuit is opposite, and no redundant description will be given here.
[0042] Regarding Figure 1 the entire circuit process, the analysis is as follows:
[0043] When the signal VIP is at a low level and the signal VIN is at a high level, the voltage of node A is the negative voltage VDD_negative, and the voltage difference across the capacitor C1 is 0 - VDD_negative. At this time, the MOS transistor P1 is turned on and the MOS transistor N1 is not turned on, and the output VOUT is at the high level VDD;
[0044] When the signal VIP switches from the low level 0V to the high level VDD, due to the fact that the voltage difference across the capacitor C1 cannot change suddenly, the voltage difference across the capacitor C1 approximately becomes VDD - 0 at this time, and the voltage of node A suddenly changes to 0V, enabling the MOS transistor N1 to turn on faster, and can accelerate the conversion speed of the circuit composed of the first inverter 1, the second inverter 2, the pull-up unit 3, the pull-down unit 4, the MOS transistor MP3, and the MOS transistor MP8, so that the voltage of node A can be switched to the high level VDD faster. At this time, the MOS transistor P1 is not turned on and the MOS transistor N1 is turned on, and the output VOUT is the negative voltage VDD_negative.
[0045] For Figure 1 the circuit simulation, where the curve VOUT1 is the output simulation diagram of the circuit without the switching acceleration circuit composed of the resistor R1 and the capacitor C1, and the curve VOUT2 is the output simulation diagram of the circuit with the switching acceleration circuit composed of the resistor R1 and the capacitor C1;
[0046] From Figure 2 it can be obtained that when the signal VIP switches from 0V to VDD = 3.3V, the curve VOUT2 switches from 3.3V to the negative voltage - 1.5V in 20ns, while the curve VOUT1 takes 40ns to switch from 3.3V to - 1V, and the switching speed is significantly slower. Therefore, the conversion speed of the level conversion circuit of the present application is faster.
[0047] In summary, the utility model forms an RC delay circuit by setting the resistor R1 and the capacitor C1 at the input end of the other pull-down branch, and by electrically connecting the capacitor C1 to the gate of the MOS transistor N1. In this way, due to the fact that the voltage on the capacitor C1 cannot change suddenly, the voltage of the capacitor C1 can accelerate the conduction of the MOS transistor N1 during voltage switching, thereby being able to accelerate the conversion speed of the level conversion circuit.
[0048] Embodiment 2
[0049] This embodiment provides a radio frequency switch, and the above-mentioned level conversion circuit for accelerating the level switching speed is provided on the radio frequency switch.
[0050] Based on the inspiration of the present utility model, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of this utility model. The technical scope of this utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.
Claims
1. A level conversion circuit for accelerating the level switching speed, characterized in that It includes a first inverter, a second inverter, a pull-up unit, a pull-down unit, MOS transistor P1, MOS transistor N1, resistor R1, and capacitor C1; the pull-up unit includes two pull-up branches, and the pull-down unit includes two pull-down branches; The input terminal of the first inverter is electrically connected to the gate of MOS transistor P1; the output terminal of the first inverter is electrically connected to the output terminal of one pull-up branch and the input terminal of one pull-down branch respectively through a first switch transistor; the output terminal of the second inverter is electrically connected to the output terminal of the other pull-up branch and the input terminal of the other pull-down branch respectively through a second switch transistor; The input terminal of the other pull-up branch is electrically connected to the gate of NOS transistor N1 and one end of capacitor C1 respectively through resistor R1. The drain of MOS transistor N1 is electrically connected to the drain of MOS transistor P1 for outputting a conversion voltage. The source of MOS transistor P1 is used to be electrically connected to power supply VDD. The source of MOS transistor N1 is electrically connected to the output terminals of the two pull-down branches respectively; the other end of capacitor C1 is used to input signal VIP_BB, and signal VIP_BB is obtained after the signal at the input terminal of the first inverter is processed by an even number of third inverters.
2. The level conversion circuit for accelerating the level switching speed according to claim 1, wherein The first inverter includes MOS transistors MP1 and MN5. The source of MOS transistor MP1 is used to be electrically connected to power supply VDD. The gate of MOS transistor MP1 is electrically connected to the gate of MOS transistor MN5, which is the input terminal of the first inverter. The drain of MOS transistor MP1 and the drain of MOS transistor MN5 are electrically connected, which is the output terminal of the first inverter. The source of MOS transistor MN5 is grounded.
3. The level conversion circuit for accelerating the level switching speed according to claim 1, wherein The second inverter includes MOS transistors MP6 and MN6. The source of MOS transistor MP6 is used to be electrically connected to power supply VDD. The gate of MOS transistor MP6 is electrically connected to the gate of MOS transistor MN6, which is the input terminal of the second inverter. The drain of MOS transistor MP6 and the drain of MOS transistor MN6 are electrically connected, which is the output terminal of the second inverter. The source of MOS transistor MN6 is grounded.
4. A level conversion circuit for accelerating the level switching speed according to claim 1, characterized in that The pull-up unit includes MOS transistors MP2, MP4, MP5, and MP7; the sources of MOS transistor MP2 and MOS transistor MP5 are used to be electrically connected to power supply VCC; the gate of MOS transistor MP2 is electrically connected to the drain of MOS transistor MP5 and the source of MOS transistor MP7 respectively. The gate of MOS transistor MP5 is electrically connected to the drain of MOS transistor MP2 and the source of MOS transistor MP4 respectively. The gate of MOS transistor MP4 is electrically connected to the gate of MOS transistor MP7; the drain of MOS transistor MP4 is the output terminal of one pull-up branch, and the drain of MOS transistor MP7 is the output terminal of the other pull-up branch.
5. A level conversion circuit for accelerating the level switching speed according to claim 1, characterized in that, The pull-down unit includes MOS transistor MN1, MOS transistor MN2, MOS transistor MN3, and MOS transistor MN4; the drain of MOS transistor MN1 is the input end of one path of the pull-down branch, and the gates of MOS transistor MN1 and MOS transistor MN4 are both grounded; the source of MOS transistor MN1 is electrically connected to the drain of MOS transistor MN2 and the gate of MOS transistor MN4 respectively, the source of MOS transistor MN3 is electrically connected to the drain of MOS transistor MN4 and the gate of MOS transistor MN2 respectively, the source of MOS transistor MN2 is the output end of one path of the pull-down branch, and the source of MOS transistor MN4 is the output end of the other path of the pull-down branch.
6. The level conversion circuit for accelerating the level switching speed according to claim 1, wherein The first switching transistor is MOS transistor MP3; the source of MOS transistor MP3 is electrically connected to the output end of the first inverter, the drain of MOS transistor MP3 is electrically connected to the input end of one path of the pull-down branch, and the gate of MOS transistor MP3 is grounded.
7. The level conversion circuit for accelerating the level switching speed according to claim 6, characterized in that, The second switching transistor is MOS transistor MP8, the source of MOS transistor MP8 is electrically connected to the output end of the second inverter, the drain of MOS transistor MP8 is electrically connected to the input end of the other path of the pull-down branch, and the gate of MOS transistor MP8 is grounded.
8. A level conversion circuit for accelerating the level switching speed according to claim 7, characterized in that, Both MOS transistor MP3 and MOS transistor MP8 are PMOS transistors, MOS transistor P1 is a PMOS transistor, and MOS transistor N1 is an NMOS transistor.
9. A level conversion circuit for accelerating the level switching speed according to claim 1, wherein The signal VIP_BB is obtained by processing the signal at the input end of the first inverter through two third inverters.
10. A radio frequency switch, characterized in that, The radio frequency switch is provided with the level conversion circuit for accelerating the level switching speed according to any one of claims 1-9.