Multi-interface communication gateway

Abstract

The utility model relates to the field of communication, in particular to a multi-interface communication gateway. Comprising a control chip, and a ZETA communication module, an LORA communication module, an RS485 communication module, a TF data memory card interface circuit and an LVDS display module which are respectively connected with the control chip, the ZETA communication module is connected with an SPI pin and an interrupt pin of the control chip, the RS485 communication module comprises a transceiver chip and a digital isolator, the control chip is connected with pins TXD and RXD of the transceiver chip through the digital isolator, and the control chip is connected with the TXD and RXD of the transceiver chip through the digital isolator. And pins A and B of the transceiver chip are connected with the 485 antenna. According to the utility model, a plurality of communication modules such as ZETA, LORA and RS485 are integrated, and diversification of communication methods is realized.

Description

Technical Field

[0001] The utility model relates to the field of communication, in particular to a communication gateway with multiple interfaces. Background Art

[0002] As a device for connecting networks with different communication protocols, the communication gateway with multiple interfaces plays an important role in the fields of Internet of Things, industrial automation, etc. At present, the technology of the communication gateway with multiple interfaces has been relatively mature, but there is a lack of a communication gateway integrating ZETA, LORA and wired network. Content of the Utility Model

[0003] Aiming at the defects of the prior art, the utility model provides a communication gateway with multiple interfaces, which integrates multiple communication modules such as ZETA, LORA and RS485, and realizes diversified communication methods.

[0004] In order to solve the technical problems, the technical scheme adopted by the utility model is: a communication gateway with multiple interfaces, including a control chip and a ZETA communication module, a LORA communication module, an RS485 communication module, a TF data memory card interface circuit and an LVDS display module which are respectively connected with the control chip. The ZTEA communication module is connected with the SPI pin and the interrupt pin of the control chip. The RS485 communication module includes a transceiver chip and a digital isolator. The control chip is connected with the pins TXD and RXD of the transceiver chip through the digital isolator. The pins A and B of the transceiver chip are connected with a 485 antenna.

[0005] Further, the ZETA communication module includes a chip ZTG1323B and an antenna interface RF1. The antenna is connected to the antenna interface RF1. The antenna interface RF1 is respectively connected to the input port and the output port of the chip ZTG1323B through a filter voltage stabilization circuit. The SPI pin and the interrupt pin of the chip ZTG1323B are respectively connected to the SPI pin and the interrupt pin of the control chip.

[0006] Further, the series-connected inductors L1, L2, L3, L4 and capacitor C26 constitute a filter voltage stabilization circuit between the antenna interface RF1 and the output port TX of the ZTG1323B. The capacitor C24 is grounded between the inductors L1 and L2. The capacitor C25 is grounded between the inductors L3 and L4. The capacitor C30 is connected to the input port RXP of the ZTG1323B between the inductors L2 and L3. The inductor L6 is connected to the input port RXN of the ZTG1323B between the inductors L2 and L3. An inductor L7 is connected between the input ports RXP and RXN of the ZTG1323B. One end of the inductor L7 is grounded through the inductor L5, and the other end of the inductor L7 is grounded through the capacitor C31.

[0007] Further, a resistor R1 and a transient suppression diode D41 are connected in parallel between the pin A of the transceiver chip and the ground, a resistor R7 and a transient suppression diode D42 are connected in parallel between the pin B of the transceiver chip and the ground, and a transient suppression diode D24 is connected between the pin A and the pin B of the transceiver chip. The positive electrode of the transient suppression diode D24 is connected to the pin B, and the negative electrode is connected to the pin A.

[0008] Further, the RS485 communication module further includes a DC / DC converter. The input end of the DC / DC converter is connected to +5V, the output end outputs +5V, and the +5V is respectively connected to the VCC2 of the digital isolator and the VCC terminal of the transceiver chip. The VCC1 of the digital isolator is connected to +3.3V.

[0009] Further, the LORA communication module includes a communication chip. The pins AUX, LNA_EN, PA_EN, RXD, and TXD of the communication chip are respectively connected to the control chip, and the pin ANT of the communication chip is connected to the antenna through a Π-type filter circuit.

[0010] Further, the control chip is FET113i-S.

[0011] The beneficial effects of the present utility model: The present utility model is designed with multiple communication interfaces, integrating multiple communication modules such as ZETA, LORA, and RS485, realizing diversified communication methods, ensuring that communication functions can be achieved in various environments, and having a communication interface with domestic self-organizing network ZETA technology. As a pure domestic LPWAN communication technology, ZETA realizes the full-stack localization of the communication module, which can effectively address the problem of technology monopoly. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is the principle block diagram of the present utility model;

[0013] Figure 2 is the circuit schematic diagram of the ZETA communication module;

[0014] Figure 3 is the circuit schematic diagram of the RS485 communication module;

[0015] Figure 4 is the circuit schematic diagram of the LORA communication module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] In order to make the technical solutions of the present utility model clearer, the present utility model will be further described in detail through specific embodiments in conjunction with the accompanying drawings. The specific implementation cases described this time are only used to explain the present utility model and cannot be used to limit the present utility model.

[0017] Embodiment 1

[0018] This embodiment discloses a communication gateway with multiple interfaces, such as Figure 1 shown in the figure. It includes a control chip, a ZETA communication module, a LORA communication module, an RS485 communication module, a TF data memory card interface circuit, and an LVDS display module, all of which are connected to the control chip. The ZTEA communication module is connected to the SPI pin and the interrupt pin of the control chip. The RS485 communication module includes a transceiver chip and a digital isolator. The control chip is connected to the TXD and RXD pins of the transceiver chip through the digital isolator. The A and B pins of the transceiver chip are connected to the 485 antenna.

[0019] In this embodiment, the FET113i-S control chip is used as the control chip. The ZETA communication module uses the SPI function of the chip pins, and other modules are connected to the general IO ports of the control chip.

[0020] such as Figure 2 shown in the figure. The ZETA communication module includes the chip ZTG1323B and the antenna interface RF1. The antenna is connected to the antenna interface RF1. The antenna interface RF1 is connected to the input port and output port of the chip ZTG1323B through a filter voltage stabilization circuit respectively. The SPI pin and the interrupt pin of the chip ZTG1323B are connected to the SPI pin and the interrupt pin of the control chip respectively.

[0021] In this embodiment, the series-connected inductors L1, L2, L3, L4, and capacitor C26 constitute the filter voltage stabilization circuit between the antenna interface RF1 and the output port TX of the ZTG1323B. Capacitor C24 is grounded between inductor L1 and inductor L2. Capacitor C25 is grounded between inductor L3 and inductor L4. Capacitor C30 is connected to the input port RXP of the ZTG1323B between inductor L2 and inductor L3. Inductor L6 is connected to the input port RXN of the ZTG1323B between inductor L2 and inductor L3. An inductor L7 is connected between the input ports RXP and RXN of the ZTG1323B. One end of the inductor L7 is grounded through the inductor L5, and the other end of the inductor L7 is grounded through the capacitor C31.

[0022] such as Figure 3As shown in the figure, the RS485 transceiver chip U19 selects MAX13487ESA, and the digital isolator U24 selects ISO7221MDR. The 2nd and 3rd pins of the digital isolator are connected to the pins UART4_RXD and UART4_TXD of the control chip for receiving and transmitting the level signals of the pins; the 6th and 7th pins of the digital isolator U24 are respectively connected to the pins RXD and TXD of the transceiver chip U19; the pins B and A of the transceiver chip U19 are connected through the transient suppression diode D24, and the pins B and A are respectively connected in parallel with the resistor R1 and the transient suppression diode D41, the resistor R7 and the transient suppression diode D42. The pins B and A of the transceiver chip U19 are used for receiving and transmitting RS485 signals. The RS485 communication module also includes a DC / DC converter. The input end of the DC / DC converter is connected to +5V, and the output end outputs +5V. The +5V is respectively connected to the VCC2 of the digital isolator and the VCC terminal of the transceiver chip. The VCC1 of the digital isolator is connected to +3.3V. The DC / DC converter is used to provide a stable voltage source for the RS485 circuit. In this embodiment, there are two RS485 communication modules. The two RS485 communication modules have the same structure and both include the RS485 transceiver chip MAX13487ESA and the digital isolator ISO7221MDR. The pins B and A of the transceiver chips of the two paths are both connected to the connector P4, and the connector P4 is connected to the antenna.

[0023] As Figure 4 shown, the LORA communication module includes the communication chip E70-433MT14S. The pins AUX, LNA_EN, PA_EN, RXD, and TXD of the communication chip E70-433MT14S are respectively connected to the control chip. The pin AUX indicates the working state of the module. The pin LNA_EN is the output of the external LNA. LNA is a low-noise amplifier, and its function is to amplify the weak signal of the radio frequency signal on the premise of minimizing the influence on the noise figure of the receiver. The pin PA_EN is the output of the external PA and is used to implement the low-power mode. The ANT pin of the communication chip is connected to the antenna RF1 through a Π-type filter circuit. As Figure 4 shown, the Π-type filter circuit includes the inductor L1, the capacitor C10, and the capacitor C11. The inductor L1 is connected between the ANT pin and the antenna interface RF1. The capacitor C10 is connected between one end of the inductor L1 and the ground. The capacitor C11 is connected between the other end of the inductor L1 and the ground. The Π-type filter circuit can make the signal have stronger anti-interference ability. At the same time, the LORA communication module is provided with a mode selection button and a reset button, which are conventional technical means in the art and will not be elaborated here.

[0024] At the same time, the TF data memory card interface circuit and the LVDS display module are also conventional technical means in the art, and will not be described in detail according to the drawings in this embodiment.

[0025] The above description is only about the basic principle and preferred embodiments of the present utility model. The improvements and substitutions made by those skilled in the art based on the present utility model fall within the protection scope of the present utility model.

Claims

1. A communication gateway with multiple interfaces, characterized in that: It includes a control chip, as well as a ZETA communication module, a LORA communication module, an RS485 communication module, a TF data memory card interface circuit, and an LVDS display module that are respectively connected to the control chip. The ZTEA communication module is connected to the SPI pin and the interrupt pin of the control chip. The RS485 communication module includes a transceiver chip and a digital isolator. The control chip is connected to the TXD and RXD pins of the transceiver chip through the digital isolator. The A and B pins of the transceiver chip are connected to the 485 antenna.

2. The multi-interface communication gateway according to claim 1, wherein: The ZETA communication module includes the chip ZTG1323B and the antenna interface RF1. The antenna is connected to the antenna interface RF1. The antenna interface RF1 is respectively connected to the input port and the output port of the chip ZTG1323B through a filter voltage stabilization circuit. The SPI pin and the interrupt pin of the chip ZTG1323B are respectively connected to the SPI pin and the interrupt pin of the control chip.

3. The communication gateway with multiple interfaces according to claim 2, characterized in that: The series-connected inductors L1, L2, L3, L4, and capacitor C26 constitute the filter voltage stabilization circuit between the antenna interface RF1 and the output port TX of the ZTG1323B. The capacitor C24 is grounded between the inductor L1 and the inductor L2. The capacitor C25 is grounded between the inductor L3 and the inductor L4. The capacitor C30 is connected to the input port RXP of the ZTG1323B between the inductor L2 and the inductor L3. The inductor L6 is connected to the input port RXN of the ZTG1323B between the inductor L2 and the inductor L3. An inductor L7 is connected between the input ports RXP and RXN of the ZTG1323B. One end of the inductor L7 is grounded through the inductor L5, and the other end of the inductor L7 is grounded through the capacitor C31.

4. The communication gateway with multiple interfaces according to claim 1, characterized in that: A resistor R1 and a transient suppression diode D41 are connected in parallel between the pin A of the transceiver chip and the ground. A resistor R7 and a transient suppression diode D42 are connected in parallel between the pin B of the transceiver chip and the ground. And a transient suppression diode D24 is connected between the pin A and the pin B of the transceiver chip. The positive pole of the transient suppression diode D24 is connected to the pin B, and the negative pole is connected to the pin A.

5. The multi-interface communication gateway according to claim 1 or 4, characterized in that: The RS485 communication module also includes a DC / DC converter. The input end of the DC / DC converter is connected to +5V, and the output end outputs +5V. The +5V is respectively connected to the VCC2 of the digital isolator and the VCC end of the transceiver chip. The VCC1 of the digital isolator is connected to +3.3V.

6. The multi-interface communication gateway according to claim 1, characterized in that: The LORA communication module includes a communication chip. The AUX, LNA_EN, PA_EN, RXD, and TXD pins of the communication chip are respectively connected to the control chip. The ANT pin of the communication chip is connected to the antenna through a Π-type filter circuit.

7. The communication gateway with multiple interfaces according to claim 1, characterized in that: The control chip is FET113i-S.

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