Two-phase clock signal generation circuit and generator

Abstract

The utility model provides a two-phase clock signal generating circuit and a two-phase clock signal generator, which belong to the electronic circuit technology and comprise an input end IO4, output ends IO1-IO3, comparators U1-U3, a positive peak detector and a negative peak detector. Wherein the input end IO4 receives a symmetric excitation signal. The comparator U1 outputs an in-phase clock signal to the IO3. And the positive peak detector is matched with the comparator U2 and is output to the S end of the SR trigger U6. And the negative peak value detector is matched with the comparator U3 and is output to the R end of the SR trigger U6. The Q output end and the Q output end of the SR trigger U6 are connected to the output end IO1 and the output end IO2 respectively, and 90-degree and 270-degree orthogonal clock signals are generated. According to the utility model, an orthogonal clock signal which strictly keeps a 90-degree phase difference with an excitation signal can be generated in a simple and effective manner.

Description

Technical Field

[0001] The utility model belongs to the field of electronic circuits, and particularly relates to a two-phase clock signal generating circuit and a generator. Background Art

[0002] In various industrial application fields, such as the fuel monitoring system in avionics equipment, the water volume monitoring in the fire protection system, etc., technical solutions based on the principle of quadrature lock-in amplifiers are adopted. Especially in the field of avionics equipment, due to the volume limitation and strict energy consumption requirements of the equipment, the application of such technologies is particularly crucial.

[0003] The core of such technologies lies in driving the sensor with a two-phase signal and accurately measuring the in-phase component (In-Phase, I) and quadrature component (Quadrature, Q) of the signal to achieve non-contact detection of the capacitive and dielectric characteristics of the measured medium. These measured characteristic parameters are directly related to the volume of the measured medium. Therefore, an orthogonal lock-in amplifier and a synchronous demodulator are usually integrated in the design to facilitate extracting useful information from complex and possibly noise-interfered signals.

[0004] However, in the process of implementing the above technologies, there is a significant technical challenge: that is, how to generate an orthogonal signal that strictly maintains a 90° phase difference from the excitation signal. This challenge is crucial for improving the measurement accuracy because any phase error will directly affect the accuracy of the final measurement result. In addition, in order to adapt to the harsh working environment and meet the requirements of miniaturization, it is also necessary to ensure that the entire system has good stability and low power consumption characteristics.

[0005] In summary, although the existing technologies can meet the actual needs to a certain extent, there is still room for improvement in terms of accuracy, anti-interference ability, and power consumption management. Summary of the Invention

[0006] The purpose of the utility model is to provide a two-phase clock signal generating circuit and a generator, so as to generate two-phase clock signals suitable for the input of an orthogonal lock-in amplifier in a simple and effective way, thereby improving the ability to extract a sinusoidal signal with a constant amplitude or a slowly changing amplitude from a noise background.

[0007] To achieve the above purpose, the technical solution adopted by the utility model is:

[0008] A two-phase clock signal generating circuit includes an input terminal IO4, a comparator U1, an output terminal IO3, a comparator U2, a positive peak detector, a negative peak detector, a comparator U3, an SR flip-flop U6, and an output port; the input terminal IO4 is connected to the positive electrode of the input side of the comparator U1, the negative electrode of the input side of the comparator U1 is grounded, and the output side is connected to the output terminal IO3; one end of the positive peak detector is connected to the input terminal IO4, and the other end is connected to the negative electrode of the input side of the comparator U2; the positive electrode of the input side of the comparator U2 is connected to the input terminal IO4, and the output side is connected to the S terminal of the SR flip-flop U6; the negative peak detector, one end is connected to the input terminal IO4, and the other end is connected to the positive electrode of the input side of the comparator U3; the comparator U3, the negative electrode of the input side is connected to the input terminal IO4, and the output side is connected to the R terminal of the SR flip-flop U6; the SR flip-flop U6 is connected to the output port.

[0009] Further, the output port includes an output terminal IO1 and an output terminal IO2, the Q output terminal of the SR flip-flop U6 is connected to the output terminal IO1, and the ~Q output terminal is connected to the output terminal IO2.

[0010] Further, the output terminal IO1 outputs a 90° quadrature phase clock signal; the output terminal IO2 outputs a 270° quadrature phase clock signal.

[0011] Further, the output terminal IO3 outputs a in-phase clock signal.

[0012] Further, the input of the input terminal IO4 is a symmetric excitation signal.

[0013] Further, the positive peak detector specifically includes a diode D1, a capacitor C1, and a resistor R1; the positive electrode of the diode D1 is connected to the input terminal IO4, and the negative electrode is respectively connected to one end of the capacitor C1 and the resistor R1, and the other ends of the capacitor C1 and the resistor R1 are grounded.

[0014] Further, the negative electrode of the input side of the comparator U2 is connected to the negative electrode of the diode D1.

[0015] Further, the negative peak detector specifically includes a diode D2, a capacitor C2, and a resistor R2, the negative electrode of the diode D2 is connected to the input terminal IO4, and the positive electrode is respectively connected to one end of the capacitor C2 and the resistor R2, and the other ends of the capacitor C2 and the resistor R2 are grounded.

[0016] Further, the positive electrode of the input side of the comparator U3 is connected to the positive electrode of the diode D2.

[0017] A two-phase clock signal generator includes the above-mentioned two-phase clock signal generating circuit.

[0018] Compared with the prior art, the utility model has the following technical effects:

[0019] The present utility model provides a two-phase clock signal generator, and its core advantage lies in being able to generate orthogonal clock signals with a strict 90° phase difference from the excitation signal in a simple and effective manner. Compared with the existing technical solutions, the two-phase clock signal generator of the present utility model specifically includes the following beneficial effects:

[0020] 1. Improve measurement accuracy: By accurately generating orthogonal clock signals with a 90° phase difference, the phase error is effectively reduced, which is crucial for improving the measurement accuracy of the lock-in amplifier. A smaller phase error means higher measurement accuracy, which is particularly important for applications with extremely high requirements for accuracy.

[0021] 2. Enhance anti-interference ability: The design of the present utility model integrates a peak detector and a comparator, which can accurately extract useful signals from a complex noise environment. This design helps to improve the reliability and stability of the system in a harsh environment. The positive peak detector cooperates with the comparator U2 and outputs to the S terminal of the SR flip-flop U6. The negative peak detector cooperates with the comparator U3 and outputs to the R terminal of the SR flip-flop U6. The Q and ~Q output terminals of the SR flip-flop U6 are respectively connected to the output terminals IO1 and IO2 to generate 90° and 270° orthogonal clock signals. The present utility model can generate orthogonal clock signals with a strict 90° phase difference from the excitation signal in a simple and effective manner.

[0022] 3. Simplify circuit design: By using a simple combination of a peak detection circuit and a comparator, efficient two-phase clock signal generation is achieved. This not only reduces the complexity of the circuit but also reduces the number of required components, thereby reducing costs and simplifying the manufacturing process.

[0023] 4. Reduce power consumption: The present utility model pays special attention to power consumption management. By optimizing the circuit design, it ensures high performance even in low-power modes. This is particularly important for application scenarios that require long-term operation and are sensitive to energy consumption, such as fuel monitoring systems in avionics.

[0024] 5. Strong adaptability: This clock signal generator can adapt to various working environments. Whether it is temperature changes or adverse factors such as electromagnetic interference, it can work stably. This is a very important feature for devices that need to work under harsh conditions.

[0025] 6. Easy to integrate: The design of the present utility model is convenient for integration with other electronic components, such as orthogonal lock-in amplifiers and synchronous demodulators, which helps to build a complete measurement system. In addition, its miniaturized design is also more suitable for application scenarios with limited space.

[0026] In summary, the two-phase clock signal generator provided by the present utility model effectively solves the problems existing in the prior art through its unique design, and demonstrates remarkable advantages in improving measurement accuracy, enhancing anti-interference ability, simplifying circuit design, reducing power consumption, enhancing adaptability, and being easy to integrate. These characteristics make it a highly potential technological innovation in the field of industrial applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0028] Figure 1 is the schematic diagram of the two-phase clock signal generator in this embodiment;

[0029] Figure 2 is the waveform diagram of the output signal of the output terminal IO3 in this embodiment;

[0030] Figure 3 is the waveform diagram of the signal of the positive peak detector in this embodiment;

[0031] Figure 4 is the waveform diagram of the output signal of the comparator U2 in this embodiment;

[0032] Figure 5 is the waveform diagram of the signal of the negative peak detector in this embodiment;

[0033] Figure 6 is the waveform diagram of the output signal of the comparator U3 in this embodiment;

[0034] Figure 7 is the waveform diagram of the output signal of the SR flip-flop U6 in this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, rather than all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present utility model.

[0036] This embodiment provides a clock signal source capable of outputting a two-phase clock reference signal that fully meets the requirements of a lock-in amplifier; in a possible implementation manner, the specific structure of the clock signal generator is as Figure 1as shown

[0037] In some specific embodiments, the clock signal generator includes an input terminal IO4 for inputting an excitation signal. It should be noted that the excitation signal input to the input terminal IO4 must be symmetric. Otherwise, it is necessary to eliminate the DC offset through capacitive coupling or other methods before inputting to the input terminal IO4.

[0038] In some possible embodiments, the clock signal generator includes three output terminals IO1, IO2, and IO3. Among them, IO1 and IO2 are used to output quadrature clock signals (90° and 270°), and IO3 is used to output in-phase clock signals (0°).

[0039] In some possible embodiments, the clock signal generator includes a shaping circuit for generating an in-phase clock signal (0°), which specifically includes a comparator U1. As Figure 2 , when the signal input to the input terminal IO4 is greater than 0, the output of the comparator U1 is high level (H), and when the signal input to the input terminal IO4 is less than or equal to 0, the output of the comparator U1 is low level (L). In this way, the output signal of the comparator U1 is in phase with the sine signal input to the input terminal IO4.

[0040] In some specific embodiments, the output side of the comparator U1 is connected to the output terminal IO3, the positive input side is connected to the input terminal IO4, and the negative input side is grounded. The output signal of the comparator U1 is output through the output terminal IO3.

[0041] In some possible embodiments, the clock signal generator includes a peak detector (positive peak detector) for generating a reference voltage slightly lower than the peak value of the sine wave. The positive peak detector specifically uses a diode D1, a capacitor C1, and a resistor R1 to form a simple peak holding circuit, as Figure 3 , this circuit charges to a voltage slightly lower than the peak value at the rising edge of the sine wave (waveform V1) and holds this voltage at the falling edge until it is updated by the next peak.

[0042] In some specific embodiments, the specific connection manner of the diode D1, the capacitor C1, and the resistor R1 is as Figure 1 shown. The positive electrode of the diode D1 is connected to the input terminal IO4, the negative electrode is respectively connected to one end of the capacitor C1 and the resistor R1, and the other ends of the capacitor C1 and the resistor R1 are grounded. Specifically, the diode D1 is used to only allow the voltage to pass in the positive direction; the capacitor C1 is used to store the voltage value; the resistor R1 is used to control the discharge rate of the capacitor to ensure that the voltage remains relatively stable before the next peak arrives.

[0043] In some specific embodiments, a comparator U2 is provided on the output side of the positive peak detector. More specifically, the negative terminal of the input side of the comparator U2 is connected to the negative terminal of the diode, and the positive terminal of the input side of the comparator U2 is connected to the input terminal IO4. When the input sine wave exceeds the positive reference voltage generated by the positive peak detector, the comparator U2 generates a pulse signal (waveform V2), indicating the start of the quadrature clock signal.

[0044] In some possible embodiments, the clock signal generator includes a peak detector (negative peak detector) for generating a reference voltage slightly lower than the negative peak of the sine wave. Specifically, the negative peak detector uses a diode D2, a capacitor C2, and a resistor R2 to form a simple peak hold circuit, such as Figure 5 which charges to a voltage slightly lower than the negative peak at the falling edge of the sine wave and holds that voltage at the rising edge until it is updated by the next negative peak.

[0045] In some specific embodiments, the specific connection manner of the diode D2, the capacitor C2, and the resistor R2 is as shown in Figure 1 wherein the negative terminal of the diode D2 is connected to the input terminal IO4, the positive terminal is respectively connected to one end of the capacitor C2 and the resistor R2, and the other ends of the capacitor C2 and the resistor R2 are grounded. Specifically, the diode D2 is used to allow only voltages in the negative direction to pass through; the capacitor C1 is used to store the voltage value; the resistor R1 is used to control the discharge rate of the capacitor to ensure that the voltage can remain relatively stable before the next negative peak arrives.

[0046] In some specific embodiments, a comparator U3 is provided on the output side of the negative peak detector. More specifically, the positive terminal of the input side of the comparator U3 is connected to the negative terminal of the diode, and the negative terminal of the input side of the comparator U3 is connected to the input terminal IO4. When the signal voltage is lower than the reference voltage provided by the peak detector, the output of the comparator U3 becomes high level, that is, a pulse (high level) is generated when the sine wave is lower than the negative reference voltage. That is, whenever the sine wave reaches near the negative peak, U3 outputs a pulse signal (waveform V3), indicating the end of the quadrature clock signal.

[0047] In some possible embodiments, the clock signal generator further includes an SR flip-flop U6 (Set-Reset flip-flop). The SR flip-flop U6 includes an S (Set) terminal connected to the output side of the comparator U2; an R (Reset) terminal connected to the output side of the comparator U3; a Q output terminal connected to the output terminal IO1; and a ~Q output terminal connected to the output terminal IO2.

[0048] As shown in Figure 7When the S terminal receives a high-level pulse, the SR flip-flop U6 enters the set state (waveform V4), and the Q output terminal outputs a signal with a 90° phase difference from the sine wave through the output terminal IO1. When the R terminal receives a high-level pulse (waveform V5), the SR flip-flop enters the reset state, and the ~Q output terminal outputs a signal with a 270° phase difference from the sine wave through the output terminal IO2.

[0049] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims

1. A two-phase clock signal generating circuit, characterized in that, It includes an input terminal IO4, a comparator U1, an output terminal IO3, a comparator U2, a positive peak detector, a negative peak detector, a comparator U3, an SR flip-flop U6, and an output port; the input terminal IO4 is connected to the positive electrode of the input side of the comparator U1, the negative electrode of the input side of the comparator U1 is grounded, and the output side is connected to the output terminal IO3; one end of the positive peak detector is connected to the input terminal IO4, and the other end is connected to the negative electrode of the input side of the comparator U2; the positive electrode of the input side of the comparator U2 is connected to the input terminal IO4, and the output side is connected to the S terminal of the SR flip-flop U6; the negative peak detector, one end is connected to the input terminal IO4, and the other end is connected to the positive electrode of the input side of the comparator U3; the comparator U3, the negative electrode of the input side is connected to the input terminal IO4, and the output side is connected to the R terminal of the SR flip-flop U6; the SR flip-flop U6 is connected to the output port.

2. The two-phase clock signal generating circuit according to claim 1, wherein The output port includes an output terminal IO1 and an output terminal IO2, the Q output terminal of the SR flip-flop U6 is connected to the output terminal IO1, and the ~Q output terminal is connected to the output terminal IO2.

3. A two-phase clock signal generating circuit according to claim 2, wherein The output terminal IO1 outputs a 90° quadrature phase clock signal; the output terminal IO2 outputs a 270° quadrature phase clock signal.

4. A two-phase clock signal generating circuit according to claim 1, wherein The output terminal IO3 outputs a in-phase clock signal.

5. A two-phase clock signal generating circuit according to claim 1, wherein The input of the input terminal IO4 is a symmetric excitation signal.

6. A two-phase clock signal generating circuit according to claim 1, characterized in that The positive peak detector specifically includes a diode D1, a capacitor C1, and a resistor R1; the positive electrode of the diode D1 is connected to the input terminal IO4, and the negative electrode is respectively connected to one end of the capacitor C1 and the resistor R1, and the other ends of the capacitor C1 and the resistor R1 are grounded.

7. A two-phase clock signal generating circuit according to claim 6, characterized in that, The negative electrode of the input side of the comparator U2 is connected to the negative electrode of the diode D1.

8. A two-phase clock signal generating circuit according to claim 1, wherein The negative peak detector specifically includes a diode D2, a capacitor C2, and a resistor R2, the negative electrode of the diode D2 is connected to the input terminal IO4, and the positive electrode is respectively connected to one end of the capacitor C2 and the resistor R2, and the other ends of the capacitor C2 and the resistor R2 are grounded.

9. A two-phase clock signal generating circuit according to claim 8, characterized in that, The positive electrode of the input side of the comparator U3 is connected to the positive electrode of the diode D2.

10. A two-phase clock signal generator, characterized in that, It includes the two-phase clock signal generating circuit according to any one of claims 1 to 9.

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