Trench gate silicon carbide VDMOS with low driving loss
By introducing a dual P-type well region structure and current redistribution layer into the silicon carbide VDMOS device, the problem of high driving loss in high-frequency applications is solved, the device's low driving voltage and low loss are achieved, and the device's reliability is improved.
Patent Information
- Application Number
- CN202422074725.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-08-26
AI Technical Summary
The existing silicon carbide VDMOS devices have high driving losses in high-frequency applications and have become an indispensable loss part, which requires reducing the driving voltage and driving losses of the device.
The low-drive loss trench gate silicon carbide VDMOS structure is adopted, including a dual P-type well region structure and current reallocation layer, which reduces the inverse equilibrium voltage and gate leakage capacitance of the device, and optimizes the current distribution to reduce driving loss.
It effectively reduces the driving voltage and driving loss of the device, improves the gate reliability of the device, and reduces the current impact at the gate corners.
Smart Images
Figure CN223157517U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a trench-gate silicon carbide VDMOS with low drive loss. Background Art
[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. The excellent switching characteristics of silicon carbide VDMOS devices are particularly obvious in high-frequency applications. As the switching frequency increases, at a certain operating frequency, the drive loss and conduction loss of the device can be comparable, and the drive loss becomes an important part of the device loss that cannot be ignored. Reducing the device drive loss is more important in silicon carbide devices. Summary of the Utility Model
[0003] The technical problem to be solved by the utility model is to provide a trench-gate silicon carbide VDMOS with low drive loss to reduce the device drive voltage and drive loss.
[0004] The utility model is realized as follows: A trench-gate silicon carbide VDMOS with low drive loss, comprising:
[0005] A silicon carbide substrate,
[0006] A current redistribution layer, the lower side of which is connected to the upper side of the silicon carbide substrate;
[0007] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate and the current redistribution layer;
[0008] A first P-type well region, the lower side of which is connected to the upper side of the drift layer, and a second P-type well region is provided on the first P-type well region;
[0009] A P-type source region, the lower side of which is connected to the upper side of the first P-type well region;
[0010] An N-type source region, the lower side of which is respectively connected to the upper sides of the first P-type well region and the second P-type well region, and the outer side of the N-type source region is connected to the inner side of the P-type source region;
[0011] A gate dielectric layer, the lower side of which is connected to the upper side of the drift layer, and the outer side of the gate dielectric layer is respectively connected to the first P-type well region, the second P-type well region, and the N-type source region; a trench is provided in the gate dielectric layer;
[0012] A gate metal layer, which is arranged in the trench;
[0013] A source metal layer, which is respectively connected to the N-type source region and the P-type source region;
[0014] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0015] The advantages of the present utility model are as follows:
[0016] 1. On the basis of the trench-gate VDMOS device structure, the device constructs a double P-type well region structure. The second P-type well region is lightly doped, reducing the total charge number in the well region for gate control inversion of the device, effectively reducing the inversion balance voltage of the device and the device drive voltage.
[0017] 2. A current redistribution layer is constructed above the silicon carbide substrate of the device, reducing the gate-drain capacitance of the device, effectively reducing the gate charge of the device, and reducing the device drive loss.
[0018] 3. The current redistribution layer of the device is distributed directly below the gate and on the left and right sides, which can laterally redistribute the current on the left and right sides of the gate to the entire area of the device at the drain, playing a role in current sharing.
[0019] 4. The current redistribution layer of the device can also concentrate the drain current towards the current redistribution region, avoiding the impact of the large drain current on the gate corners of the device and improving the gate reliability of the device. Description of the Drawings
[0020] The following further describes the present utility model with reference to the drawings in conjunction with embodiments.
[0021] Figure 1 It is a schematic diagram of a low-drive-loss trench-gate silicon carbide VDMOS of the present utility model.
[0022] Figure 2 It is a flowchart of a preparation method of a low-drive-loss trench-gate silicon carbide VDMOS of the present utility model.
[0023] Figure 3 It is a process cross-section of a low-drive-loss trench-gate silicon carbide VDMOS of the present utility model Figure 1 .
[0024] Figure 4 It is a process cross-section of a low-drive-loss trench-gate silicon carbide VDMOS of the present utility model Figure 2 .
[0025] Figure 5 It is a process cross-section of a low-drive-loss trench-gate silicon carbide VDMOS of the present utility model Figure 3 .
[0026] Figure 6 It is a process cross-section of a low-drive-loss trench-gate silicon carbide VDMOS of the present utility model Figure 4 .
[0027] Figure 7 Process cross-section of a trench-gate silicon carbide VDMOS with low drive loss according to the present utility model Figure 5 。
[0028] Figure 8 Process cross-section of a trench-gate silicon carbide VDMOS with low drive loss according to the present utility model Figure 6 。
[0029] Figure 9 Process cross-section of a trench-gate silicon carbide VDMOS with low drive loss according to the present utility model Figure 7 。
[0030] Figure 10 Process cross-section of a trench-gate silicon carbide VDMOS with low drive loss according to the present utility model Figure 8 。
[0031] Figure 11 Process cross-section of a trench-gate silicon carbide VDMOS with low drive loss according to the present utility model Figure 9 。
[0032] Figure 12 Process cross-section of a trench-gate silicon carbide VDMOS with low drive loss according to the present utility model Figure 10 。
[0033] Figure 13 Process cross-section of a trench-gate silicon carbide VDMOS with low drive loss according to the present utility model Figure 10 One.
[0034] Figure 14 Process cross-section of a trench-gate silicon carbide VDMOS with low drive loss according to the present utility model Figure 10 Two. Specific embodiments
[0035] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0037] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of the present utility model, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part.
[0038] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device during use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. Additionally, the device may also assume additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0039] As used herein, the singular forms "a", "an" and "the" may also include the plural, unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0040] As Figure 1 shown, embodiments of the present application provide a low-drive-loss trench-gate silicon carbide VDMOS, including:
[0041] a silicon carbide substrate 101,
[0042] Current redistribution layer 102, the lower side of the current redistribution layer 102 is connected to the upper side of the silicon carbide substrate 101;
[0043] Drift layer 103, the lower side of the drift layer 103 is connected to the upper side of the silicon carbide substrate 101 and the current redistribution layer 102;
[0044] First P-type well region 104, the lower side of the first P-type well region 104 is connected to the upper side of the drift layer 103, and a second P-type well region 1041 is provided on the first P-type well region 104;
[0045] P-type source region 105, the lower side of the P-type source region 105 is connected to the upper side of the first P-type well region 104;
[0046] N-type source region 106, the lower side of the N-type source region 106 is respectively connected to the upper side of the first P-type well region 104 and the upper side of the second P-type well region 1041, and the outer side of the N-type source region 106 is connected to the inner side of the P-type source region 105;
[0047] Gate dielectric layer 107, the lower side of the gate dielectric layer 107 is connected to the upper side of the drift layer 103, and the outer side of the gate dielectric layer 107 is respectively connected to the first P-type well region 104, the second P-type well region 1041 and the N-type source region 106; a trench 1071 is provided in the gate dielectric layer 107;
[0048] Gate metal layer 108, the gate metal layer 108 is provided in the trench 1071;
[0049] Source metal layer 109, the source metal layer 109 is respectively connected to the N-type source region 106 and the P-type source region 105;
[0050] And a drain metal layer 110, the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101.
[0051] As Figures 2 to 14 shown, the manufacturing method of the above-mentioned silicon carbide VDMOS includes the following steps:
[0052] Step 1, deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110, and epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 103;
[0053] Step 2, form a barrier layer a on the drift layer 103, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 103 to form a current redistribution layer 102, and the ion implantation energy is 10 - 100 kev;
[0054] Step 3: Remove the original barrier layer a, and epitaxially grow a drift layer 103 on the drift layer 103 and the current redistribution layer 102;
[0055] Step 4: Perform ion implantation on the drift layer 103 to form a first P-type well region 104 in the drift layer 103, and the ion implantation energy is 200 - 300 kev;
[0056] Step 5: Form a barrier layer a on the drift layer 103, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 103, and form a second P-type well region 1041 in the first P-type well region 104, and the ion implantation energy is 200 - 270 kev;
[0057] Step 6: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 103 to form a P-type source region 105, and the ion implantation energy is 100 - 200 kev;
[0058] Step 7: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 103 to form an N-type source region 106, and the ion implantation energy is 100 - 200 kev;
[0059] Step 8: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, etch the drift layer 103, the second P-type well region 1041, and the first P-type well region 104 to form a groove 111, the etching depth is 800 nm, perform dry oxidation in the groove 111 to form a gate dielectric layer 107, and a trench 1071 is provided in the gate dielectric layer 107;
[0060] Step 9: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, deposit metal to form a gate metal layer 108;
[0061] Step 10: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, etch the drift layer 103, the etching depth is 300 nm, deposit metal to form a source metal layer 109, remove the barrier layer a, and complete the preparation.
[0062] The doping concentration of the first P-type well region 104 is greater than that of the second P-type well region 1041. The lower side of the second P-type well region 1041 is in the same plane as the lower side of the gate metal layer 108. The current redistribution layer 102 includes a first distribution region 1021, a second distribution region 1022, and a third distribution region 1023. The first distribution region 1021, the second distribution region 1022, and the third distribution region 1023 are arranged at intervals, and the second distribution region 1022 is disposed directly below the gate dielectric layer 107, and the width of the second distribution region 1022 is equal to the width of the gate dielectric layer 107. The current redistribution layer 102, the silicon carbide substrate 101, and the drift layer 103 are all N-type. The doping concentration of the silicon carbide substrate 101 is 2e18cm -3 , and the doping concentration of the drift layer 103 is 5e16cm -3 , and the doping concentration of the current redistribution layer 102 is 5e17cm -3 , and the doping concentration of the first P-type well region 104 is 5e17 cm -3 , and the doping concentration of the second P-type well region 1041 is 1e17 cm -3 , and the doping concentration of the N-type source region 106 is 5e18cm -3 , and the doping concentration of the P-type source region 105 is 8e18cm -3 .
[0063] The gate dielectric layer 107 is silicon dioxide, the gate metal layer 108 is Al, the source metal layer 109 is Al, and the drain metal layer 110 is a Ni, Al alloy with a ratio of 2:8. The thickness of the silicon carbide substrate 101 of the device is 1μm, the thickness of the drift layer 103 is 20 - 30μm, the thickness of the current redistribution layer 102 is 300nm, the thickness of the first P-type well region 104 is 300nm, the thickness of the second P-type well region 1041 is 200nm, and its bottom is flush with the bottom of the gate metal layer 108. The width of the second P-type well region 1041 is 100nm. The bottom thickness of the gate dielectric layer 107 is 30nm, the sidewall thickness is 20nm, the thickness of the N-type source region 106 is 300nm, the thickness of the P-type source region 105 is 300nm, the thickness from the top of the source metal layer 109 to the top of the N-type source region 106 is 300nm, the thickness of the gate metal layer 108 is 800nm, and the breakdown voltage of the device is 1200 - 3000V;
[0064] The concentration of the silicon carbide substrate 101 is for forming a low-resistance ohmic contact with the drain metal layer 110 to reduce the on-resistance of the device, and its thickness is for ensuring support during device epitaxy and improving process stability. The doping concentration of the current redistribution layer 102 is for realizing the doping concentration transition between the silicon carbide substrate 101 and the drift layer 103 to ensure the function of current redistribution;
[0065] The current redistribution layer 102 can shield the capacitive effect from the gate to the n+ SiC substrate, reduce the gate-drain capacitance of the device, effectively reduce the gate charge of the device, and reduce the drive loss of the device.
[0066] The current redistribution layer 102 of the device can make the drain current concentrate in the current redistribution layer region, avoid the impact of the large drain current on the gate corner of the device, and improve the gate reliability of the device;
[0067] The doping concentration of the first P-type well region 104 of the device is greater than that of the second P-type well region 1041. Therefore, the first P-type well region 104 can achieve inversion and high electron concentration at a smaller gate voltage. This well region structure can reduce the gate drive voltage of the device, thereby reducing the drive loss of the device. The doping concentration of the first P-type well region 104 of the device is relatively high, and the bottom of the first P-type well region 104 is at the same height as the bottom of the gate dielectric layer 107, which can suppress the electric field concentration at the gate corner and improve the gate reliability.
[0068] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.
Claims
1. A low-drive-loss trench-gate silicon carbide VDMOS, characterized in that, Including: A silicon carbide substrate, A current redistribution layer, the lower side of which is connected to the upper side of the silicon carbide substrate; A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate and the current redistribution layer; A first P-type well region, the lower side of which is connected to the upper side of the drift layer, and a second P-type well region is provided on the first P-type well region; A P-type source region, the lower side of which is connected to the upper side of the first P-type well region; An N-type source region, the lower side of which is respectively connected to the upper sides of the first P-type well region and the second P-type well region, and the outer side of the N-type source region is connected to the inner side of the P-type source region; A gate dielectric layer, the lower side of which is connected to the upper side of the drift layer, and the outer side of the gate dielectric layer is respectively connected to the first P-type well region, the second P-type well region and the N-type source region; a trench is provided in the gate dielectric layer; A gate metal layer, which is provided in the trench; A source metal layer, which is respectively connected to the N-type source region and the P-type source region; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The low-drive-loss trench-gate silicon carbide VDMOS according to claim 1, wherein The doping concentration of the first P-type well region is greater than that of the second P-type well region.
3. A low-drive-loss trench-gate silicon carbide VDMOS as claimed in claim 1, characterized in that, The lower side of the second P-type well region and the lower side of the gate metal layer are in the same plane.
4. A low-drive-loss trench-gate silicon carbide VDMOS as claimed in claim 1, wherein The thickness of the current redistribution layer is 300 nm.
5. A low-drive-loss trench-gate silicon carbide VDMOS as claimed in claim 1, wherein The current redistribution layer includes a first distribution region, a second distribution region and a third distribution region, the first distribution region, the second distribution region and the third distribution region are arranged at intervals, and the second distribution region is provided directly below the gate dielectric layer, and the width of the second distribution region is equal to the width of the gate dielectric layer.
6. A low-drive-loss trench-gate silicon carbide VDMOS according to claim 1, characterized in that, The current redistribution layer, the silicon carbide substrate and the drift layer are all N-type.