Trench gate silicon carbide VDMOS with high switching speed
By adopting a trench gate structure and built-in Schott-matrix diode design in silicon carbide VDMOS, the device switching speed and loss problems are solved, achieving higher switching speed and lower loss.
Patent Information
- Application Number
- CN202422150980.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-03
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-09-03
AI Technical Summary
Existing silicon carbide VDMOS devices have shortcomings in switching speed and switching losses, which are difficult to meet high-performance requirements.
Using a trench gate structure, the thickness of the bottom of the gate dielectric layer is increased to 100nm, the P-type masking layer is eliminated, and an N-type silicon carbide material with high middle and low sides is built-in Schott-matrix diode to reduce on-resistance and reverse recovery time.
Improves the switching speed of the device, reduces switching losses and reverse recovery time, and enhances the reliability of the device.
Smart Images
Figure CN223157518U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a trench-gate silicon carbide VDMOS with high switching speed. Background Art
[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements for the device vary in different fields, but generally, the overall requirements include lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage shock reliability, etc.), and lower body diode conduction loss. Summary of the Utility Model
[0003] The technical problem to be solved by the utility model is to provide a trench-gate silicon carbide VDMOS with high switching speed, improve the switching speed of the device, reduce the switching loss of the device, and at the same time, reduce the body diode conduction loss of the device and improve the reverse recovery speed of the device.
[0004] The utility model is realized as follows: A trench-gate silicon carbide VDMOS with high switching speed, comprising:
[0005] A silicon carbide substrate, on which a raised portion is provided, a first groove is provided on the silicon carbide substrate, and an insulating layer is provided in the first groove;
[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; a second groove is provided on the drift layer;
[0007] A P-type well region, the lower side of which is connected to the upper side of the drift layer;
[0008] An N-type source region, which is connected to the P-type well region;
[0009] An N-type region, which is respectively connected to the upper side of the drift layer, the outer side of the N-type source region, and the P-type well region;
[0010] A gate dielectric layer, the lower part of which is provided in the second groove, and the outer side of the gate dielectric layer is respectively connected to the inner side of the N-type source region and the inner side of the P-type well region; a trench is provided in the gate dielectric layer;
[0011] A gate metal layer, which is provided in the trench;
[0012] A source metal layer, which is respectively connected to the N-type source region and the N-type region;
[0013] And a drain metal layer, which is respectively connected to the silicon carbide substrate and the insulating layer.
[0014] The advantages of the present utility model are as follows:
[0015] 1. Based on the trench gate structure, the present utility model increases the thickness of the bottom of the gate dielectric layer from the traditional 50 nm to 100 nm, so that the P-type mask layer can no longer be used to protect the device structure, eliminating the influence of the P-type mask layer on the on-resistance of the device;
[0016] 2. The bottom of the gate dielectric does not contain the device gate-controlled conductive channel, so this structural change does not affect the gate control ability of the device;
[0017] 3. An N-type silicon carbide material with a high middle and low sides is constructed above the drain metal of the device. This structure effectively reduces the distance from the gate to the drain of the device, can effectively suppress the gate-drain capacitance of the device, that is, the Miller capacitance, can reduce the turn-on and turn-off plateau periods of the device, and effectively improve the switching speed of the device;
[0018] 4. A Schottky substrate diode from the source metal to the N-type region is constructed inside the device, which can effectively reduce the body diode loss of the device, reduce the reverse recovery time of the device, and improve the switching speed of the device. Description of the Drawings
[0019] The following further describes the present utility model with reference to the drawings in conjunction with embodiments.
[0020] Figure 1 It is a schematic diagram of a trench-gate silicon carbide VDMOS with a high switching speed according to the present utility model.
[0021] Figure 2 It is a process cross-section of a trench-gate silicon carbide VDMOS with a high switching speed according to the present utility model Figure 1 .
[0022] Figure 3 It is a process cross-section of a trench-gate silicon carbide VDMOS with a high switching speed according to the present utility model Figure 2 .
[0023] Figure 4 It is a process cross-section of a trench-gate silicon carbide VDMOS with a high switching speed according to the present utility model Figure 3 .
[0024] Figure 5 It is a process cross-section of a trench-gate silicon carbide VDMOS with a high switching speed according to the present utility model Figure 4 .
[0025] Figure 6 It is a process cross-section of a trench-gate silicon carbide VDMOS with a high switching speed according to the present utility model Figure 5 .
[0026] Figure 7 Process cross-section of a trench-gate silicon carbide VDMOS with high switching speed according to the present utility model Figure 6 。
[0027] Figure 8 Process cross-section of a trench-gate silicon carbide VDMOS with high switching speed according to the present utility model Figure 7 。
[0028] Figure 9 Process cross-section of a trench-gate silicon carbide VDMOS with high switching speed according to the present utility model Figure 8 。
[0029] Figure 10 Process cross-section of a trench-gate silicon carbide VDMOS with high switching speed according to the present utility model Figure 9 。
[0030] Figure 11 Process cross-section of a trench-gate silicon carbide VDMOS with high switching speed according to the present utility model Figure 10 。
[0031] Figure 12 Process cross-section of a trench-gate silicon carbide VDMOS with high switching speed according to the present utility model Figure 10 I.
[0032] Figure 13 Schematic diagram of the insulating layer of a trench-gate silicon carbide VDMOS with high switching speed according to the present utility model. Specific embodiments
[0033] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0035] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of the present utility model, the first element, component, region, layer, doping type, or part discussed below may be referred to as a second element, component, region, layer, or part.
[0036] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" may include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0037] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0038] As Figures 1 to 12 shown, embodiments of the present application provide a trench-gate silicon carbide VDMOS with a high switching speed, including:
[0039] Silicon carbide substrate 1, on which there is a raised portion 11, and there is a first groove 12 on the silicon carbide substrate 1, and an insulating layer 121 is provided in the first groove 12; the raised portion 11 is trapezoidal or stepped; the insulating layer 121 is trapezoidal or stepped;
[0040] Drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1; there is a second groove 21 on the drift layer 2;
[0041] P-type well region 3, the lower side of which is connected to the upper side of the drift layer 2;
[0042] N-type source region 4, which is connected to the P-type well region 3;
[0043] N-type region 5, which is respectively connected to the upper side of the drift layer 2, the outer side of the N-type source region 4, and the P-type well region 3;
[0044] Gate dielectric layer 6, the lower part of which is provided in the second groove 21, and the outer side of the gate dielectric layer 6 is respectively connected to the inner side of the N-type source region 4 and the inner side of the P-type well region 3; there is a trench 61 in the gate dielectric layer 6;
[0045] Gate metal layer 7, which is provided in the trench 61;
[0046] Source metal layer 8, which is respectively connected to the N-type source region 4 and the N-type region 5;
[0047] And a drain metal layer 9, which is respectively connected to the silicon carbide substrate 1 and the insulating layer 121.
[0048] The thickness of the bottom of the gate dielectric layer 6 is 100 nm, the doping concentration of the N-type region 5 is less than that of the P-type well region 3, and the doping concentration of the P-type well region 3 is less than that of the N-type source region 4; the depth of the second groove 21 is equal to the thickness from the upper side of the trench 61 of the gate dielectric layer 61 to the bottom of the gate dielectric layer 6, the width of the upper side of the insulating layer 121 is greater than the width of the gate dielectric layer 6, and the P-type well region 3 is L-shaped.
[0049] As Figures 1 to 13 shown, the manufacturing method of the above-mentioned silicon carbide VDMOS includes the following steps:
[0050] Step 1, form a barrier layer a on the drain metal layer 9, etch the barrier layer a to form a through hole, and deposit to form the insulating layer 121;
[0051] Step 2, remove the barrier layer a, and deposit to form the silicon carbide substrate 1 above the drain metal layer 9 and the insulating layer 121;
[0052] Step 3: Epitaxially grow a drift layer 2 on the silicon carbide substrate 1; since the insulating layer 121 is nanoscale while the drift layer 2 is micron-scale, and the thickness of the drift layer 2 is more than ten times that of the insulating layer 121, during the epitaxial growth process, the upper surface of the drift layer 2 tends to be flat as the epitaxy grows, and no additional treatment is required;
[0053] Step 4: Ion implantation to form an N-type region 5 within the drift layer 2, with an ion implantation energy of 100 - 270 kev;
[0054] Step 4: Form a barrier layer a on the drift layer 2, etch the barrier layer a to form a through-hole, perform ion implantation to form a P-type well region 3 within the N-type region 5, with an ion implantation energy of 170 - 270 kev;
[0055] Step 5: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through-hole, perform ion implantation to form an N-type source region 4 within the N-type region 5 and the P-type well region 3, with an ion implantation energy of 100 - 200 kev;
[0056] Step 6: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through-hole, and etch the N-type region 5 and the drift layer 2 to form a second groove 21, oxidize to form a gate dielectric layer 6, and the gate dielectric layer 6 is provided with a groove 61;
[0057] Step 7: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through-hole, deposit metal to form a gate metal layer 7;
[0058] Step 8: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through-hole, etch the drift layer 2 until reaching the upper side of the N-type source region 4, deposit metal to form a source metal layer 8, and remove the barrier layer a to complete the preparation.
[0059] As Figure 13 shown, in this embodiment, preferably, the specific steps of Step 1 are as follows:
[0060] Step 11: Form a barrier layer a on the drain metal layer 9, etch the barrier layer a to form a through-hole, and deposit a first insulating material;
[0061] Step 12: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through-hole, and deposit a second insulating material; perform Step 12 at least once, and finally form the insulating layer 121, which can be trapezoidal or stepped.
[0062] In another embodiment of the present invention, the insulating layer 121 is silicon dioxide, and the doping concentration of the silicon carbide substrate 1 is 2e18 cm -3, the silicon carbide substrate 1 is N-type; the doping concentration of the drift layer 2 is 1e16 cm -3 , the drift layer 2 is N-type; the doping concentration of the N-type region 5 is 1e17 cm -3 , the doping concentration of the P-type well region 3 is 5e17 cm -3 , the gate dielectric layer 6 can be one or a combination of silicon dioxide, aluminum nitride, hafnium dioxide, etc., and the doping concentration of the N-type source region 4 is 2e18 cm -3 ;
[0063] The insulating layer 121 is silicon dioxide, which is to improve process compatibility and ensure the reliability of depositing N-type silicon carbide material above the insulating material. And setting this insulating layer 121 is to make the set shape of the silicon carbide substrate 1 formed, and can prevent the high voltage of the drain from easily impacting the gate structure of the device; the concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse breakdown voltage and on-resistance of the device; the doping concentration of the N-type region 5 is to reduce the on-resistance of the device, and at the same time form a Schottky metal rather than an ohmic contact with the source metal layer 8 to constitute a Schottky substrate diode inside the device; the P-type well region 3 is to control the turn-off characteristics of the device without affecting the gate control ability and the freewheeling ability of the Schottky diode of the device.
[0064] The thickness of the N-type silicon carbide substrate 1 of the present utility model is 1 μm, which is to ensure the support for the subsequent structure preparation of the device. The thickness of the N-type drift layer 2 is 15 - 25 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the N-type region 5 above the P-type well region 3 is 200 nm, and the thickness at the edge side of the P-type well region 5 is 500 nm. The width of the N-type source region 4 is 500 nm. The lateral width from the N-type region 5 to the P-type well region 3 of the device is related to the doping concentrations of the P-type well region 3 and the N-type region 5 to ensure that this region can be turned off when the device is under reverse breakdown voltage; the bottom thickness of the gate dielectric layer 6 is 100 nm, which is to protect the gate of the device and suppress the breakdown problem caused by the electric field concentration at the gate corner. The side thickness of the gate dielectric layer 6 is 50 nm. The thickness of the N-type source region 4 is 300 nm. The thickness of the P-type well region 3 at the contact region with the N-type source region 4 is 200 nm, and the thickness at the contact part with the N-type region 5 is 300 nm;
[0065] The N-type region 5 of the device is connected to the source metal layer 8, constituting a Schottky diode between the source metal and the N-type region 5, which can effectively reduce the on-voltage drop of the body diode of the device. The cathode distribution position of the Schottky diode of the device is the same as that of the cathode of the pn junction, but the Schottky diode has a faster reverse recovery and a lower on-voltage drop. Therefore, generally, the device has the characteristic of fast recovery;
[0066] On the basis of adopting a trench-gate structure, the thickness of the insulating medium at the bottom of the device is increased from the traditional 50 nm to 100 nm. As a result, it is not necessary to set a P-type masking layer at the bottom of the gate dielectric layer 6 to protect the device structure, eliminating the influence of the P-type masking layer on the on-resistance of the device. There is no device gate-controlled conductive channel at the bottom of the gate dielectric layer 6, so this structural change does not affect the gate control ability of the device;
[0067] An N-type silicon carbide substrate 1 with a high middle and low sides is constructed above the drain metal layer 9 of the device. This structure effectively reduces the distance from the gate to the drain of the device, can effectively suppress the gate-drain capacitance of the device, that is, the Miller capacitance, can reduce the on and off plateau periods of the device, and effectively improve the switching speed of the device. A Schottky body diode from the source metal to the N-type region is constructed inside the device, which can effectively reduce the body diode loss of the device, reduce the reverse recovery time of the device, and improve the switching speed of the device.
[0068] Although the specific implementation manners of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered by the scope protected by the claims of the present invention.
Claims
1. A trench-gate silicon carbide VDMOS with high switching speed, characterized in that: Comprising: A silicon carbide substrate, on which a raised portion is provided, a first groove is provided on the silicon carbide substrate, and an insulating layer is provided in the first groove; A drift layer, the lower side surface of which is connected to the upper side surface of the silicon carbide substrate; a second groove is provided on the drift layer; A P-type well region, the lower side surface of which is connected to the upper side surface of the drift layer; An N-type source region, which is connected to the P-type well region; An N-type region, which is respectively connected to the upper side surface of the drift layer, the outer side surface of the N-type source region, and the P-type well region; A gate dielectric layer, the lower part of which is provided in the second groove, and the outer side surface of which is respectively connected to the inner side surface of the N-type source region and the inner side surface of the P-type well region; a trench is provided in the gate dielectric layer; A gate metal layer, which is provided in the trench; A source metal layer, which is respectively connected to the N-type source region and the N-type region; And a drain metal layer, which is respectively connected to the silicon carbide substrate and the insulating layer.
2. The trench-gate silicon carbide VDMOS with high switching speed as described in claim 1, wherein: The depth of the second groove is equal to the thickness from the upper side surface of the trench of the gate dielectric layer to the bottom of the gate dielectric layer.
3. A trench-gate silicon carbide VDMOS with a high switching speed as claimed in claim 1, characterized in that: The thickness of the insulating layer is 300 - 600 nm.
4. A trench-gate silicon carbide VDMOS with high switching speed as claimed in claim 1, characterized in that: The width of the upper side surface of the insulating layer is greater than the width of the gate dielectric layer.
5. A trench-gate silicon carbide VDMOS with high switching speed as claimed in claim 1, characterized in that: The P-type well region is L-shaped.
6. A trench-gate silicon carbide VDMOS with a high switching speed as claimed in claim 1, characterized in that: The thickness of the bottom of the gate dielectric layer is 100 nm.