Silicon carbide VDMOS resistant to drain-source voltage overshoot

Abstract

The utility model provides a drain-source voltage overshoot resistant silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor), which is characterized in that a drift layer is connected to a silicon carbide substrate, and a conductive layer is arranged in the drift layer; a P-type source region, an N-type source region, an insulating medium layer and a P-type well region are arranged on the drift layer, the P-type source region is connected to the drift layer, the P-type source region is respectively connected with the N-type source region and the insulating medium layer, the N-type source region is connected to the insulating medium layer, the insulating medium layer is connected to the P-type well region, the insulating medium layer and the N-type source region are both connected to the P-type well region, and a groove is formed in the drift layer; the masking layer is arranged in the groove; the gate dielectric layer is arranged in the groove, the gate dielectric layer is connected to the masking layer, the gate dielectric layer is respectively connected with the drift layer and the P-type well region, and a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the P-type source region, the N-type source region and the P-type well region; and the drain metal layer is connected to the silicon carbide substrate, so that the switching speed is improved while the drain voltage impact resistance of the device is improved.

Description

Technical Field

[0001] The utility model relates to a silicon carbide VDMOS resistant to drain-source voltage overshoot. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. The development of device structures and manufacturing processes promotes the reduction of the on-resistance of devices and the improvement of reliability. For trench-gate devices, they have the characteristic of low on-resistance, but they are easily damaged irreversibly by occasional voltage impacts on the drain. Therefore, improving the voltage impact resistance of the drain-source can effectively improve the reliability of the device, which is a technical problem that urgently needs to be solved. Content of the Utility Model

[0003] The technical problem to be solved by the utility model is to provide a silicon carbide VDMOS resistant to drain-source voltage overshoot, which improves the voltage impact resistance of the drain while increasing the switching speed.

[0004] The utility model is realized as follows: A silicon carbide VDMOS resistant to drain-source voltage overshoot, comprising:

[0005] A silicon carbide substrate;

[0006] A drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a conductive layer is provided in the drift layer; a P-type source region, an N-type source region, an insulating dielectric layer, and a P-type well region are provided on the drift layer. The lower side of the P-type source region is connected to the drift layer, the inner side of the P-type source region is respectively connected to the outer side of the N-type source region and the outer side of the insulating dielectric layer, the lower side of the N-type source region is connected to the upper side of the insulating dielectric layer, the lower side of the insulating dielectric layer is connected to the P-type well region, the inner side of the insulating dielectric layer and the inner side of the N-type source region are both connected to the P-type well region, and a groove is provided on the drift layer;

[0007] A masking layer, the masking layer is provided in the groove;

[0008] A gate dielectric layer, the gate dielectric layer is provided in the groove, and the lower side of the gate dielectric layer is connected to the upper side of the masking layer. The outer side of the gate dielectric layer is respectively connected to the drift layer and the P-type well region, and a trench is provided in the gate dielectric layer;

[0009] A gate metal layer, the gate metal layer is provided in the trench;

[0010] A source metal layer, the source metal layer is respectively connected to the P-type source region, the N-type source region, and the P-type well region;

[0011] And a drain metal layer, the drain metal layer is connected to the lower side of the silicon carbide substrate.

[0012] The advantages of the present utility model are as follows:

[0013] First, the present utility model adopts a trench gate structure, and the device has the characteristic of low on-resistance;

[0014] Second, the present utility model constructs a layer of insulating medium under the N-type source region, and this insulating medium can shield the voltage overshoot from the drain of the device, avoiding the impact of the drain voltage overshoot on the source structure after being inverted through the well region, and improving the ability to withstand the drain-source voltage overshoot;

[0015] Third, the N-type source of the present utility model is located directly above the insulating medium and has a distance of 30 nm from the gate dielectric layer of the device. This distance is partially the P-type well region. When the drain voltage overshoot occurs, pn junction inversion continues upward in this region. Since the thickness of this part is greater than the thickness of the P-type well region under the insulating medium, the voltage-bearing capacity of this part is strong, and the drain-source voltage withstand ability can be increased;

[0016] Fourth, the P-type well region of the present utility model only wraps the N-type source region of the device and the insulating medium layer thereunder, and does not wrap the P-type source region, thus realizing the direct contact between the P-type source region and the N-type drift region, and reducing the on-resistance of the body diode;

[0017] Fifth, the P-type well region of the present utility model is wider than the N-type source region and the insulating medium layer, which is to avoid the conductive channel from the N-type source region to the N-type drift layer that may be caused by process errors and improve the device yield;

[0018] Sixth, the conductive layer of the present utility model realizes current sharing inside the device and reduces the on-resistance of the device;

[0019] Seventh, the P-type masking layer of the present utility model is to protect the corner of the gate of the device from being broken down by electric field concentration and improve the reliability of the device gate. Description of the Drawings

[0020] The following further describes the present utility model with reference to the accompanying drawings in conjunction with embodiments.

[0021] Figure 1 It is the schematic diagram of a silicon carbide VDMOS withstanding drain-source voltage overshoot of the present utility model.

[0022] Figure 2 It is the process cross-section of a silicon carbide VDMOS withstanding drain-source voltage overshoot of the present utility model Figure 1 .

[0023] Figure 3 It is the process cross-section of a silicon carbide VDMOS withstanding drain-source voltage overshoot of the present utility model Figure 2 .

[0024] Figure 4Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 3 。

[0025] Figure 5 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 4 。

[0026] Figure 6 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 5 。

[0027] Figure 7 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 6 。

[0028] Figure 8 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 7 。

[0029] Figure 9 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 8 。

[0030] Figure 10 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 9 。

[0031] Figure 11 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 10 。

[0032] Figure 12 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 10 I.

[0033] Figure 13 Process cross-section of a silicon carbide VDMOS with resistance to drain-source voltage overshoot according to the present utility model Figure 10 II. Specific embodiments

[0034] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0036] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, a first element, component, region, layer, doping type or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of the present invention.

[0037] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over" and the like may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0038] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0039] As Figure 1 shown, an embodiment of the present application provides a silicon carbide VDMOS resistant to source-drain voltage overshoot, including:

[0040] A silicon carbide substrate 1;

[0041] A drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and a conductive layer 21 is provided in the drift layer 2; a P-type source region 22, an N-type source region 23, an insulating dielectric layer 24, and a P-type well region 25 are provided on the drift layer 2. The lower side of the P-type source region 22 is connected to the drift layer 2, the inner side of the P-type source region 22 is respectively connected to the outer side of the N-type source region 23 and the outer side of the insulating dielectric layer 24, the lower side of the N-type source region 23 is connected to the upper side of the insulating dielectric layer 24, the lower side of the insulating dielectric layer 24 is connected to the P-type well region 25, the inner side of the insulating dielectric layer 24 and the inner side of the N-type source region 23 are both connected to the P-type well region 25, and a groove 26 is provided on the drift layer 2;

[0042] A masking layer 3, the masking layer 3 is provided in the groove 26;

[0043] A gate dielectric layer 4, the gate dielectric layer 4 is provided in the groove 26, and the lower side of the gate dielectric layer 4 is connected to the upper side of the masking layer 3. The outer side of the gate dielectric layer 4 is respectively connected to the drift layer 2 and the P-type well region 25, and a trench 41 is provided in the gate dielectric layer;

[0044] A gate metal layer 5, the gate metal layer 5 is provided in the trench 41;

[0045] A source metal layer 6, the source metal layer 6 is respectively connected to the P-type source region 22, the N-type source region 23, and the P-type well region 25;

[0046] And a drain metal layer 7, the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1.

[0047] As Figures 1 to 13 shown, the manufacturing method of the above-mentioned silicon carbide VDMOS includes the following steps:

[0048] Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form the drain metal layer 7; epitaxially grow on the upper side of the silicon carbide substrate 1 to form the drift layer 2;

[0049] Step 2: Form the conductive layer 21 by ion implantation of the drift layer 2, and the ion implantation energy is 300-400 kev;

[0050] Step 3: Form a blocking layer a on the drift layer 2, etch the blocking layer a to form a through hole, perform ion implantation on the drift layer 2 to form a masking layer 3, and the ion implantation energy is 200 - 230 kev;

[0051] Step 4: Remove the blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, perform ion implantation on the drift layer 2 to form a P-type well region 25, and the ion implantation energy is 10 - 170 kev;

[0052] Step 5: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, and etch the P-type well region 25, then deposit to form an insulating dielectric layer 24, and the etching depth is 500 nm;

[0053] Step 6: Deposit to form an N-type source region 23;

[0054] Step 7: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, perform ion implantation on the drift layer 2 and the P-type well region 25 to form a P-type source region 22, and the ion implantation energy is 10 - 100 kev;

[0055] Step 8: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, etch the P-type well region 25 and the drift layer 2 until the upper side of the masking layer 3, and oxidize to form a gate dielectric layer 4, and a trench 41 is provided in the gate dielectric layer 4;

[0056] Step 9: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, deposit metal to form a gate metal layer 5;

[0057] Step 10: Remove the original blocking layer a, reform the blocking layer a, etch the blocking layer a to form a through hole, deposit metal to form a source metal layer 6, and remove the blocking layer a to complete the preparation.

[0058] The doping concentration of the masking layer 3 is greater than that of the conductive layer 21, the doping concentration of the conductive layer 21 is greater than that of the drift layer 2, the masking layer 3 is P-type, and the silicon carbide substrate 1, the conductive layer 21, and the drift layer 2 are all N-type.

[0059] In a specific embodiment, the doping concentration of the silicon carbide substrate 1 is 2e18 cm -3 , the doping concentration of the N-type drift layer 2 is 6e16 cm -3 , the doping concentration of the conductive layer 21 is 5e17 cm -3 , the doping concentration of the P-type masking layer 3 is 1e18 cm -3 , the doping concentration of the P-type well region 25 is 5e17 cm -3, the insulating dielectric layer 24 can be one or a combination of silicon dioxide, aluminum nitride, and hafnium dioxide. The doping concentration of the N-type source region 23 is 2e18 cm -3 , and the doping concentration of the P-type source region 22 is 1e19 cm -3 ; The concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 7 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The conductive layer 21 and its doping concentration are to evenly distribute the current from the N-type source region 23 on both sides of the gate inside the device, avoiding the phenomenon of burnout caused by excessive electric field density due to current concentration. The P-type masking layer 3 is to suppress the electric field concentration at the gate corner of the device and the influence of the drain voltage impact on the gate of the device. The doping concentrations of the N-type source region 23 and the P-type source region 22 are to form an ohmic contact with the source metal and reduce the contact resistance.

[0060] The thickness of the N-type silicon carbide substrate 1 is 1 μm, the thickness of the N-type drift layer 2 is 15 - 25 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the conductive layer 21 is 300 nm, and the distance between the lower side of the conductive layer 21 and the upper side of the P-type masking layer 3 is 200 nm. The conductive layer 21 can effectively shield the capacitance effect of the gate on the drain, reduce the gate-drain charge of the device, and improve the switching speed of the device. The thickness of the P-type masking layer is 100 nm, which is to protect the gate of the device and suppress the breakdown problem caused by the electric field concentration at the gate corner; the thickness of the insulating dielectric layer 24 is 100 nm, the thickness of the P-type source region 22 is 300 nm, the thickness of the N-type source region 23 is 250 nm, the thickness of the part of the P-type well region 25 at the bottom of the insulating dielectric layer 24 is 150 nm, the thickness of the part of the P-type well region 25 at the bottom of the P-type source region 22 is 200 nm, the thickness of the P-type well region 25 under the source metal layer 6 is 500 nm, and the distance from the inner side of the N-type source region 23 to the outer side of the gate dielectric layer 4 is 30 nm. This is to ensure a trade-off among the gate control ability, the on-state ability, and the breakdown voltage ability of the device. The P-type well region 25 of the device only wraps the N-type source region 23 of the device and the insulating dielectric layer 24 below it, and does not wrap the P-type source region 22, thus achieving direct contact between the P-type source region 22 and the N-type drift region 2 and reducing the on-resistance of the body diode. The P-type well region 25 of the device is wider than the N-type source region 23, which is to improve the yield of the device;

[0061] An insulating dielectric layer 24 is constructed under the N-type source region 23 of the device. The insulating dielectric layer 24 can shield the voltage overshoot from the drain of the device, avoiding the impact of the drain voltage overshoot on the source structure after inversion through the P-type well region 25, and improving the ability to withstand the drain-source voltage overshoot; between the N-type source region 23 and the gate dielectric layer 4 is the P-type well region 25. When the drain voltage overshoot occurs, pn junction inversion continues upward in this region. Since the thickness of this part is greater than the thickness of the P-type well region under the insulating dielectric, the voltage-bearing capacity of this part is strong, which can increase the ability to withstand the drain-source voltage.

[0062] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A silicon carbide VDMOS resistant to drain-source voltage overshoot, characterized in that, Comprising: A silicon carbide substrate; A drift layer, the lower side surface of the drift layer is connected to the upper side surface of the silicon carbide substrate, and a conductive layer is provided in the drift layer; A P-type source region, an N-type source region, an insulating dielectric layer, and a P-type well region are provided on the drift layer. The lower side surface of the P-type source region is connected to the drift layer, the inner side surface of the P-type source region is respectively connected to the outer side surface of the N-type source region and the outer side surface of the insulating dielectric layer, the lower side surface of the N-type source region is connected to the upper side surface of the insulating dielectric layer, the lower side surface of the insulating dielectric layer is connected to the P-type well region, the inner side surface of the insulating dielectric layer and the inner side surface of the N-type source region are both connected to the P-type well region, and a groove is provided on the drift layer; A masking layer, the masking layer is provided in the groove; A gate dielectric layer, the gate dielectric layer is provided in the groove, and the lower side surface of the gate dielectric layer is connected to the upper side surface of the masking layer. The outer side surface of the gate dielectric layer is respectively connected to the drift layer and the P-type well region, and a trench is provided in the gate dielectric layer; A gate metal layer, the gate metal layer is provided in the trench; A source metal layer, the source metal layer is respectively connected to the P-type source region, the N-type source region, and the P-type well region; And a drain metal layer, the drain metal layer is connected to the lower side surface of the silicon carbide substrate.

2. The silicon carbide VDMOS resistant to drain-source voltage overshoot according to claim 1, characterized in that The masking layer is P-type, and the silicon carbide substrate, the conductive layer, and the drift layer are all N-type.

3. The silicon carbide VDMOS with leakage source voltage overshoot resistance according to claim 1, characterized in that, The thickness of the conductive layer is 300 nm.

4. The silicon carbide VDMOS resistant to source voltage overshoot as described in claim 1, wherein The distance between the upper side surface of the conductive layer and the upper side surface of the drift layer is 200 nm.

5. The silicon carbide VDMOS resistant to drain-source voltage overshoot according to claim 1, wherein The thickness of the masking layer is 100 nm.

6. The silicon carbide VDMOS resistant to drain-source voltage overshoot according to claim 1, wherein The distance between the inner side surface of the N-type source region and the outer side surface of the gate dielectric layer is 30 nm.

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