Electrostatic protection device

Abstract

The utility model relates to the field of electronic science and technology, in particular to an electrostatic protection device, which comprises an N-single crystal wafer, a cathode metal layer and an anode metal layer, a first P-region, a third P + region and a second P-region are sequentially arranged in the N-single crystal wafer, a first P + region, a first N + region and a second P + region are sequentially arranged in the first P-region, and a second P + region is sequentially arranged in the second P + region. A fourth P + region, a second N + region and a fifth P + region are sequentially arranged in the second P-region; a discontinuous silicon dielectric layer is arranged on the surface of the N-single crystal wafer, the first P + region, the first N + region and the second P + region are all connected with the cathode metal layer, and the fourth P + region, the second N + region and the fifth P + region are all connected with the anode metal layer. According to the utility model, the symmetrical SCR structure with two short-circuited sides is introduced, so that the deep flyback characteristics in two directions are symmetrical, and the effective area of the SCR structure for determining the bleeder current capability is only the same as that of C1 (or C2) in a conventional structure, so that the chip area can be reduced by 20-40%, and lower breakdown voltage can be obtained under the condition of smaller chip area.

Description

Technical Field

[0001] The utility model belongs to the field of electronic science and technology, mainly relates to the field of integrated circuit electrostatic discharge (ESD - Electrostatic Discharge) protection, and specifically relates to an electrostatic protection device. Background Art

[0002] The electrostatic discharge (ESD) phenomenon is an important cause of damage and failure of integrated circuits. Integrated circuits are vulnerable to ESD during production, manufacturing, and operation, resulting in internal damage to the products, thereby weakening the product performance and reducing the reliability. Therefore, ESD protection devices with excellent performance play a more important role. The design of ESD protection devices needs to consider the following issues: one is strong ESD anti-interference ability; the second is to be able to discharge large currents; the third is to have a low parasitic capacitance.

[0003] Devices commonly used for ESD protection include diodes, BJTs (bipolar junction transistors), SCRs (silicon controlled rectifiers), etc. Due to the introduction of the injection modulation effect, the BJT structure obtains a shallow snapback characteristic. The SCR structure realizes a deep snapback characteristic through the positive feedback mechanism of PNPN. In terms of the residual voltage parameter, the SCR structure is the lowest, the BJT structure is the second, and the diode structure is the highest. Therefore, the SCR structure is beneficial to obtaining a higher discharge current.

[0004] Figure 5 is a layout schematic diagram of a conventional electrostatic protection device. The structure at the A - A' position is as Figure 4 shown. On the N - single crystal wafer 101, front - side photolithography, boron implantation, and drive - in are performed to form the P - region 102. Front - side photolithography, phosphorus implantation, and drive - in are performed to form the N+ regions 103a, 103b. Front - side photolithography, boron implantation, and drive - in are performed to form the P+ regions 104a, 104b, 104c. Front - side photolithography, phosphorus implantation, and drive - in are performed to form the N+ region 105. The silicon surface dielectric layer 106 plays a role in dielectric isolation. The metal layer 107 and the metal layer 108 respectively represent the two electrode ports of the ESD protection device, namely the cathode and the anode. The equivalent circuit of the conventional electrostatic protection device is as Figure 6As shown, the equivalent circuit is a series connection of circuits C1 and C2. Both C1 and C2 can be equivalently formed by an SCR structure formed by the interconnection of PNP and NPN. The emitter region, base region, and collector region of the PNP are respectively composed of a P+ region 104a, an N - single crystal wafer 101, a P - region 102, and a P+ region 104c. The emitter region, base region, and collector region of the NPN are respectively composed of an N+ region 103b, a P - region 102, an N+ region 103a, and an N - single crystal wafer 101. The breakdown voltage VBR of the SCR = VBR(Z1), which is determined by the breakdown voltage of the Z1 diode. Z1 is composed of an N+ region 105 and a P+ region 104b. The impurity concentrations of the N+ region 105 and the P+ region 104b are generally 2E19 - 6E19 cm-3 and 1E19 - 3E19 cm-3 respectively, and the breakdown voltage formed by the two is 7 - 10V. To obtain a lower breakdown voltage, it is usually necessary to increase the impurity concentrations of the N+ region 105 and the P+ region 104b. However, if the impurity concentration is too high, the leakage current will increase rapidly, and the breakdown characteristic will show soft breakdown. At the same time, due to the ultra-high impurity concentrations of the N+ region 105 and the P+ region 104b, the capacitance of the SCR will also be increased. From Figure 5 The parameters of the SCR structure product shown in Figure 5 can generally be: VRWM = 5V, VBR(IT = 1mA) = 6 - 10V, IR(VR = 5V) ≤ 1uA, IPP(tp = 8 / 20us) ≥ 5A, Cj(f = 1MHz, VR = 0V) = 0.4 - 0.7pF, VESD(Contact Mode) ≥ ±15KV. Summary of the Invention

[0005] The purpose of the present invention is to provide an electrostatic protection device, so as to obtain a lower breakdown voltage with a smaller chip area through reasonable structural and technological designs.

[0006] To achieve the above purpose, the present invention provides the following technical solution: An electrostatic protection device includes an N - single crystal wafer, a cathode metal layer, and an anode metal layer. A first P - region, a third P+ region, and a second P - region are sequentially arranged in the N - single crystal wafer. A first P+ region, a first N+ region, and a second P+ region are sequentially arranged in the first P - region. A fourth P+ region, a second N+ region, and a fifth P+ region are sequentially arranged in the second P - region. A discontinuous silicon dielectric layer is provided on the surface of the N - single crystal wafer. The first P+ region, the first N+ region, and the second P+ region are all connected to the cathode metal layer. The fourth P+ region, the second N+ region, and the fifth P+ region are all connected to the anode metal layer.

[0007] Preferably, the first P - region, the N - single crystal wafer, and the second P - region respectively correspond to the emitter region, base region, and collector region of a PNP.

[0008] Preferably, the first N+ region, the first P- region, and the N- single crystal wafer respectively correspond to the emitter region, the base region, and the collector region of an NPN; the second N+ region, the second P- region, and the N- single crystal wafer respectively correspond to the emitter region, the base region, and the collector region of an NPN.

[0009] Preferably, the third P+ region, the N- single crystal wafer, and the fourth P+ region correspond to a Z2 triode, and the third P+ region, the N- single crystal wafer, and the fourth P+ region correspond to a Z2 triode.

[0010] Compared with the prior art, the beneficial effects of the present utility model are as follows: by introducing a symmetric SCR structure with bilateral short - circuit, the deep snap - back characteristics in two directions are symmetric, and the effective area of the SCR structure that determines the current discharge capacity is only the same as C1 (or C2) in the conventional structure, so that the chip area can be reduced by 20 - 40%, and a lower breakdown voltage can be obtained with a smaller chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural diagram of an electrostatic protection device of the present utility model.

[0012] Figure 2 It is a layout schematic diagram of an electrostatic protection device of the present utility model;

[0013] Figure 3 It is an equivalent circuit diagram of an electrostatic protection device of the present utility model;

[0014] Figure 4 It is a structural diagram of a conventional electrostatic protection device;

[0015] Figure 5 It is a layout schematic diagram of a conventional electrostatic protection device;

[0016] Figure 6 It is an equivalent circuit diagram of a conventional electrostatic protection device;

[0017] Figure 7 It is an IV characteristic curve diagram of an electrostatic protection device of the present utility model and a conventional electrostatic protection device. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Refer to Figure 1 and Figure 2, this utility model application protects an electrostatic protection device, which includes an N-monocrystalline wafer 109, a cathode metal layer 114, and an anode metal layer 115. In the N-monocrystalline wafer 109, a first P-region 110a, a third P+-region 112c, and a second P-region 110b are successively arranged. In the first P-region 110a, a first P+-region 112a, a first N+-region 111a, and a second P+-region 112b are successively arranged. In the second P-region 110b, a fourth P+-region 112d, a second N+-region 111b, and a fifth P+-region 112e are successively arranged. A discontinuous silicon dielectric layer 113 is arranged on the surface of the N-monocrystalline wafer 109. The first P+-region 112a, the first N+-region 111a, and the second P+-region 112b are all connected to the cathode metal layer 114, and the fourth P+-region 112d, the second N+-region 111b, and the fifth P+-region 112e are all connected to the anode metal layer 115.

[0019] According to the above structure, an embodiment is provided, and its layout schematic diagram is as Figure 2 shown, and the structure at the B-B' position is as Figure 1 shown: On the N-monocrystalline wafer 109, front-side photolithography, boron implantation, and drive-in are performed to form the first P-region 110a and the second P-region 110b. Front-side photolithography, phosphorus implantation, and drive-in are performed to form the first N+-region 111a and the second N+-region 111b. Front-side photolithography, boron implantation, and drive-in are performed to form the first P+-region 112a, the second P+-region 112b, the third P+-region 112c, the fourth P+-region 112d, and the fifth P+-region 112e. A dielectric layer is deposited on the surface to form the silicon dielectric layer 113. The cathode metal layer 114 and the anode metal layer 115 respectively represent the two electrode ports of this utility model, the cathode and the anode.

[0020] The equivalent circuit of this utility model is as Figure 3 shown, which is equivalent to a bilateral short-circuit symmetric SCR structure. The first P-region 110a, the N-monocrystalline wafer 109, and the second P-region 110b respectively correspond to the emitter region, the base region, and the collector region of a PNP; the first N+-region 111a, the first P-region 110a, and the N-monocrystalline wafer 109 respectively correspond to the emitter region, the base region, and the collector region of an NPN; the second N+-region 111b, the second P-region 110b, and the N-monocrystalline wafer 109 respectively correspond to the emitter region, the base region, and the collector region of an NPN. The third P+-region 112c, the N-monocrystalline wafer 109, and the fourth P+-region 112d correspond to a Z2 triode, and the third P+-region 112c, the N-monocrystalline wafer 109, and the fourth P+-region 112d also correspond to a Z2 triode.

[0021] The volt-ampere characteristic curve of this utility model is as Figure 7As shown, when the cathode metal layer 114 is connected to a high potential and the anode metal layer 115 is connected to a low potential, the current sequentially passes through the first P-region 110a, the N-single crystal wafer 109, the second P-region 110b, and the second N+ region 111b, showing the deep backscattering characteristics of the SCR. The breakdown voltage of the Z2 triode composed of the third P+ region 112c, the N-single crystal wafer 109, and the fourth P+ region 112d is much lower than the breakdown voltage of the NP junction composed of the N-single crystal wafer 109 and the fourth P+ region 112d. Therefore, the breakdown starts from the Z2 triode first. When the current increases to the point where the PN junction voltage drop between the second P-region 110b and the second N+ region 111b reaches the turn-on voltage of the PN junction, 0.7V, the NPN composed of the second N+ region 111b, the second P-region 110b, and the N-single crystal wafer 109 as the emitter region, base region, and collector region, respectively, conducts. When the current further increases, the PNP composed of the first P-region 110a, the N-single crystal wafer 109, and the second P-region 110b as the emitter region, base region, and collector region, respectively, also conducts. The NPN and PNP then initiate a positive feedback mechanism, forming the conduction of the SCR structure and obtaining the deep backscattering characteristics. When the anode metal layer 115 is connected to a high potential and the cathode metal layer 114 is connected to a low potential, the current sequentially passes through the second P-region 110b, the N-single crystal wafer 109, the first P-region 110a, and the first N+ region 111a, showing the deep backscattering characteristics of the SCR. Since the present invention is an SCR structure with bilateral short circuits, the deep backscattering characteristics in both directions are symmetric.

[0022] The breakdown voltage VBR of the SCR of the present invention = VBR(Z2), which is determined by the breakdown voltage of the punch-through type Z2 triode. The Z2 triode is composed of the third P+ region 112c, the N-single crystal wafer 109, the fourth P+ region 112d or the second P+ region 112b, and the breakdown voltage depends on Figure 1 the spacing d therein. d represents the distance from the third P+ region 112c to the fourth P+ region 112d or the second P+ region 112b. When d = 0.3 - 0.6um, VBR = VBR(Z2) can reach 3 - 6V. In addition, compared with the conventional electrostatic protection device structure, the present invention introduces a symmetric SCR structure with bilateral short circuits. The effective area of the SCR structure that determines the current discharge capacity is only the same as C1 (or C2) in the conventional structure Figure 4 、 Figure 5 Therefore, the chip area of the present invention can be reduced by 20 - 40%.

[0023] The parameters of the SCR structure product of the present utility model can be achieved through the above structural and technological optimizations as follows: VRWM = 1.5V, VBR(IT = 1mA) = 3.0 - 6.0V, IR(VR = 1.5V) ≤ 1uA, IPP(tp = 8 / 20us) ≥ 5A, Cj(f = 1MHz, VR = 0V) = 0.4 - 0.7pF, VESD(Contact Mode) ≥ ±15KV.

[0024] In summary, the present utility model provides a new electrostatic protection device, which obtains a lower breakdown voltage with a smaller chip area through reasonable structural and technological designs.

[0025] Finally, it should be noted that the above are only the preferred embodiments of the present utility model and are not used to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. An electrostatic protection device, characterized in that: It includes an N-monocrystalline wafer, a cathode metal layer and an anode metal layer. A first P-region, a third P+-region and a second P-region are successively arranged in the N-monocrystalline wafer. A first P+-region, a first N+-region and a second P+-region are successively arranged in the first P-region. A fourth P+-region, a second N+-region and a fifth P+-region are successively arranged in the second P-region. A discontinuous silicon dielectric layer is arranged on the surface of the N-monocrystalline wafer. The first P+-region, the first N+-region and the second P+-region are all connected to the cathode metal layer. The fourth P+-region, the second N+-region and the fifth P+-region are all connected to the anode metal layer.

2. The electrostatic protection device according to claim 1, characterized in that: The first P-region, the N-monocrystalline wafer and the second P-region respectively correspond to the emitter region, the base region and the collector region of a PNP.

3. The electrostatic protection device according to claim 1, characterized in that: The first N+-region, the first P-region and the N-monocrystalline wafer respectively correspond to the emitter region, the base region and the collector region of an NPN. The second N+-region, the second P-region and the N-monocrystalline wafer respectively correspond to the emitter region, the base region and the collector region of an NPN.

4. The electrostatic protection device according to claim 1, wherein: The third P+-region, the N-monocrystalline wafer and the fourth P+-region correspond to a Z2 triode. The third P+-region, the N-monocrystalline wafer and the fourth P+-region correspond to a Z2 triode.

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