Short-circuit protection circuit and drive circuit of full-bridge inverter circuit

Abstract

The utility model discloses a short-circuit protection circuit and a drive circuit of a full-bridge inverter circuit, and the circuit collects the current of a full-bridge drive loop in the full-bridge inverter circuit through an independent short-circuit protection circuit, and converts the collected current into a corresponding voltage signal. And the independent short-circuit protection circuit judges the output short-circuit state of the full-bridge inverter circuit according to the voltage signal, and directly turns off or disables a half-bridge driving chip in the full-bridge inverter circuit when short circuit occurs. The short-circuit protection circuit scheme provided by the utility model can form short-circuit protection for driving when the full-bridge driving circuit outputs a short circuit to a power supply or the ground, so that the driving circuit is prevented from being damaged, and the reliability of the circuit is improved.

Description

Technical Field

[0001] The utility model relates to the technology of full-bridge inverter circuits, specifically to the short-circuit protection technology of full-bridge inverter circuits. Background Art

[0002] As a conversion circuit, the full-bridge inverter circuit can convert DC electrical energy into AC electrical energy and has a very wide range of applications. For example, the full-bridge drive circuit of automotive PDLC material dimming glass is constructed based on the full-bridge inverter circuit.

[0003] See Figure 1 , which shows an example of the composition of the basic full-bridge inverter of automotive PDLC material dimming glass. In such a full-bridge drive circuit, an SPWM signal is generated by a microcontroller unit (MCU) to control two groups of drive chips to perform sinusoidal pulse width modulation on the outputs of MOS transistors Q1, Q2, Q3, and Q4, so that an SPWM voltage waveform based on the HV voltage is output. Then, low-pass filtering is performed through inductors L1 / L2 and capacitors C1 respectively, and thus a 48V / 50Hz sinusoidal AC voltage is obtained across the PDLC as the PDLC drive power.

[0004] Accordingly, correspondingly, the peak value of the drive output voltage is close to 68V (48 times the square root of 2), and currently, the size of the conventional PDLC color-changing glass applied to automotive sunroofs is approximately 1m 2 or so, and the peak value of its drive current is close to 0.2A. Thus, higher requirements are imposed on the performance of MOS transistors Q1, Q2, Q3, and Q4 in the drive circuit, requiring that MOS transistors Q1, Q2, Q3, and Q4 have higher breakdown voltage performance and smaller operating current. When the SPWM modulation frequency is 50KHz, a 100V / 3A MOS transistor can fully meet the drive requirements (certain parameter reserves need to be considered when selecting MOS transistors, and MOS drive loss, switching loss, and conduction loss need to be considered when selecting current parameters). However, when the output is short-circuited to the power supply (12V) and the ground, the MOS transistor may be burned out due to overload.

[0005] Since the normal operating current is very small, although MOS transistors with a larger drive current can be selected to meet the short-circuit requirements, the cost performance is very low. Moreover, on the one hand, due to the relatively high operating voltage, currently available drive chips on the market do not have short-circuit protection functions. On the other hand, since the full-bridge output undergoes LC low-pass filtering, the inductance value is relatively large, and the full-bridge is constantly switching for SPWM modulation, so even if the drive chip has a short-circuit protection strategy, it cannot meet the short-circuit protection requirements at the final output end in this specific application.

[0006] Therefore, it can be seen that how to effectively prevent the drive circuit from being damaged when the output of the full-bridge inverter circuit is short-circuited to the power supply or the ground and improve the reliability of the circuit is an urgent problem to be solved in this field. Summary of the Invention

[0007] Aiming at the problems existing in the short - circuit protection of the existing full - bridge drive circuit, the purpose of the present utility model is to provide a short - circuit protection circuit for a full - bridge inverter circuit, which can protect the full - bridge drive circuit when the output of the full - bridge drive circuit is short - circuited to the power supply or the ground, avoid damage to the drive circuit, and improve the reliability of the drive circuit; on this basis, the present utility model further provides a full - bridge drive circuit adopting the short - circuit protection circuit of the full - bridge inverter circuit provided by this solution.

[0008] To achieve the above - mentioned purpose, the short - circuit protection circuit of the full - bridge inverter circuit provided by the present utility model includes an acquisition unit and a short - circuit protection unit. The acquisition unit is configured to be connected to the common - ground terminal of the full - bridge inverter circuit. The short - circuit protection unit is configured to be connected to the acquisition unit and is also connected to the control chip and the half - bridge drive chip in the full - bridge inverter circuit. The acquisition unit is configured to be able to detect the current of the full - bridge drive loop in the full - bridge inverter circuit. The short - circuit protection unit is configured to cooperate with the acquisition unit, be able to convert the acquired current into a corresponding voltage signal, and is configured to be able to judge the short - circuit state of the output of the full - bridge inverter circuit according to the voltage signal, and directly turn off or disable the half - bridge drive chip in the full - bridge inverter circuit when a short - circuit occurs.

[0009] In some embodiments of the present utility model, the short - circuit protection unit is further configured to be able to provide the obtained voltage signal to the control chip in the full - bridge inverter circuit for over - current and / or open - circuit diagnosis.

[0010] In some embodiments of the present utility model, the acquisition unit is composed of a sampling resistor.

[0011] In some embodiments of the present utility model, the short - circuit protection unit includes an acquisition and amplification circuit, a signal comparison circuit, a signal latching circuit, and an enable output circuit. The acquisition and amplification circuit can amplify the voltage signal and transmit the amplified voltage signal to the signal comparison circuit; the signal comparison circuit is configured with two reference voltages and compares the amplified voltage signal transmitted by the acquisition and amplification circuit through the two reference voltages to judge the short - circuit state of the output of the full - bridge inverter circuit, and forms a corresponding judgment signal, and transmits it to the signal latching circuit; the signal latching circuit is configured to act when the output of the full - bridge inverter circuit is short - circuited, and drive the output enable circuit to directly turn off or disable the half - bridge drive chip in the full - bridge inverter circuit.

[0012] In some embodiments of the present utility model, the acquisition and amplification circuit includes a differential amplifier circuit with voltage bias composed of an operational amplifier.

[0013] In some embodiments of the present utility model, two comparators and voltage-dividing resistors are provided in the signal comparison circuit, and different reference voltages corresponding to the two comparators are formed by voltage division of the voltage-dividing resistors.

[0014] In some embodiments of the present utility model, the signal latching circuit is configured to be able to receive a latching circuit reset signal given by a control chip in the full-bridge inverter circuit.

[0015] In some embodiments of the present utility model, a reset signal pull-down resistor is configured in the signal latching circuit.

[0016] In some embodiments of the present utility model, the control chip in the full-bridge inverter circuit is configured to be able to send a diagnostic signal to the short-circuit protection unit, and at the same time read the short-circuit protection unit status signal fed back by the short-circuit protection unit according to the diagnostic signal for diagnostic action, and then judge the working state of the short-circuit protection unit by analyzing the read short-circuit protection unit status signal.

[0017] To achieve the above object, the full-bridge inverter drive circuit provided by the present utility model includes the above-mentioned short-circuit protection circuit, and the short-circuit protection circuit is arranged in the full-bridge inverter drive circuit.

[0018] The solution of the present utility model provides a short-circuit protection circuit solution, which can form short-circuit protection for the drive when the output of the full-bridge drive circuit is short-circuited to the power supply or the ground, avoid damage to the drive circuit, and improve the reliability of the circuit.

[0019] The solution of the present utility model also configures a corresponding self-diagnosis method in the short-circuit protection circuit solution to diagnose whether the protection circuit is normal, ensure that the function of the protection circuit is normal before the drive output, and maximize the reliability of the output short-circuit protection.

[0020] The solution of the present utility model provides a short-circuit protection circuit solution that is stable, reliable and low-cost, and has very high practicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present utility model will be further described below in conjunction with the drawings and specific embodiments.

[0022] Figure 1 It is an example diagram of a full-bridge inverter drive circuit for existing PDLC material dimming glass;

[0023] Figure 2 It is a schematic diagram of the composition of the short-circuit protection circuit in the present utility model;

[0024] Figure 3 It is an example diagram of the topology of the basic full-bridge inverter circuit in the example of the present utility model;

[0025] Figure 4This is an example diagram of the normal operating state of the basic full-bridge inverter circuit in the embodiment of the present utility model;

[0026] Figure 5 This is an example diagram of the state where the output of the basic full-bridge inverter circuit in the embodiment of the present utility model is short-circuited to ground;

[0027] Figure 6 This is an example diagram of the normal operating state of the basic full-bridge inverter circuit in the embodiment of the present utility model;

[0028] Figure 7 This is an example diagram of the state where the output of the basic full-bridge inverter circuit in the embodiment of the present utility model is short-circuited to the power supply;

[0029] Figure 8 This is the schematic diagram of the composition of the short-circuit protection unit in the short-circuit protection circuit in the embodiment of the present utility model;

[0030] Figure 9 This is an example diagram of the composition of the full-bridge drive circuit of the PDLC material dimming glass with output short-circuit protection in the embodiment of the present utility model. Detailed implementation manners

[0031] In order to make the technical means, creative features, achieved purposes and effects realized by the present utility model easy to understand, the present utility model will be further described below with reference to specific diagrams.

[0032] In view of the circuit characteristics when the output of the full-bridge inverter circuit is short-circuited to ground or the power supply, the solution of the present utility model provides a corresponding short-circuit protection circuit. When the output of the full-bridge inverter circuit is short-circuited to the power supply or ground, the short-circuit protection circuit forms short-circuit protection to avoid damage to the drive circuit and improve the reliability of the circuit.

[0033] See Figure 1 , which shows the schematic diagram of the composition of the short-circuit protection circuit of the full-bridge inverter circuit given by the present utility model.

[0034] Combined with the diagram, the short-circuit protection circuit 100 of this full-bridge inverter circuit is independently arranged from the full-bridge inverter circuit 200, and mainly includes two parts: a collection unit 110 and a short-circuit protection unit 120. Among them, the collection unit 110 is arranged such that the collection end is connected to the common ground end of the full-bridge inverter circuit 200, and the output end is connected to the short-circuit protection unit 120; and the short-circuit protection unit 120 is arranged such that the input end is connected to the collection unit 110, and the output end is connected to the control chip 210 and the half-bridge drive chip 220 in the full-bridge inverter circuit 200.

[0035] On this basis, the acquisition unit 110 is configured to be able to detect the full-bridge drive loop current in the full-bridge inverter circuit 200, and the short-circuit protection unit 120 is configured to cooperate with the acquisition unit 110 to be able to convert the acquired current into a corresponding voltage signal. At the same time, the short-circuit protection unit 120 is also configured to be able to judge the short-circuit state of the output of the full-bridge inverter circuit 200 according to the acquired voltage signal, and when a short circuit occurs, directly turn off or disable the half-bridge drive chip 200 in the full-bridge inverter circuit, thereby protecting the output circuit from damage.

[0036] In some embodiments of the solution of the present invention, the acquisition unit 110 in the short-circuit protection circuit 100 is preferably composed of a sampling resistor Shunt to monitor the current of the drive circuit in real time.

[0037] The following is an example to illustrate the implementation mechanism and process of monitoring the current of the drive circuit in real time by using the sampling resistor Shunt as the acquisition unit 110 in the short-circuit protection circuit 100.

[0038] Here, take the full-bridge drive circuit of PDLC material dimming glass as an example, see Figure 3 , which shows the basic full-bridge inverter circuit topology in the full-bridge drive circuit of PDLC material dimming glass. Among them, MOS transistors HB_Q1, HB_Q2, HB_Q3, and HB_Q4 form the four bridge arms of the full-bridge inverter circuit. MOS transistors HB_Q1 and HB_Q3 are set to be turned on simultaneously, and MOS transistors HB_Q2 and HB_Q4 are set to be turned on simultaneously. MOS transistors HB_Q1 and HB_Q3 and MOS transistors HB_Q2 and HB_Q4 are alternately turned on according to a preset modulation method. A certain dead time needs to be satisfied when switching between the two groups to avoid short circuits caused by the simultaneous turning on of the two bridge arms on the same side.

[0039] Furthermore, inductors L1, L2 and filter capacitor Cfilter form an LC low-pass filter circuit to restore the modulated AC voltage waveform (usually a sine wave); PDLC (polymer dispersed liquid crystal, also known as PDLC (polymer dispersed liquid crystal)) is the load, and the overall characteristic is capacitive.

[0040] At the same time, a sampling resistor Shunt is added to the common ground terminal of the full-bridge inverter drive circuit to detect the current of the full-bridge drive loop.

[0041] On this basis, further see Figure 4 , when MOS transistors HB_Q1 and HB_Q3 are turned on and at the maximum duty cycle, V A The output voltage is the highest, and V B The output voltage at the end is the lowest. If the HV voltage is 68V, then V C And V A Are also basically 68V, VB and V D The voltage is close to the GND voltage of 0V.

[0042] See further Figure 5 , if V A terminal is shorted to GND at this time, the impact on the circuit is the greatest at this time. At this time, the V A voltage is instantly pulled down to 0V, and the V B voltage is instantly pulled to -68V because the voltage across the capacitor cannot change suddenly, and the inductor current cannot change suddenly. Therefore, the V C and V D voltages also become 0V and -68V respectively. At this time, as Figure 5 shown, impact currents I1 and I2 will be generated in the drive circuit; and by setting on the sampling resistor Shunt at the common ground terminal of the full-bridge inverter drive circuit, the reverse impact current can be detected.

[0043] See as Figure 6 , when the MOS transistors HB_Q2 and HB_Q4 are turned on and at the maximum duty cycle, the V A output voltage is the lowest, and the output voltage at the V B terminal is the highest. If the HV voltage is 68V, then the V B and V D are also basically 68V, and the V C and V A voltages are close to the GND voltage of 0V.

[0044] See further Figure 7 , if the V A terminal is shorted to the power supply of 12V at this time, the impact on the circuit is the greatest at this time. At this time, the V A voltage is instantly pulled down to 12V, and the V B voltage is instantly pulled to 80V because the voltage across the capacitor cannot change suddenly, and the inductor current cannot change suddenly. Therefore, the V C and V D voltages also become 12V and 80V respectively. At this time, as Figure 7 shown, impact currents I1 and I2 are generated in the drive circuit; and by setting on the sampling resistor Shunt at the common ground terminal of the full-bridge inverter drive circuit, the forward impact current can be detected.

[0045] In some embodiments of the solution of the present invention, see Figure 8 , the short-circuit protection unit 120 in the short-circuit protection circuit 100 mainly includes four parts: a collection and amplification circuit 121, a signal comparison circuit 122, a signal latching circuit 123, and an enable output circuit 124.

[0046] Specifically, the acquisition and amplification circuit 121 here is set to be connected to the acquisition unit 110 (i.e., the sampling resistor Shunt). At the same time, the acquisition and amplification circuit 121 is also connected to the signal comparison circuit 122 and the control chip 210 in the full-bridge inverter circuit. The acquisition and amplification circuit 121 configured in this way is capable of amplifying the voltage signal and transmitting the amplified voltage signal to the control chip 210 in the full-bridge inverter circuit and the signal comparison circuit 122.

[0047] As a further example, the acquisition and amplification circuit 121 preferably adopts a differential amplification circuit with voltage bias composed of operational amplifiers.

[0048] The signal comparison circuit 122 in the short-circuit protection unit 120 is set to be connected to the acquisition and amplification circuit 121 and the signal latching circuit 123. The signal comparison circuit 122 configured in this way is equipped with two reference voltages, and the amplified voltage signal transmitted by the acquisition and amplification circuit 121 is compared through the two reference voltages to judge the output short-circuit state of the full-bridge inverter circuit, and a corresponding judgment signal is formed and transmitted to the signal latching circuit 123.

[0049] As a further example, two reference voltages are formed in the signal comparison circuit 122 here through two comparators and resistors. These two reference voltages are one large and one small, corresponding to the states of the output short-circuit of the full-bridge inverter circuit to the power supply or the ground respectively.

[0050] As a further example, the signal comparison circuit 122 is configured to correspond to the output short-circuit state of the full-bridge inverter circuit through the high and low of the output signal. For example, when the output of the signal comparison circuit 122 is a low-level signal, it corresponds to the full-bridge inverter circuit being in the output short-circuit state; when the output of the signal comparison circuit 122 is in a high-impedance state, it corresponds to the full-bridge inverter circuit being in a non-output short-circuit state.

[0051] The signal latching circuit 123 in the short-circuit protection unit 120 is set to be connected to the signal comparison circuit 122 and the output enable circuit 124. The signal latching circuit 123 configured in this way is capable of performing corresponding actions according to the output signal of the signal comparison circuit 122:

[0052] When the output signal of the signal comparison circuit 122 corresponds to the output short-circuit state of the full-bridge inverter circuit, the signal latching circuit 123 acts to form a short-circuit protection signal to drive the output enable circuit to directly turn off or disable the half-bridge drive chip in the full-bridge inverter circuit and lock the short-circuit protection state;

[0053] When the signal comparison circuit 122 outputs other signals (i.e., output signals that do not correspond to the output short-circuit state of the full-bridge inverter circuit), the signal latching circuit 123 maintains its initial state.

[0054] As a further illustration, the signal latching circuit 123 in the short-circuit protection unit 120 is further configured to be connected to the control chip 210 in the full-bridge inverter circuit, and is capable of receiving the latching circuit reset signal given by the control chip 210 in the full-bridge inverter circuit and performing a reset according to the reset signal.

[0055] As a further example, the signal latching circuit 123 here can be configured to correspond to whether it enters the short-circuit protection state by the high or low level of the output signal:

[0056] When it is determined according to the output signal of the signal comparison circuit 122 that the full-bridge inverter circuit is in the output short-circuit state, the signal latching circuit 123 outputs a high-level signal as the short-circuit protection signal to drive the output enable circuit to act, and at the same time always maintains the output high-level signal to lock the short-circuit protection state;

[0057] When it is determined according to the output signal of the signal comparison circuit 122 that the full-bridge inverter circuit is in the non-output short-circuit state, the signal latching circuit 123 maintains its initial state and the output is pulled low, that is, it outputs a low-level signal and will not drive the output enable circuit to act.

[0058] The enable output circuit 124 in the short-circuit protection unit 120 is set to be connected to the signal latching circuit 123 and the half-bridge drive chip 220 in the full-bridge inverter circuit 200. The enable output circuit 124 configured in this way is capable of performing corresponding actions according to the output signal of the signal latching circuit 123:

[0059] When receiving the short-circuit protection signal output by the signal latching circuit 123, the enable output circuit 124 acts to directly turn off or disable the half-bridge drive chip 220 in the full-bridge inverter circuit, so that the function of the full-bridge drive chip 220 is disabled and the full-bridge output is turned off to enter the output short-circuit protection state;

[0060] When not receiving the short-circuit protection signal output by the signal latching circuit 123, the enable output circuit 124 does not act and the half-bridge drive chip 220 in the full-bridge inverter circuit works normally.

[0061] As a further example, the enable output circuit 124 here can be configured to correspond to the state of driving the half-bridge drive chip 220 in the full-bridge inverter circuit by the high or low level of the output signal, such as:

[0062] When receiving the short-circuit protection signal output by the signal latching circuit 123, the enable output signal Gate-Driver_EN of the enable output circuit 124 outputs a low-level signal, thereby directly turning off or disabling the half-bridge drive chip 220 in the full-bridge inverter circuit, so that the function of the full-bridge drive chip 220 is disabled and the full-bridge output is turned off to enter the output short-circuit protection state;

[0063] When no short - circuit protection signal output by the signal latching circuit 123 is received, the enable output signal Gate - Driver_EN of the enable output circuit 124 outputs a high - level signal, and the half - bridge driver chip 220 in the full - bridge inverter circuit operates normally.

[0064] In some embodiments of the solution of the present utility model, when this short - circuit protection circuit 100 cooperates with the full - bridge inverter circuit 200, the control chip 210 in the full - bridge inverter circuit 200 can perform self - diagnosis on the state of the short - circuit protection circuit 100.

[0065] Furthermore, the control chip 210 in the full - bridge inverter circuit can be configured to be able to send a diagnostic signal to the input end of the short - circuit protection circuit 100, and at the same time read the state signal of the short - circuit protection circuit 100 fed back according to the diagnostic signal for diagnostic actions by the short - circuit protection circuit 100, and then judge the working state of the short - circuit protection circuit 100 by analyzing the read state signal of the short - circuit protection circuit.

[0066] The following describes the process of the short - circuit protection circuit protecting the output of the full - bridge inverter circuit in combination with the short - circuit protection circuit composition solution of this full - bridge inverter circuit.

[0067] Combined Figure 8 As shown, first, this short - circuit protection circuit is set in the full - bridge inverter drive circuit, a sampling resistor Shunt(110) is added to the common - ground terminal of the full - bridge inverter drive circuit to detect the current of the full - bridge drive loop; at the same time, a short - circuit protection unit 120 composed of a collection and amplification circuit 121, a signal comparison circuit 122, a signal latching circuit 123, and an enable output circuit 124 is set between the control chip 210 and the half - bridge driver chip 220 in the full - bridge inverter drive circuit.

[0068] On this basis, the control chip 210 in the full - bridge inverter drive circuit first performs self - diagnosis on the working state of the set short - circuit protection circuit.

[0069] Specifically, the control chip 210 injects diagnostic signals (Test_P and Test_N) into the input end of the short - circuit protection circuit 100 respectively, and then reads the state of the short - circuit protection circuit from the short - circuit protection circuit state feedback pins (State_Diag and Current_Diag). If the read signal meets the requirements, it is judged that the short - circuit protection circuit works normally; otherwise, it is judged that the short - circuit protection circuit works abnormally and a prompt is given.

[0070] Next, during the operation of the full - bridge inverter drive circuit, the current of the full - bridge drive loop is monitored in real - time by the sampling resistor Shunt(110);

[0071] Meanwhile, the acquisition and amplification circuit 121 adopts a voltage-biased differential amplification circuit composed of operational amplifiers to amplify the subtle voltage changes generated by the current on the full-bridge inverter circuit through the sampling resistor Shunt. The amplified voltage signal Current_Diag is transmitted to the control chip 210 for overcurrent and open-circuit diagnosis on the one hand, and given to the signal comparison circuit 122 as the signal input for short-circuit protection on the other hand.

[0072] In the control chip 210, the current of the inverter full-bridge can be monitored in real time according to the signal transmitted by the acquisition and amplification circuit 121; when the current exceeds a certain threshold, the control chip 210 can execute corresponding overcurrent protection strategies; when the current is less than a certain threshold, the control chip 210 can execute corresponding open-circuit protection strategies.

[0073] Meanwhile, in the signal comparison circuit 122, two reference voltages, one large and one small, are formed based on two comparators and resistors for comparison and judgment, that is, two different reference voltages corresponding to the two comparators are formed by voltage division of the voltage-dividing resistors, and the two comparators respectively make comparison and judgment based on the corresponding reference voltages:

[0074] When the Current_Diag voltage is between the two reference voltages, the signal comparison circuit 122 outputs a high-impedance state signal;

[0075] When the Current_Diag voltage is greater than the large reference voltage or less than the small reference voltage, it indicates that the output of the full-bridge inverter circuit is short-circuited to the power supply or ground (that is, when the output of the full-bridge inverter circuit is short-circuited to the ground or the power supply, it will cause the Current_Diag voltage to be greater than or less than the reference voltage), and the signal comparison circuit 122 outputs a low-level signal.

[0076] In coordination with this, when the signal comparison circuit 122 outputs a high-impedance state, the signal latch circuit 123 is in the initial state and the output is pulled low, that is, a low-level signal is output;

[0077] When the signal comparison circuit 122 outputs a low-level signal, it indicates that the full-bridge inverter circuit is in the state of output short-circuit to the power supply or ground. At this time, the signal latch circuit 123 outputs a high-level signal. Meanwhile, regardless of how the output of the signal comparison circuit 122 changes, the output of the signal latch circuit 123 always remains high level, locking the short-circuit protection state.

[0078] Furthermore, when the output of the signal latch circuit 123 is pulled low, that is, a low-level signal is output, the enable output signal Gate-Driver_EN of the enable output circuit 124 outputs high (consistent with MCU_Enable), and the half-bridge driver chip 220 in the full-bridge inverter circuit works normally;

[0079] When the signal latch circuit 123 outputs a high-level signal due to a short circuit in the full-bridge output, the Gate-Driver_EN signal of the enable output circuit 124 is pulled low. At this time, the function of the full-bridge driver chip is disabled, and the full-bridge output is turned off to form an output short-circuit protection function.

[0080] For the short-circuit protection circuit solution of the full-bridge inverter circuit provided by the present invention, the following will be further described through specific application examples.

[0081] In this example, the full-bridge drive circuit of PDLC material dimming glass is taken as an example. Refer to Figure 9 , which shows the full-bridge drive circuit of PDLC material dimming glass with output short-circuit protection constituted by the solution of the present invention.

[0082] The composition of the full-bridge inverter circuit in the full-bridge drive circuit of PDLC material dimming glass with output short-circuit protection in this example is as follows:

[0083] Among them, HV is the input voltage of the full-bridge inverter circuit, and a suitable input voltage is matched according to the finally required output inverter voltage. For example, when outputting a sinusoidal alternating current with an effective value of 48V, the input voltage HV is generally about 70V (for a sinusoidal voltage with an effective value of 48V, the peak value is close to 68V, and a certain margin needs to be considered for the inverter conversion to avoid waveform distortion of the conversion).

[0084] The MOS transistors HB_Q1, HB_Q2, HB_Q3, and HB_Q4 are the four bridge arms of the full-bridge inverter circuit, which are driven by a half-bridge driver chip and are switched and controlled by the PWM signal or SPWM signal given by the control chip MCU. The half-bridge driver chip also receives the Gate_Driver-EN signal converted by the MCU_Enable signal given by the MCU through the enable output circuit for enabling.

[0085] Further, when the MCU_Enable signal is high and the enable output circuit does not operate, the Gate_Driver-EN signal is also high. At this time, the half-bridge driver chip can output normally; when the MCU_Enable signal is low or the output enable circuit works, that is, Q3 is turned on and the Gate_Driver-EN signal is pulled low. At this time, the function of the half-bridge driver chip is enabled and cannot output, and the full-bridge output is turned off.

[0086] The inductor L1, L2 and the filter capacitor Cfilter constitute an LC low-pass filter circuit to restore the fundamental wave modulated by the full-bridge inverter circuit and obtain the finally desired output AC voltage waveform.

[0087] The PDLC is the load for the full-bridge drive circuit. Its main characteristic is capacitive. It accepts AC drive. When not powered on, it is in a full-fog state. When powered on, it presents different haze degrees according to different AC drive voltages. Generally, it presents a nearly fully transparent state at 48VACrms.

[0088] Based on the above full-bridge inverter circuit, a sampling resistor Shunt is added to the common ground terminal of the further full-bridge inverter drive circuit as the full-bridge current sampling resistor, converting the current change of the full-bridge into a weak voltage change across Shunt and giving it to the current acquisition circuit.

[0089] Based on the above full-bridge inverter circuit, a current acquisition circuit is configured in this example to cooperate with the sampling resistor Shunt.

[0090] The current acquisition circuit in this example is specifically composed of a general-purpose operational amplifier U3, resistors R14, R15, R17, R18, R19, and R20 in cooperation.

[0091] Among them, the positive input terminal of the general-purpose operational amplifier U3 is respectively connected to one end of resistors R14, R15, and R16, and to the Test_P signal pin of the control chip MCU; the negative input terminal of the general-purpose operational amplifier U3 is respectively connected to one end of resistors R17, R18, and R19, and to the Test_N signal pin of the control chip MCU; the positive power supply pin of the general-purpose operational amplifier U3 is connected to the working power supply; the output of the general-purpose operational amplifier U3 is connected to one end of resistor R20 and the other end of resistor R17.

[0092] The other end of resistor R14 is connected to the working power supply VCC, and the other end of resistor R15 is connected to one end of the sampling resistor Shunt; the other end of resistor R18 is connected to the other end of the sampling resistor Shunt; the other ends of resistor R16 and resistor R19 are grounded.

[0093] In the thus formed current acquisition circuit, the general-purpose operational amplifier U3 is used to amplify the weak voltage signal across the sampling resistor Shunt, so that the final output voltage can not only meet the requirements of the MCU for diagnosing overcurrent or open circuit output, but also meet the signal requirements of the output short-circuit protection voltage comparison circuit.

[0094] Resistors R15, R17, and R18 cooperate to form an amplification factor adjustment circuit. The resistances of resistors R15 and R18 are the same. By adjusting their ratio to resistor R17, the voltage amplification factor of the operational amplifier circuit can be obtained. For example, if the resistances of resistors R15 and R18 are 1KΩ and the resistance of R17 is 100KΩ, the circuit amplification factor is 100 times.

[0095] Resistors R14, R16, and R19 cooperate to form a voltage bias circuit, adding a fixed voltage bias to the input signal.

[0096] Since the basic working principle of the operational amplifier differential sampling circuit is as follows:

[0097] V out = K(U p - U n ), V out is the output voltage of the operational amplifier, K is the operation proportional coefficient, U p is the positive terminal voltage of the sampling resistor Shunt, and U n is the negative terminal voltage of the sampling resistor Shunt.

[0098] Among them, since the operational amplifier is powered by a single power supply, V out can only be a positive voltage. If no voltage bias is added to the output terminal, the circuit can only collect current in one direction, that is, U p must be U n .

[0099] In this solution, a formed voltage bias circuit is formed to increase the bias voltage, and the working principle of the current acquisition circuit is: V out = K(U p + U ref - U n ), U ref is the added positive bias voltage. In this way, the current acquisition circuit can collect positive and negative currents, that is, within a certain range, U p voltage can be less than U n . Thus, the acquisition performance and reliability of the entire current acquisition circuit are effectively improved.

[0100] Among them, the resistances of resistors R16 and R19 are quite the same. By adjusting their ratio to resistor R14, the required bias voltage can be obtained. When the input voltage (the voltage across Shunt) is 0V, the output voltage is not 0V, which is the bias voltage; when the input voltage is a positive voltage (the voltage across Shunt is higher at the top and lower at the bottom in the figure), the output voltage is the input voltage plus the bias voltage and then multiplied by the amplification factor; when the input voltage is a negative voltage (the voltage across Shunt is lower at the top and higher at the bottom in the figure), the output voltage is the bias voltage minus the absolute value of the input voltage and then multiplied by the amplification factor. Thus, it can effectively realize adding current sampling through the common ground terminal of the full-bridge inverter circuit and simultaneously realizing short-circuit-to-power-supply and short-circuit-to-ground protection.

[0101] Resistor R20 serves as the output current limiting resistor of the current acquisition circuit to prevent the output voltage from being too high and damaging the MCU port.

[0102] On the above basis, a signal comparison circuit is configured in this example to cooperate with the current acquisition circuit.

[0103] The signal comparison circuit in this example is specifically composed of a voltage comparator U1, a voltage comparator U2, resistors R1, R2, R3, R4, R5, and a capacitor C1 working together.

[0104] Among them, the positive input terminal of the voltage comparator U1 is respectively connected to one end of the resistor R1 and the resistor R2; the negative input terminal of the voltage comparator U1 is connected to one end of the resistor R3 and the positive input terminal of the voltage comparator U2; the output terminal of the voltage comparator U1 is connected to the output terminal of the voltage comparator U2 and one side of the capacitor C1. The negative input terminal of the voltage comparator U2 is connected to one end of the resistors R4 and R5.

[0105] The other ends of the resistor R1 and the resistor R5 are respectively grounded, and the other ends of the resistor R2 and the resistor R4 are respectively connected to the working power supply voltage VCC; the resistor R3 is connected to the other end of the resistor R20 and the Current_Diag signal pin of the control chip MCU; the other side of the capacitor C1 is grounded.

[0106] In the signal comparison circuit formed thereby, the voltage comparator U1 and the voltage comparator U2 cooperate. When the voltage at the non-inverting input terminal is higher than the voltage at the inverting input terminal, a high-impedance state is output (the output of the comparator is usually in an open-drain configuration); on the contrary, the output of the comparator is low, and at this time the signal latch circuit will act.

[0107] The resistors R1 and R2, and R4 and R5 respectively divide the voltage of VCC to obtain two different reference voltages, which are respectively given to the non-inverting input terminal and the inverting input terminal of the voltage comparator U1 and the voltage comparator U2.

[0108] Among them, the reference voltage formed by the resistors R1 and R2 is larger, generally close to the VCC voltage (for example, if VCC is 5V, this reference voltage can be 4.5V). When the Current_Diag voltage is less than this reference voltage, the output of the voltage comparator U1 is in a high-impedance state, and when the Current_Diag voltage is greater than or equal to this reference voltage, the output of the voltage comparator U1 is low, and the signal latch circuit will act. The reference voltage formed by the resistors R4 and R5 is smaller, generally close to the GND voltage (such as 0.5V). When the Current_Diag voltage is greater than this reference voltage, the output of the voltage comparator U2 is in a high-impedance state, and when the Current_Diag voltage is less than or equal to this reference voltage, the output of the voltage comparator U2 is low, and the signal latch circuit will act.

[0109] The resistor R3 acts as a current-limiting resistor to play a certain stabilizing role on the Current_Diag signal entering the comparator; the capacitor C1 acts as an output filter of the signal comparison circuit to prevent possible jitter when the circuit is interfered by the outside world.

[0110] On the above basis, a signal latch circuit is configured in this example to cooperate with the signal comparison circuit.

[0111] The signal latching circuit in this example is specifically composed of a triode Q1, a triode Q2, resistors R6, R7, R8, R9, and R10 in cooperation.

[0112] Among them, the emitter of the triode Q1 is connected to the power supply voltage VCC and one end of the resistor R6, the collector of the triode Q1 is connected to one end of the resistor R8, and the base of the triode Q1 is connected to the other end of the resistor R6 and one end of the resistor R7.

[0113] The emitter of the triode Q2 is connected to the Reset signal pin of the control chip MCU, one end of the resistor R10, and one end of the resistor R9; the collector of the triode Q2 is connected to the other end of the resistor R7 and the output ends of the voltage comparators U1 and U2; the base of the triode Q2 is connected to the other ends of the resistor R9 and the resistor R8; the other end of the resistor R10 is grounded.

[0114] In the signal latching circuit thus formed, the resistors R6 and R9 serve as the bias resistors of the triodes Q1 and Q2 respectively, and the resistors R7 and R8 are the current-limiting resistors for the bases of the triodes Q1 and Q2 respectively.

[0115] On this basis, when the signal comparison circuit outputs a high impedance state, the signal latching circuit does not operate. Since the resistors R8 and R9 are connected to GND, the output of the signal latching circuit is low; when the signal comparison circuit outputs low, the triode Q1 of the signal latching circuit is turned on, and the output of the signal latching circuit changes from low to high. At the same time, the triode Q2 is turned on through the resistors R8 and R9 to maintain the low-level signal output by the signal comparison circuit, so that the output of the signal latching circuit remains high all the time.

[0116] The Reset signal here is the latching circuit reset signal given by the control chip MCU. When the level of the Reset signal changes from high to low, the latching circuit will be reset, and the output will become the initial state of low level.

[0117] The resistor R10 is configured as a pull-down for the Reset signal, thereby further improving the reliability of the entire short-circuit protection. When the Reset outputs low, the signal latching circuit works normally and receives the trigger signal from the signal comparison circuit; when the Reset outputs high, the signal will make the output of the signal latching circuit high through the resistors R9 and R8, so that the enable signal of the half-bridge drive chip will be pulled low, and the full bridge will not be able to output; when the Reset outputs a high impedance state, due to the pull-down of the resistor R10, the signal latching circuit can still work normally; in this way, regardless of the output state of the Reset signal of the control chip MCU, the short-circuit protection scheme of the output of this full-bridge circuit can directly disable the output or function normally, thereby effectively avoiding the loss of short-circuit protection function in the case of normal output of the full bridge due to software or MCU function abnormalities.

[0118] On this basis, in this embodiment, an output enable circuit is configured to cooperate with the signal latch circuit.

[0119] The output enable circuit in this embodiment is specifically composed of a triode Q3, a resistor R11, a resistor R12, a resistor R13, a resistor R21, and a capacitor C2 in cooperation.

[0120] Among them, the emitter of the triode Q3 is grounded; the collector of the triode Q3 is connected to the enable signal pin (MCU_Enable) of the half-bridge drive chip of the control chip MCU through the resistor R13, the resistor R21, and the drive chip; the base of the triode Q3 is connected to one end of the resistor R11, the resistor R12, and one side of the capacitor C2.

[0121] The other point of the resistor R21 is connected to the short-circuit protection circuit state diagnosis interface State_Diag of the control chip MCU; the other end of the resistor R11 is connected to the collector of the triode Q1 in the signal latch circuit; the other end of the resistor R12 and the other side of the capacitor C2 are grounded.

[0122] In the output enable circuit formed thereby, the resistor R11 serves as the base current-limiting resistor of the triode Q3; the resistor R12 serves as the base-emitter biasing resistor of the triode Q3; the capacitor C2 is configured as a filter capacitor for stabilizing the input signal and preventing misoperation; the triode Q3 is the key device of this circuit module. When the signal latch circuit outputs high, it is turned on to pull down the Gate_Driver-EN signal and disable the half-bridge drive chip.

[0123] The resistor R13 is the current-limiting resistor for the control chip MCU_Enable signal. On the one hand, it plays a certain role in stabilizing the signal of the control chip MCU, and on the other hand, it prevents the control chip MCU_Enable signal from overcurrent when the triode Q3 is turned on and pulled down.

[0124] The resistor R21 is the current-limiting resistor for the State_Diag signal of the control chip MCU, which stabilizes the signal and prevents overcurrent.

[0125] On this basis, in this embodiment, the control chip MCU serves as the control core of the entire drive circuit and is configured to handle the inverter conversion (PWM) of the full-bridge inverter circuit, the diagnosis of overcurrent and open circuit (Current_Diag), the enable of the half-bridge drive chip (MCU_Enable), the state diagnosis of the short-circuit protection circuit (State_Diag), the reset (Reset), the self-diagnosis signal (Test), etc. by the MCU.

[0126] Specifically, the control chip MCU is configured with State_Diag as the short-circuit protection circuit status diagnosis interface. When the full-bridge inverter circuit outputs normally, MCU_Enable outputs high, and the Reset signal outputs low, if the State_Diag level is high, it indicates that the hardware short-circuit protection has not been triggered. If the State_Diag level is low, it indicates that the hardware short-circuit protection has been triggered, and the MCU can execute corresponding diagnostic strategies accordingly.

[0127] The control chip MCU is configured with Test_P and Test_N as the self-diagnosis signals of the short-circuit protection circuit, which can cooperate with the short-circuit protection circuit to complete self-diagnosis.

[0128] On this basis, when the control chip MCU outputs a high level on MCU_Enable, outputs a level on Reset, and SPWM1 and SPWM2 do not output, the self-diagnosis of the protection circuit is performed.

[0129] Further, when Test_P and Test_N are digital signals:

[0130] When Test_P outputs a high level, since a high level is injected into the non-inverting input terminal of the current detection operational amplifier circuit, the entire sampling circuit should show that the forward current input is abnormally large. After passing through the operational amplifier circuit, if the MCU detects a voltage close to the bias voltage on Current_Diag before the diagnostic signal injection and detects a voltage close to the power supply after the diagnostic signal injection, it is determined that the non-inverting input terminal of the sampling circuit current is normal, otherwise it is abnormal; at the same time, if the MCU detects a high level on State_Diag before the diagnostic signal injection and a low level after the injection, it is determined that the voltage comparison circuit and the latch circuit are working normally, otherwise it is abnormal;

[0131] Similarly, when Test_N outputs a high level, since a high level is injected into the inverting input terminal of the current detection operational amplifier circuit, the entire sampling current should show that the reverse current input is abnormally large. After passing through the operational amplifier circuit, if the MCU detects a voltage close to the bias voltage on Current_Diag before the diagnostic signal injection and detects a voltage close to GND after the diagnostic signal injection, it is determined that the non-inverting input terminal of the sampling circuit current is normal, otherwise it is abnormal; at the same time, if the MCU detects a high level on State_Diag before the diagnostic signal injection and a low level after the injection, it is determined that the voltage comparison circuit and the latch circuit are working normally, otherwise it is abnormal.

[0132] Further, diodes D1 and D2 are respectively set at the output pins of Test_P and Test_N of the control chip MCU, which can prevent the influence of Test_P and Test_N on the protection circuit in the non-diagnostic mode.

[0133] As can be seen from the above examples, the short-circuit protection solution provided by the present utility model can form short-circuit protection for the output of the full-bridge drive circuit of PDLC material dimming glass; and cooperate with the corresponding self-diagnosis method to diagnose whether the protection circuit is normal, ensuring that the function of the protection circuit is normal before the drive output, and maximizing the reliability of the output short-circuit protection.

[0134] It should be noted here that the short-circuit protection solution provided by the present utility model is not only applicable to the full-bridge drive circuit of PDLC material dimming glass, but also applicable to other full-bridge drive circuits.

[0135] The above shows and describes the basic principles, main features and advantages of the present utility model. Those skilled in the art should understand that the present utility model is not limited by the above embodiments. The above embodiments and the descriptions in the specification only illustrate the principles of the present utility model. Without departing from the spirit and scope of the present utility model, the present utility model will have various changes and improvements, and these changes and improvements all fall within the scope of the present utility model claimed. The scope of protection claimed by the present utility model is defined by the appended claims and their equivalents.

Claims

1. Short-circuit protection circuit for a full-bridge inverter circuit, characterized in that, It includes a collection unit and a short - circuit protection unit. The collection unit is configured to be connected to the common ground terminal of the full - bridge inverter circuit. The short - circuit protection unit is configured to be connected to the collection unit and is also connected to the control chip and the half - bridge drive chip in the full - bridge inverter circuit. The collection unit is configured to be able to detect the current in the full - bridge drive loop of the full - bridge inverter circuit. The short - circuit protection unit is configured to cooperate with the collection unit, be able to convert the collected current into a corresponding voltage signal, and is configured to be able to judge the short - circuit state of the output of the full - bridge inverter circuit according to the voltage signal, and directly turn off or disable the half - bridge drive chip in the full - bridge inverter circuit when a short - circuit occurs.

2. The short-circuit protection circuit of the full-bridge inverter circuit according to claim 1, characterized in that The short - circuit protection unit is also configured to be able to provide the obtained voltage signal to the control chip in the full - bridge inverter circuit for over - current and / or open - circuit diagnosis.

3. The short-circuit protection circuit of the full-bridge inverter circuit according to claim 1, characterized in that The collection unit is composed of a sampling resistor.

4. The short-circuit protection circuit of the full-bridge inverter circuit according to claim 1, characterized in that The short - circuit protection unit includes a collection and amplification circuit, a signal comparison circuit, a signal latching circuit, and an enable output circuit. The collection and amplification circuit can amplify the voltage signal and transmit the amplified voltage signal to the signal comparison circuit. The signal comparison circuit is configured with two reference voltages and uses the two reference voltages to compare the amplified voltage signal transmitted by the collection and amplification circuit to judge the short - circuit state of the output of the full - bridge inverter circuit, and form a corresponding judgment signal, which is then transmitted to the signal latching circuit. The signal latching circuit is configured to act when the output of the full - bridge inverter circuit is short - circuited, and drive the output enable circuit to directly turn off or disable the half - bridge drive chip in the full - bridge inverter circuit.

5. The short-circuit protection circuit of the full-bridge inverter circuit according to claim 4, characterized in that, The collection and amplification circuit includes a differential amplifier circuit with voltage bias composed of an operational amplifier.

6. The short-circuit protection circuit of the full-bridge inverter circuit according to claim 4, characterized in that, Two comparators and voltage - dividing resistors are provided in the signal comparison circuit, and two different reference voltages corresponding to the two comparators are formed by voltage - dividing with the voltage - dividing resistors.

7. The short-circuit protection circuit of the full-bridge inverter circuit according to claim 4, characterized in that, The signal latching circuit is configured to be able to receive the latching - circuit reset signal given by the control chip in the full - bridge inverter circuit.

8. The short - circuit protection circuit of the full - bridge inverter circuit according to claim 4, characterized in that, A reset - signal pull - down resistor is configured in the signal latching circuit.

9. The short-circuit protection circuit of the full-bridge inverter circuit according to claim 1, characterized in that, The control chip in the full - bridge inverter circuit is configured to be able to send a diagnostic signal to the short - circuit protection unit, and at the same time read the short - circuit protection unit status signal fed back by the short - circuit protection unit according to the diagnostic signal for diagnosis action, and then judge the working state of the short - circuit protection unit by analyzing the read short - circuit protection unit status signal.

10. Full-bridge inverter drive circuit, characterized in that, It includes the short - circuit protection circuit according to any one of claims 1 - 9, and the short - circuit protection circuit is arranged in the full - bridge inverter drive circuit.

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