Signal selection circuit and fan adsorption system

Abstract

The utility model relates to a signal selection circuit and a fan adsorption system, the signal selection circuit comprises a signal selection operation module and a selection output module, the signal selection operation module comprises an AND gate logic circuit unit and an NAND gate logic circuit unit, the AND gate logic circuit unit is used for outputting a first selection signal when receiving a first signal, and the NAND gate logic circuit unit is used for outputting a second selection signal when receiving a second signal; or a first selection signal is output when the first signal and the second signal are received. And the NAND gate logic circuit unit is used for outputting a feedback signal to the AND gate logic circuit unit when receiving the second signal, so that the AND gate logic circuit unit outputs a second selection signal according to the second signal and the feedback signal. The selection output module is used for outputting a first analog signal when the control end receives the first selection signal and outputting a second analog signal when the control end receives the second selection signal. Through cooperation of the signal selection operation module and the selection output module, directional selection output of two paths of analog signals can be realized, a programming chip does not need to be arranged, and the circuit cost is effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of data detection equipment, and in particular to a signal selection circuit and a fan adsorption system. Background Art

[0002] In fan suction applications, such as those used in PCB (Printed Circuit Board) processing, ensuring stable suction of workpieces (such as PCBs) is crucial. Typically, fan suction systems employ a PID (Proportional-Integral-Derivative) control method, which precisely controls the output (i.e., suction force) by adjusting the system input in real time, maintaining it at a preset stable level. During this process, a vacuum pressure gauge continuously monitors the system's analog pressure signal, providing necessary feedback to the PID controller.

[0003] Because the fan adsorption system may have two independent adsorption platforms, one on the left and one on the right, each capable of independent adsorption, when the system is in single-axis processing mode, the system directly collects and uses the analog signal of that working axis to make adjustments to ensure the adsorption stability of the single platform. In dual-axis processing scenarios, the analog signal of one axis (such as the left axis) is selected as the reference, and the adsorption force of the entire system is uniformly adjusted to ensure synchronization and consistency between the two platforms.

[0004] Currently, programming chips are mostly used to form directional selection circuits for analog signals, and directional selection of analog signals of two axes is achieved through programming control. However, this circuit contains relatively high-cost programming chips, resulting in high circuit costs. Utility Model Content

[0005] Based on this, it is necessary to provide a signal selection circuit and a fan adsorption system that can directionally select two analog signals to address the above problems.

[0006] A signal selection circuit comprising:

[0007] The signal selection operation module includes an AND logic circuit unit and a NAND logic circuit unit. The signal feedback terminal of the AND logic circuit unit is connected to the signal feedback terminal of the NAND logic circuit unit. The signal output terminal of the AND logic circuit unit is connected to the control terminal of the selection output module. The signal input terminal of the AND logic circuit unit is used to access the first signal or the second signal. The AND logic circuit unit is configured to output the first selection signal when receiving the first signal, or output the first selection signal when receiving both the first signal and the second signal. The signal input terminal of the NAND logic circuit unit is used to access the second signal. The NAND logic circuit unit is configured to output a feedback signal to the AND logic circuit unit when receiving the second signal, so that the AND logic circuit unit outputs a second selection signal according to the second signal and the feedback signal.

[0008] The selection output module. The first input terminal of the selection output module is used to access the first analog signal transmitted externally, and the second input terminal of the selection output module is used to access the second analog signal transmitted externally. The control terminal of the selection output module is connected to the output terminal of the AND logic circuit unit. The selection output module is configured to output the first analog signal when the control terminal receives the first selection signal, and output the second analog signal when the control terminal receives the second selection signal.

[0009] In one embodiment, the AND logic circuit unit includes an AND device and a first resistor. The AND device includes at least a first AND logic circuit, a second AND logic circuit, a third AND logic circuit, and a fourth AND logic circuit.

[0010] The two input terminals of the first AND logic circuit are respectively used to access the first signal and the second signal, and the output terminal is used to output an operation signal.

[0011] The first input terminal of the second AND logic circuit is used to access the first signal, the second input terminal is connected to the output terminal of the first AND logic circuit, and the output terminal of the second AND logic circuit is connected to the control terminal of the selection output module and is used to output the first selection signal.

[0012] The first input terminal of the third AND logic circuit is used to access the first signal, the second input terminal is connected to the power supply through the first resistor, and the output terminal is connected to the control terminal of the selection output module and is used to output the first selection signal.

[0013] The first input terminal of the fourth AND logic circuit is used to access the second signal, the second input terminal is connected to the feedback terminal of the NAND logic circuit unit, and the output terminal is used to output the second selection signal.

[0014] In one embodiment, the AND logic circuit unit further includes a first diode and a second diode. The anode of the first diode is connected to the output terminal of the second AND logic circuit, and the cathode of the first diode is connected to the control terminal of the selection output module. The anode of the second diode is connected to the output terminal of the third AND logic circuit, and the cathode of the second diode is connected to the control terminal of the selection output module. The cathodes of the first diode and the second diode are connected together.

[0015] In one embodiment, the NAND logic circuit unit includes a NAND device and a second resistor. The NAND device includes at least one set of NAND logic circuits.

[0016] The first signal input terminal of the NAND logic circuit is used to receive the second signal. The second signal input terminal of the NAND logic circuit is connected to the output terminal of the first set of AND logic circuits. The third and fourth signal input terminals of the NAND logic circuit are both connected to the power supply through the second resistor. The feedback terminal of the NAND logic circuit is connected to the second input terminal of the fourth AND logic circuit, and the feedback terminal is used to output a feedback signal.

[0017] In one embodiment, the selection output module includes a first output unit and a second output unit.

[0018] The input terminal of the first output unit is used to receive the first analog signal. The control terminal of the first output unit is used to receive the first selection signal. The output terminal of the first output unit is used to output the first analog signal.

[0019] The input terminal of the second output unit is used to receive the second analog signal. The control terminal of the second output unit is used to receive the second selection signal. The output terminal of the second output unit is used to output the second analog signal.

[0020] In one embodiment, the first output unit includes a first relay, a first switch module, and a third diode. One end of the contact of the first relay is used to receive the first analog signal, and the other end is used to output the first analog signal. One end of the coil of the first relay and the cathode of the third diode are both connected to the power supply, and the other end is connected to the anode of the third diode and the first end of the first switch module. The second end of the first switch module is grounded, and the control terminal of the first switch module is used to receive the first selection signal.

[0021] The second output unit includes a second relay, a second switch module, and a fourth diode; one end of the contact of the second relay is used to access the second analog signal, and the other end is used to output the second analog signal; one end of the coil of the second relay and the cathode of the fourth diode are both connected to a power supply, and the other end is connected to the anode of the fourth diode and the first end of the second switch module. The second end of the second switch module is grounded, and the control end of the second switch module is used to access the second selection signal.

[0022] In one embodiment, the first switch module includes a first switching tube, a third resistor, a fourth resistor, and a first capacitor; the first end of the third resistor is used to access the first selection signal, the second end of the third resistor is connected to the first end of the fourth resistor, the first end of the first capacitor, and the control end of the first switching tube. The second end of the fourth resistor, the second end of the first capacitor, and the first end of the first switching tube are grounded; the second end of the first switching tube serves as the first end of the first switch module and is connected to the anode of the third diode;

[0023] The second switch module includes a second switching tube, a fifth resistor, a sixth resistor, and a second capacitor; the first end of the fifth resistor is used to access the second selection signal, the second end of the fifth resistor is connected to the first end of the sixth resistor, the first end of the second capacitor, and the control end of the second switching tube. The second end of the sixth resistor, the second end of the second capacitor, and the first end of the second switching tube are grounded; the second end of the second switching tube serves as the first end of the second switch module and is connected to the anode of the fourth diode.

[0024] In one embodiment, the signal selection circuit further includes a first signal detection unit and a second signal detection unit. The output end of the first signal detection unit is connected to the signal input end of the AND logic circuit unit. The input end of the first signal detection unit is used to access a first control signal. When the first control signal is received, the output end of the first signal detection unit outputs the first signal;

[0025] The output end of the second signal detection unit is respectively connected to the AND logic circuit unit and the NAND logic circuit unit. The input end of the second signal detection unit is used to access a second control signal. When the second control signal is received, the output end of the second signal detection unit outputs the second signal.

[0026] In one embodiment, the first signal detection unit includes a first optocoupler. The input side of the first optocoupler is used to access the first control signal, and the output side of the first optocoupler is connected to the signal input end of the AND logic circuit unit for outputting the first signal;

[0027] The second signal detection unit includes a second photoelectric coupler, the input side of the second photoelectric coupler is used to receive the second control signal, and the output side of the second photoelectric coupler is respectively connected to the AND gate logic circuit unit and the NAND gate logic circuit unit for outputting the second signal.

[0028] A fan adsorption system includes a first adsorption platform, a second adsorption platform, a first vacuum pressure detection module, a second vacuum pressure detection module, and the above-mentioned signal selection circuit; the first adsorption platform includes a first fluid channel and a first solenoid valve for controlling the first fluid channel; the second adsorption platform includes a second fluid channel and a second solenoid valve for controlling the second fluid channel;

[0029] The first vacuum pressure detection device is used to detect the air pressure in the first fluid channel and output the first analog signal; the second vacuum pressure detection device is used to detect the air pressure in the second fluid channel and output the second analog signal;

[0030] The first signal is generated based on a control signal of the first solenoid valve, and the second signal is generated based on a control signal of the second solenoid valve.

[0031] The above-mentioned signal selection circuit and fan adsorption system include a signal selection operation module and a selection output module. The signal selection operation module includes an AND gate logic circuit unit and a NAND gate logic circuit unit. The AND gate logic circuit unit is used to output a first selection signal when receiving a first signal, or output a first selection signal when receiving a first signal and a second signal. The NAND gate logic circuit unit is used to output a feedback signal to the AND gate logic circuit unit when receiving a second signal, so that the AND gate logic circuit unit outputs a second selection signal according to the second signal and the feedback signal. The selection output module is used to output a first analog signal when the control end receives the first selection signal, and output a second analog signal when receiving the second selection signal. Therefore, the directional selection output of two analog signals can be achieved through the cooperation of the signal selection operation module and the selection output module, without the need to set up a programming chip, which not only effectively reduces the circuit cost, but also eliminates the programming steps of the programming chip, greatly simplifying the design process. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a structural block diagram of a signal selection circuit in one embodiment;

[0033] Figure 2 This is a structural block diagram of a fan adsorption system in one embodiment;

[0034] Figure 3This is a structural schematic diagram of an AND gate logic circuit unit in one embodiment;

[0035] Figure 4 A partial structural schematic diagram of an AND gate logic circuit unit in one embodiment;

[0036] Figure 5 This is a schematic diagram of the structure of a NAND gate logic circuit unit in one embodiment;

[0037] Figure 6 A schematic diagram of the structure of an output module selected in one embodiment;

[0038] Figure 7 FIG. 4 is a schematic diagram of the structure of the first signal detection unit and the second signal detection unit in one embodiment. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] In one embodiment, a signal selection circuit is provided. Figure 1 As shown, the signal selection circuit includes a signal selection operation module 100 and a selection output module 200 .

[0041] Specifically, the signal selection operation module 100 includes an AND gate logic circuit unit 110 and a NAND gate logic circuit unit 120. The signal feedback terminal of the AND gate logic circuit unit 110 is connected to the signal feedback terminal of the NAND gate logic circuit unit 120, and the signal output terminal of the AND gate logic circuit unit 110 is connected to the control terminal of the selection output module 200. The signal input terminal of the AND gate logic circuit unit 110 is used to receive the first signal IN_01 or the second signal IN_02. The AND gate logic circuit unit 110 is used to output the first selection signal upon receiving the first signal IN_01, or to output the first selection signal upon receiving the first signal IN_01 and the second signal IN_02. The signal input terminal of the NAND gate logic circuit unit 120 is used to receive the second signal IN_02. The NAND gate logic circuit unit 120 is used to output a feedback signal to the AND gate logic circuit unit 110 upon receiving the second signal IN_02, so that the AND gate logic circuit unit 110 outputs the second selection signal based on the second signal IN_02 and the feedback signal.

[0042] The first input terminal of the selection output module 200 is used to receive a first analog signal MOD1 transmitted from an external source, and the second input terminal of the selection output module 200 is used to receive a second analog signal MOD2 transmitted from an external source. The control terminal of the selection output module 200 is connected to the output terminal of the AND gate logic circuit unit 110. The selection output module 200 outputs the first analog signal MOD1 when the control terminal receives a first selection signal, and outputs the second analog signal MOD2 when the control terminal receives a second selection signal.

[0043] For ease of understanding, Figure 1 In the embodiment, the first analog signal MOD1 input is represented as MOD1_INT, and the first analog signal MOD1 output is represented as MOD1_OUT; the second analog signal MOD2 input is represented as MOD2_INT, and the second analog signal MOD2 output is represented as MOD2_OUT.

[0044] In this embodiment, AND gate logic circuit unit 110 generates a first selection signal based on first signal IN_01. First signal IN_01 takes precedence over second signal IN_02. Even if IN_02 is present, IN_01 can still independently trigger the generation of the first selection signal. Thus, by employing AND gate logic circuit unit 110 and NOT gate logic circuit unit 120 and having them generate corresponding selection signals based on first signal IN_01 and second signal IN_02, it is possible to generate corresponding selection signals as needed, thus achieving output selection control for two analog signals.

[0045] The signal selection circuit can output the first analog signal MOD1_OUT when receiving the first signal IN_01; output the first analog signal MOD1_OUT when receiving the first signal IN_01 and the second signal IN_02; and output the second analog signal MOD2_OUT when receiving the second signal IN_02, thereby achieving directional selection of the two analog signals. Moreover, the signal selection circuit can achieve directional selection output of the two analog signals through the cooperation of the signal selection operation module 100 and the selection output module 200, without the need to set up a programming chip. This not only effectively reduces the circuit cost, but also eliminates the programming steps of the programming chip, greatly simplifying the design process. In addition, since there is no need for a programming chip, a series of connection components that match the programming chip, such as analog acquisition ports, input and output ports, etc., are further eliminated, thereby greatly simplifying the circuit structure and improving the simplicity of the circuit.

[0046] It should be noted that the above signal selection circuit can be applied to devices or systems that need to perform directional selection on two signals. The first signal IN_01, the second signal IN_02, the first analog signal MOD1 and the second analog signal MOD2 can all be configured based on actual applications.

[0047] In one embodiment, the signal selection circuit can be applied to a blower adsorption system. As Figure 2 shown, the blower adsorption system can include a first adsorption platform 310, a second adsorption platform 320, a first vacuum pressure detection module 410, a second vacuum pressure detection module 420, and a signal selection circuit. The first adsorption platform 310 includes a first fluid channel 311 and a first solenoid valve 312 for controlling the first fluid channel 311. The second adsorption platform 320 includes a second fluid channel 321 and a second solenoid valve 322 for controlling the second fluid channel 321.

[0048] The first vacuum pressure detection device 410 is used to detect the air pressure in the first fluid channel 311 and output the detection result, that is, the first analog signal MOD1_INT. The second vacuum pressure detection device 420 is used to detect the air pressure in the second fluid channel 321 and output the detection result, that is, the second analog signal MOD2_INT.

[0049] The first signal IN_01 is generated based on the control signal of the first solenoid valve 312, and the second signal IN_02 is generated based on the control signal of the second solenoid valve 322.

[0050] Specifically, when the first adsorption platform 310 is operating, when the first solenoid valve 312 receives the first control signal, under the control of the first control signal, the first solenoid valve 312 opens, so that adsorption gas is formed in the first fluid channel 311. When the second adsorption platform 320 is operating, when the second solenoid valve 322 receives the second control signal, under the control of the second control signal, the second solenoid valve 322 opens, so that adsorption gas is formed in the second fluid channel 321.

[0051] In one embodiment, when the voltage levels of the first control signal and the second control signal match the voltage level of the signal selection operation module 100 (for example, both voltage levels are 5V, or 24V, etc.), the first control signal can be directly used as the first signal IN_01, and the second control signal can be used as the second signal IN_02. When the voltage levels of the first control signal and the second control signal do not match the voltage level of the signal selection operation module 100, the first control signal and the second control signal can be processed by a specific intermediate circuit and then used as the first signal IN_01 and the second signal IN_02 respectively.

[0052] It can be understood that when the first solenoid valve 312 does not receive the first control signal, it is in a closed state, and the first vacuum pressure detection device 410 can be in a non-detection state, that is, it does not output the first analog signal MOD1_INT. The first vacuum pressure detection device 410 can also be in a detection state, but at this time the first adsorption platform 310 is not in an adsorption state, so the first analog signal MOD1_INT output by the first vacuum pressure detection device 410 at this time has no application significance.

[0053] Correspondingly, when the signal selection circuit does not receive the first signal IN_01, it will not output the first analog signal MOD1_OUT. Based on the same principle, when the signal selection circuit does not receive the second signal IN_02, it will not output the second analog signal MOD2_OUT. Thus, by accurately detecting the on-off state of the solenoid valve and determining whether the signal selection circuit transmits the first analog signal MOD1_OUT and the second analog signal MOD2_OUT based on the on-off state of the solenoid valve, the effectiveness of the signal transmission of the signal selection circuit is further enhanced.

[0054] Furthermore, the first analog signal MOD1_OUT and the second analog signal MOD2_OUT can be transmitted to the PID controller of the fan adsorption system, so that the PID controller can accurately control the output of the first adsorption platform 310 and the second adsorption platform 320, thereby improving the stable operation of the entire fan adsorption system and further ensuring the PCB through-hole processing quality.

[0055] Among them, the first adsorption platform 310 and the second adsorption platform 320 can be set according to the control requirements. For example, when the system is in a two-axis processing scenario and the analog signal of the left axis is directionally selected as the reference, correspondingly, the left adsorption platform can be used as the first adsorption platform 310, and the right adsorption platform can be used as the second adsorption platform 320. Thus, when the first adsorption platform 310 operates, the signal selection circuit outputs the first analog signal MOD1_OUT to the PID controller; when the second adsorption platform 320 operates, the signal selection circuit outputs the second analog signal MOD2_OUT to the PID controller; when the first adsorption platform 310 and the second adsorption platform 320 operate simultaneously, the first analog signal MOD1_OUT is directionally selected and output to the PID controller, so that the PID controller can achieve more reliable control according to the required analog signal. For the sake of understanding, the following will all be described with the signal selection circuit applied to the fan adsorption system.

[0056] It can be understood that the circuit structures of the AND logic circuit unit 110 and the NOT logic circuit unit 120 can be set according to specific circumstances during actual implementation. In one embodiment, such as Figure 3As shown, the AND logic circuit unit 110 may include an AND device U1 and a first resistor R16. The AND device U1 includes at least a first AND logic circuit, a second AND logic circuit, a third AND logic circuit, and a fourth AND logic circuit.

[0057] Two input terminals (illustrated as 4A and AB) of the first AND logic circuit are respectively used to access IN_01 and the second signal IN_02, and the output terminal (illustrated as 4Y) is used to output an operation signal SWA.

[0058] Thus, the first AND logic circuit outputs a high operation signal SWA only when receiving the first signal IN_01 and the second signal IN_02 simultaneously (both signals are at a high potential at this time).

[0059] The first input terminal (illustrated as 1A) of the second AND logic circuit is used to access the first signal IN_01, the second input terminal (illustrated as 1B) is connected to the output terminal of the first AND logic circuit to receive the SWA signal. The output terminal (illustrated as 1Y) of the second AND logic circuit is connected to the control terminal of the selection output module 200 to output a first selection signal ONE01.

[0060] The second AND logic circuit outputs a high first selection signal ONE01 when receiving the first signal IN_01 and the operation signal SWA simultaneously.

[0061] The first input terminal (illustrated as 3A) of the third AND logic circuit is used to access the first signal IN_01, the second input terminal (illustrated as 3B) is connected to the power supply VCC through the first resistor R16, and the output terminal (illustrated as 3Y) is connected to the control terminal of the selection output module 200 to output a first selection signal ONE02.

[0062] Among them, the power supply VCC can be set according to the specifically selected AND device U1, for example, 5V. Thus, the third AND logic circuit outputs a high first selection signal ONE02 when receiving the first signal IN_01 (in order to distinguish from the first selection signal ONE01 generated by the second AND logic circuit, the first selection signal generated by this third AND logic circuit is denoted as ONE02).

[0063] The first input terminal (illustrated as 2A) of the fourth AND logic circuit is used to access the second signal IN_02, the second input terminal (illustrated as 2B) is connected to the feedback terminal of the NAND logic circuit unit 120, and the output terminal is used to output a second selection signal SW2.

[0064] Since the NOT gate logic circuit unit 120 outputs a high feedback signal ONE_B when receiving the second signal IN_02, when the fourth AND gate logic circuit receives the second signal IN_02, it will also synchronously receive the feedback signal ONE_B, and then output a high second selection signal SW2.

[0065] In this embodiment, by setting the AND gate device U1, the corresponding selection signal (the first selection signal or the second selection signal SW2) can be generated according to the received first signal IN_01 and second signal IN_02. The circuit is simple, with lower cost and easier implementation compared to programming chips.

[0066] Furthermore, in some embodiments, such as Figure 4 shown, the AND gate logic circuit unit 110 may further include a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the output terminal of the second AND gate logic circuit, and the cathode of the first diode D1 is connected to the control terminal of the selection output module 200. The anode of the second diode D2 is connected to the output terminal of the third AND gate logic circuit, and the cathode of the second diode D2 is connected to the control terminal of the selection output module 200; the cathode of the first diode D1 is connected to the cathode of the second diode D2.

[0067] In this embodiment, the output terminal of the second AND gate logic circuit (shown as 1Y in the figure) is connected to the anode of the first diode D1 to transmit the generated first selection signal ONE01 to the first diode D1. The output terminal of the third AND gate logic circuit (shown as 3Y in the figure) is connected to the anode of the second diode D2, and the cathode of the first diode D1 is connected to the cathode of the second diode D2 to transmit the generated first selection signal ONE02 to the second diode D2. The common node where the two diodes are connected is connected to the control terminal of the selection output module 200, so as to output the first selection signal ONE01 to the selection output module 200 through the first diode D1, or output the first selection signal ONE02 to the selection output module 200 through the second diode D2. For ease of understanding, the signals obtained by outputting the first selection signal ONE01 and the first selection signal ONE02 at the common node of the two diodes are both represented as SW1. By setting the first diode D1 and the second diode D2, the first selection signal SW1 output to the selection output module 200 can be made more stable, thereby improving the control reliability of the selection output module 200.

[0068] It can be understood that in actual implementation, a capacitor C3 can also be set between the power supply VCC and the ground according to the actual situation, and those skilled in the art can implement it according to actual needs.

[0069] In one embodiment, such as Figure 5As shown, the NAND logic circuit unit 120 includes a NAND device U2 and a second resistor R13, and the NAND device U2 includes at least one set of NAND logic circuits.

[0070] The first signal input terminal (illustrated as 1B) of the NAND logic circuit (illustrated as 1B) is used to access the second signal IN_02, and the second signal input terminal (illustrated as 1A) of the NAND logic circuit is connected to the output terminal of the first group of AND logic circuits and is used to access the operation signal SWA. The third and fourth signal input terminals of the NAND logic circuit (illustrated as 1C and 1D respectively) are both connected to the power supply VCC through the second resistor R13, and the feedback terminal (illustrated as 1Y) of the NAND logic circuit is connected to the second input terminal of the fourth AND logic circuit, and the feedback terminal is used to output the feedback signal ONE_B.

[0071] In this embodiment, the NAND logic circuit is a four-input NAND gate. In other embodiments, other types of NAND devices can also be selected. When the four-input NAND gate receives both the second signal IN_02 and the operation signal SWA at the same time, it outputs a high feedback signal ONE_B, so that the fourth group of AND logic circuits of the AND device U1 outputs the second selection signal SW2 according to the feedback signal ONE_B. Thus, the operation of the feedback signal ONE_B can be realized through a group of NAND gates, and the circuit structure is simple.

[0072] In one embodiment, as Figure 6 shown, the selection output module 200 includes a first output unit 210 and a second output unit 220.

[0073] The input terminal of the first output unit 210 is used to access the first analog signal MOD1_INT transmitted externally, the control terminal of the first output unit 210 is used to access the first selection signal SW1, and the output terminal of the first output unit 210 is used to output the first analog signal MOD1_OUT.

[0074] The input terminal of the second output unit 220 is used to access the second analog signal MOD2_INT transmitted externally, the control terminal of the second output unit 220 is used to access the second selection signal SW2, and the output terminal of the second output unit 220 is used to output the second analog signal MOD2_OUT.

[0075] In this embodiment, the first output unit 210 is used to access the first analog signal MOD1_INT and output the first analog signal MOD1_OUT when receiving the first selection signal SW1. The second output unit 220 is used to access the second analog signal MOD2_INT and output the second analog signal MOD2_OUT when receiving the second selection signal SW2. Thus, the two analog signals are transmitted and controlled through independent paths, which can reduce the interference between different signals and improve the flexibility of control.

[0076] In actual implementation, the structures of the first output unit 210 and the second output unit 220 can be set according to specific circumstances. In one embodiment, with continued reference to Figure 6 , the first output unit 210 may include a first relay K1, a first switch module 211, and a third diode D1. One end of the contact of the first relay K1 is used to access the first analog signal MOD1_INT, and the other end is used to output the first analog signal MOD1_OUT. One end of the coil of the first relay K1 and the cathode of the third diode D1 are both connected to the power supply VCC, and the other end is connected to the anode of the third diode D1 and the first end of the first switch module 211. The second end of the first switch module 211 is grounded, and the control end of the first switch module 211 is used to access the first selection signal SW1.

[0077] The second output unit 220 includes a second relay K2, a second switch module 221, and a fourth diode D2; one end of the contact of the second relay K2 is used to access the second analog signal MOD2_INT, and the other end is used to output the second analog signal MOD2_OUT. One end of the coil of the second relay K2 and the cathode of the fourth diode D2 are both connected to the power supply VCC, and the other end is connected to the anode of the fourth diode D2 and the first end of the second switch module 221. The second end of the second switch module 221 is grounded, and the control end of the second switch module 221 is used to access the second selection signal SW2.

[0078] In this embodiment, when the first switch module 211 receives the first selection signal SW1, it conducts, causing the coil of the first relay K1 to be powered on and the contact of the first relay K1 to close, thereby outputting the first analog signal MOD1_OUT. When the second switch module 221 receives the second selection signal SW2, it conducts, causing the coil of the second relay K2 to be powered on and the contact of the second relay K2 to close, thereby outputting the second analog signal MOD2_OUT. Among them, the third diode D1 and the fourth diode D2 can provide a discharge path for the possible reverse electromotive force in the two coils respectively when the coils of the first relay K1 and the second relay K2 are powered off, thereby playing a role in protecting the circuit (the first switch tube Q1 in the first switch module 211, the second switch tube Q2 in the second switch module 221).

[0079] By setting the first relay K1 and the second relay K2, the selection signals (SW1 and SW2) and the analog signals (MOD1_INTT, MOD2_INT and their outputs MOD1_OUT, MOD2_OUT) are not directly connected, thereby achieving electrical isolation and improving the circuit safety. Among them, the first relay K1 and the second relay K2 can be selected according to specific circumstances. In some embodiments, the first relay K1 and the second relay K2 can be selected as power relays, and the characteristics of high sensitivity and fast response of the power relays are utilized to achieve precise control.

[0080] In one embodiment, the first switch module 211 includes a first switching transistor Q1, a third resistor R8, a fourth resistor R7, and a first capacitor C17. The first end of the third resistor R8 is used to connect to the first selection signal SW1. The second end of the third resistor R8 is respectively connected to the first end of the fourth resistor R7, the first end of the first capacitor C17, and the control end of the first switching transistor Q1. The second end of the fourth resistor R7, the second end of the first capacitor C17, and the first end of the first switching transistor Q1 are grounded. The second end of the first switching transistor Q1 serves as the first end of the first switch module 211 and is connected to the anode of the third diode D1.

[0081] The second switch module 221 includes a second switching transistor Q2, a fifth resistor R10, a sixth resistor R9, and a second capacitor C1. The first end of the fifth resistor R10 is used to connect to the second selection signal SW2. The second end of the fifth resistor R10 is respectively connected to the first end of the sixth resistor R9, the first end of the second capacitor C1, and the control end of the second switching transistor Q2. The second end of the sixth resistor R9, the second end of the second capacitor C1, and the first end of the second switching transistor Q2 are grounded. The second end of the second switching transistor Q2 serves as the first end of the second switch module 221 and is connected to the anode of the fourth diode D2.

[0082] Among them, the types of the first switching transistor Q1 and the second switching transistor Q2 do not need to be limited, and those skilled in the art can select according to specific circumstances. The first end, the second end of the first switching transistor Q1, the first end, and the second end of the second switching transistor Q2 need to be determined in combination with the specific types of the first switching transistor Q1 and the second switching transistor Q2.

[0083] In this embodiment, when the first selection signal SW1 is high, the first switching transistor Q1 conducts, causing the coil of the first relay K1 to be powered on. When the second selection signal SW2 is high, the second switching transistor Q2 conducts, causing the coil of the second relay K2 to be powered on. Thus, by using the first selection signal SW1 and the second selection signal SW2 to control the conduction states of the first switching transistor Q1 and the second switching transistor Q2 respectively, and further controlling the power-on of the coils of the first relay K1 and the second relay K2, independent and flexible control of the two relays is achieved, enabling the corresponding analog signals to be output or not output individually as needed.

[0084] It should be noted that when the voltage levels of the first control signal and the second control signal corresponding to the first solenoid valve 312 and the second solenoid valve 322 do not match the voltage levels of the signal selection operation module 100 (such as the AND gate device U1 and the NAND gate device U2), the first control signal and the second control signal can be processed through a specific intermediate circuit and then used as the first signal IN_01 and the second signal IN_02 respectively. In actual implementation, the voltage levels of the first control signal and the second control signal may be 24V, and the voltage levels of the AND gate device U1 and the NAND gate device U2 may be 5V. Then, the signal selection circuit needs to design a specific intermediate circuit to identify and process the first control signal and the second control signal.

[0085] In one embodiment, as Figure 7 shown, the signal selection circuit further includes a first signal detection unit 510 and a second signal detection unit 520.

[0086] The output end of the first signal detection unit 510 is connected to the signal input end of the AND logic circuit unit 110, and the input end of the first signal detection unit 510 is used to receive the first control signal 24V_01. When receiving the first control signal 24V_01, the output end of the first signal detection unit 510 outputs the first signal IN_01.

[0087] The output end of the second signal detection unit 520 is connected to the AND logic circuit unit 110 and the NAND logic circuit unit 120 respectively, and the input end of the second signal detection unit 520 is used to receive the second control signal 24V_02. When receiving the second control signal 24V_02, the output end of the second signal detection unit 520 outputs the second signal IN_02.

[0088] In this embodiment, on the one hand, the first signal detection unit 510 and the second signal detection unit 520 can respectively detect the first control signal 24V_01 and the second control signal 24V_02, and output the corresponding first signal IN_01 and second signal IN_02 in a timely manner, so that the subsequent circuit can realize the directional selection and output of analog signals. On the other hand, the first signal detection unit 510 and the second signal detection unit 520 can also convert the first control signal 24V_01 and the second control signal 24V_02, and output the first signal IN_01 and the second signal IN_02 that match the voltage level of the subsequent circuit.

[0089] Thus, through the first signal detection unit 510 and the second signal detection unit 520, the circuit can efficiently process and convert two independent control signals, ensuring that they are received by the subsequent circuit with the correct voltage level and signal type. This design improves the flexibility and reliability of the circuit, thus achieving precise control.

[0090] In one embodiment, the first signal detection unit 510 includes a first optocoupler U3. The input side of the first optocoupler U3 is used to access the first control signal 24V_01, and the output side of the first optocoupler U3 is connected to the signal input terminal of the gate logic circuit unit 110 for outputting the first signal IN_01.

[0091] The second signal detection unit 520 includes a second optocoupler U4. The input side of the second optocoupler U4 is used to access the second control signal 24V_02, and the output side of the second optocoupler U4 is respectively connected to the gate logic circuit unit 110 and the NAND logic circuit unit 120 for outputting the second signal IN_02.

[0092] It can be understood that the first signal detection unit 510 and the second signal detection unit 520 may also include devices that cooperate with the first optocoupler U3 and the second optocoupler U4. Specifically, the first signal detection unit 510 may further include a seventh resistor R1, an eighth resistor R2, a ninth resistor R14, a tenth resistor R5, an eleventh resistor R12, and a first light-emitting diode LED1. The first end of the seventh resistor R1 is used to access the first control signal 24V_01, and the second end of the seventh resistor R1 is connected to the positive electrode (shown as pin 1) of the input side of the first optocoupler U3 through the eighth resistor R2. The negative electrode (shown as pin 3) of the input side of the first optocoupler U3 is grounded after passing through the first light-emitting diode LED1 and the ninth resistor R14 in sequence. The collector of the output side of the first optocoupler U3 is connected to the power supply VCC, and the emitter of the output side of the first optocoupler U3 is respectively connected to the first end of the tenth resistor R5 and the first end of the eleventh resistor R12. The second end of the tenth resistor R5 is grounded, and the second end of the eleventh resistor R12 is used to output the first signal IN_01.

[0093] The second signal detection unit 520 may further include a twelfth resistor R3, a thirteenth resistor R4, a fourteenth resistor R15, a fifteenth resistor R6, a sixteenth resistor R17, and a second light-emitting diode LED2. The first end of the twelfth resistor R3 is used to connect to the second control signal 24V_02, and the second end of the twelfth resistor R3 is connected to the positive electrode (shown as pin 1) of the input side of the second optocoupler U4 through the thirteenth resistor R4. The negative electrode (shown as pin 3) of the input side of the second optocoupler U4 is grounded after passing through the second light-emitting diode LED2 and the fourteenth resistor R15 in sequence. The collector of the output side of the second optocoupler U4 is connected to the power supply VCC, and the emitter of the output side of the second optocoupler U4 is respectively connected to the first end of the fifteenth resistor R6 and the first end of the sixteenth resistor R17. The second end of the fifteenth resistor R6 is grounded, and the second end of the sixteenth resistor R17 is used to output the second signal IN_02.

[0094] Among them, the first light-emitting diode LED1 and the second light-emitting diode LED2 are used for output indication judgment. The first ends of the tenth resistor R5, the eleventh resistor R12, the fifteenth resistor R6, and the sixteenth resistor R17 all have a voltage-limiting function. In some embodiments, the seventh resistor R1 and the eighth resistor R2 can be two resistors or an independent resistor. The twelfth resistor R3 and the thirteenth resistor R4 can be two resistors or an independent resistor.

[0095] When the first optocoupler U3 detects that the first control signal 24V_01 has an output, it can convert the 24V first control signal 24V_01 into a 5V first signal IN_01 and output it. When the second optocoupler U4 detects that the second control signal 24V_02 has an output, it can convert the 24V second control signal 24V_02 into a 5V second signal IN_02 and output it. On the basis of realizing the voltage conversion of the input and output electrical signals, the two optocouplers achieve electrical isolation between the input and output, and can also effectively prevent mutual interference and damage between circuits.

[0096] For better understanding of the above signal selection circuit, the following will be explained in detail with specific embodiments. Please refer to Figures 1-7 , the signal selection circuit provided by the present application includes a signal selection operation module 100, a selection output module 200, a first signal detection unit 510, and a second signal detection unit 520; the signal selection operation module 100 may include a connected gate logic circuit unit 110 and a NAND gate logic circuit unit 120. The gate logic circuit unit 110 can be set with reference to Figures 3-4 for setting, the NAND gate logic circuit unit 120 can be set with reference to Figure 5 for setting, and the selection output module 200 can be set with reference toFigure 6 For the settings, the first signal detection unit 510 and the second signal detection unit 520 can refer to Figure 7 for the settings.

[0097] In this embodiment, there are two 24V control signals (the first control signal 24V_01 and the second control signal 24V_02). When the first control signal 24V_01 has an output, the corresponding first analog signal MOD1_INT is output; when the second control signal 24V_02 has an output, the corresponding second analog signal MOD2_INT is output; when both control signals have outputs, the first analog signal MOD1_INT is selectively output.

[0098] Specifically, when the first control signal 24V_01 or the second control signal 24V_02 has an output, through the corresponding optocoupler (U3 or U4), the output of the 24V control signal can be converted into the output of a 5V signal. When the first control signal 24V_01 is output, the first optocoupler U3 outputs a 5V first signal IN_01, and at the same time, LED1 is lit. When the second control signal 24V_02 is output, the second optocoupler U4 outputs a 5V second signal IN_02, and at the same time, LED2 is lit.

[0099] The AND gate device U1 can be an AND gate logic chip, that is, when both inputs A and B are "1", then Y outputs "1". The NAND gate device U2 can be a NAND gate chip. When the input is all "1", the output is "0", and when there is a "0" in the input, the output is "1".

[0100] When both the first control signal 24V_01 and the second control signal 24V_02 are output, that is, both the first signal IN_01 and the second signal IN_02 are at a high level. Then, pins 12 and 13 of the AND gate device U1 are at a high level. According to the definition of the AND gate chip, pin 11 outputs a high-level SWA signal. Subsequently, it can be obtained that both pins 1 and 2 are at a high level, and the output of pin 3 is a high-level ONE01 signal. Then, the output of the first selection signal SW1 is at a high level. The first relay K1 transmits the first analog voltage MOD1_INT of channel 1.

[0101] At the same time, pins 4 and 5 of the NAND gate chip U2 are default connected to a high level. At this time, the signal ONE_B is at a low level. Substituting it into the AND gate device U1, the second selection signal SW2 is not output at pin 6 of the AND gate device U1. Therefore, the second analog signal MOD2_OUT has no output. In summary, when both control signals are output, through the cooperation of the two operational chips, only the analog quantity of one channel is transmitted.

[0102] When the first control signal 24V_01 is output (i.e., the first signal IN_01 is high and the second signal IN_02 is low), and the signal ONE output from pin 10 of AND gate device U1 is high, then, combined with its pin 9, it is easy to conclude that signal ONE02 is also high. This turns on second diode D2, outputting the first selection signal SW1 and, in turn, the first analog signal MOD1_OUT. Since signal IN_02 is low, no other paths can output signals. Therefore, when only the first control signal 24V_01 of the first path is output, only the first control signal 24V_01 is output.

[0103] When the second control signal 24V_02 is output (i.e., the first signal IN_01 is low and the second signal IN_02 is high), it is easy to conclude that pins 4 and 5 of AND gate device U1 are high. This outputs the second select signal SW2, which in turn controls the output of the second analog signal MOD2_OUT. Since the first signal IN_01 is low, both signals ONE01 and ONE02 can only be low. Therefore, this situation only satisfies the output of the channel containing the second analog signal.

[0104] In summary, this embodiment achieves directional selection of related analog signals through the cooperation of two logic chips. This eliminates the need for a programming chip in the two-way signal directional selection circuit, effectively reducing circuit costs and eliminating the programming step of the programming chip, greatly simplifying the design process. Furthermore, since no programming chip is required, a series of connection components that are compatible with the programming chip, such as analog acquisition ports and input and output ports, are further eliminated, thereby significantly simplifying the circuit structure and improving the circuit's simplicity.

[0105] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A signal selection circuit, characterized in that, Comprising: A signal selection and operation module, including an AND logic circuit unit and a NAND logic circuit unit. The signal feedback terminal of the AND logic circuit unit is connected to the signal feedback terminal of the NAND logic circuit unit. The signal output terminal of the AND logic circuit unit is connected to the control terminal of the selection output module. The signal input terminal of the AND logic circuit unit is used to access a first signal or a second signal. The AND logic circuit unit is configured to output a first selection signal when receiving the first signal, or output the first selection signal when receiving both the first signal and the second signal. The signal input terminal of the NAND logic circuit unit is used to access the second signal. The NAND logic circuit unit is configured to output a feedback signal to the AND logic circuit unit when receiving the second signal, so that the AND logic circuit unit outputs a second selection signal according to the second signal and the feedback signal. The selection output module. The first input terminal of the selection output module is used to access a first analog signal transmitted externally, and the second input terminal of the selection output module is used to access a second analog signal transmitted externally. The control terminal of the selection output module is connected to the output terminal of the AND logic circuit unit. The selection output module is configured to output the first analog signal when the control terminal receives the first selection signal, and output the second analog signal when the control terminal receives the second selection signal.

2. The signal selection circuit according to claim 1, wherein The AND logic circuit unit includes an AND device and a first resistor. The AND device includes at least a first AND logic circuit, a second AND logic circuit, a third AND logic circuit, and a fourth AND logic circuit. Two input terminals of the first AND logic circuit are respectively used to access the first signal and the second signal, and the output terminal is used to output an operation signal. The first input terminal of the second AND logic circuit is used to access the first signal, the second input terminal is connected to the output terminal of the first AND logic circuit, and the output terminal of the second AND logic circuit is connected to the control terminal of the selection output module, and is configured to output a first selection signal. The first input terminal of the third AND logic circuit is used to access the first signal, the second input terminal is connected to the power supply through the first resistor, and the output terminal is connected to the control terminal of the selection output module, and is configured to output a first selection signal. The first input terminal of the fourth AND logic circuit is used to access the second signal, the second input terminal is connected to the feedback terminal of the NAND logic circuit unit, and the output terminal is used to output a second selection signal.

3. The signal selection circuit according to claim 2, wherein The AND logic circuit unit further includes a first diode and a second diode. The anode of the first diode is connected to the output terminal of the second AND logic circuit, and the cathode of the first diode is connected to the control terminal of the selection output module. The anode of the second diode is connected to the output terminal of the third AND logic circuit, and the cathode of the second diode is connected to the control terminal of the selection output module. The cathode of the first diode is connected to the cathode of the second diode.

4. The signal selection circuit according to claim 2, wherein The NAND logic circuit unit includes a NAND device and a second resistor, and the NAND device includes at least one set of NAND logic circuits; The first signal input terminal of the NAND logic circuit is used to access the second signal, the second signal input terminal of the NAND logic circuit is connected to the output terminal of the first set of AND logic circuits, the third signal input terminal and the fourth input terminal of the NAND logic circuit are both connected to the power supply through the second resistor, the feedback terminal of the NAND logic circuit is connected to the second input terminal of the fourth AND logic circuit, and the feedback terminal is used to output a feedback signal.

5. The signal selection circuit according to claim 1, characterized in that, The selection output module includes a first output unit and a second output unit; The input terminal of the first output unit is used to access the first analog signal transmitted externally, the control terminal of the first output unit is used to access the first selection signal, and the output terminal of the first output unit is used to output the first analog signal; The input terminal of the second output unit is used to access the second analog signal transmitted externally, the control terminal of the second output unit is used to access the second selection signal, and the output terminal of the second output unit is used to output the second analog signal.

6. The signal selection circuit according to claim 5, wherein The first output unit includes a first relay, a first switch module, and a third diode; one end of the contact of the first relay is used to access the first analog signal, and the other end is used to output the first analog signal; one end of the coil of the first relay and the cathode of the third diode are both connected to the power supply, and the other end is connected to the anode of the third diode and the first end of the first switch module, the second end of the first switch module is grounded, and the control terminal of the first switch module is used to access the first selection signal; The second output unit includes a second relay, a second switch module, and a fourth diode; one end of the contact of the second relay is used to access the second analog signal, and the other end is used to output the second analog signal; one end of the coil of the second relay and the cathode of the fourth diode are both connected to the power supply, and the other end is connected to the anode of the fourth diode and the first end of the second switch module, the second end of the second switch module is grounded, and the control terminal of the second switch module is used to access the second selection signal.

7. The signal selection circuit according to claim 6, wherein The first switch module includes a first switch tube, a third resistor, a fourth resistor, and a first capacitor; the first end of the third resistor is used to access the first selection signal, the second end of the third resistor is connected to the first end of the fourth resistor, the first end of the first capacitor, and the control terminal of the first switch tube, the second end of the fourth resistor, the second end of the first capacitor, and the first end of the first switch tube are grounded; the second end of the first switch tube serves as the first end of the first switch module and is connected to the anode of the third diode; The second switch module includes a second switching tube, a fifth resistor, a sixth resistor, and a second capacitor; a first end of the fifth resistor is configured to receive the second selection signal, a second end of the fifth resistor is connected to a first end of the sixth resistor, a first end of the second capacitor, and a control end of the second switching tube, a second end of the sixth resistor, a second end of the second capacitor, and a first end of the second switching tube are grounded; a second end of the second switching tube serves as a first end of the second switch module and is connected to an anode of the fourth diode.

8. The signal selection circuit according to any one of claims 1-7, characterized in that It further includes a first signal detection unit and a second signal detection unit. An output end of the first signal detection unit is connected to a signal input end of the AND logic circuit unit. An input end of the first signal detection unit is configured to receive a first control signal. When receiving the first control signal, the output end of the first signal detection unit outputs the first signal. An output end of the second signal detection unit is respectively connected to the AND logic circuit unit and the NAND logic circuit unit. An input end of the second signal detection unit is configured to receive a second control signal. When receiving the second control signal, the output end of the second signal detection unit outputs the second signal.

9. The signal selection circuit according to claim 8, wherein The first signal detection unit includes a first optocoupler. An input side of the first optocoupler is configured to receive the first control signal, and an output side of the first optocoupler is connected to the signal input end of the AND logic circuit unit for outputting the first signal. The second signal detection unit includes a second optocoupler. An input side of the second optocoupler is configured to receive the second control signal, and an output side of the second optocoupler is respectively connected to the AND logic circuit unit and the NAND logic circuit unit for outputting the second signal.

10. A fan adsorption system, characterized in that, It includes a first adsorption platform, a second adsorption platform, a first vacuum pressure detection module, a second vacuum pressure detection module, and the signal selection circuit according to any one of claims 1-9; the first adsorption platform includes a first fluid channel and a first solenoid valve for controlling the first fluid channel, and the second adsorption platform includes a second fluid channel and a second solenoid valve for controlling the second fluid channel. The first vacuum pressure detection device is configured to detect the air pressure in the first fluid channel and output the first analog signal; the second vacuum pressure detection device is configured to detect the air pressure in the second fluid channel and output the second analog signal. The first signal is generated based on the control signal of the first solenoid valve, and the second signal is generated based on the control signal of the second solenoid valve.

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