Testing device for providing load transient jump

Abstract

The utility model provides a testing device for providing load transient jump, which comprises a heat dissipation module for dissipating heat of an MOS (Metal Oxide Semiconductor) tube selection module, a positive and negative voltage jump module and a variable resistance module; the MOS tube selection module selects a working MOS tube from the first NMOS tube and the first PMOS tube to be connected with the output end of the chip to be tested, the grid electrode of the working MOS tube is connected with the signal generator, and the output current is the load jump current required by the chip to be tested; the variable resistance module is removably connected between the working MOS tube and the output end of the chip to be tested; and the positive and negative voltage jump module comprises an operational amplifier connected with the signal generator through an isolation transformer, and a second NMOS tube of which the grid electrode is connected with the output end of the operational amplifier. According to the utility model, the jump requirements of most loads to be tested in the market are met, the problem that rapid jump of positive and negative voltages is difficult to complete in a laboratory at present is solved, heat can be dissipated, and more accurate jump current can be provided.

Description

Technical Field

[0001] The utility model is widely applied to the verification scheme of switching power supply products, and particularly relates to a test device for providing load transient jumps. Background Art

[0002] With the progress and development of technology, electronic products are increasingly indispensable in our daily life. At the same time, electronic products bring us a lot of convenience and make our life change rapidly. There are consumers of electronic products, and naturally there are designers and producers. Almost all electronic products will use DCDC power supply chips.

[0003] A designed chip cannot be directly put into use and needs to be tested to meet the design specifications before subsequent mass production. In DCDC power supply testing, load transient testing is a very important link. By using load transient testing, the stability and rapidity of the tested power supply can be quickly evaluated. A good chip must have a stable and rapid response speed to load changes. Therefore, during chip selection, the performance of load transient testing is also an important reference for evaluating the dynamic performance of the chip.

[0004] In load jump testing, the loop response time of the chip can be most intuitively seen, that is, the Fc (crossing frequency) and Phase Margin (phase margin) that we often mention. These two indicators directly determine whether the chip is stable. Usually, we design Fc at 1 / 4 - 1 / 10 of the chip switching frequency and Phase at >45°.

[0005] Load transient testing can show the change trend of the output ripple under sudden changes in load current, and thus judge whether the phase margin is sufficient. If there is obvious jitter in the waveform, we can judge that this system is unstable. Content of the Utility Model

[0006] The utility model aims to provide a test device for providing load transient jumps, and the device covers the load jump modes commonly encountered in the testing process of switching power supply products, and at the same time provides jump currents under most load jump modes.

[0007] In order to achieve the above object, a test device for providing load transient jumps of the utility model includes a heat dissipation module, a MOS tube selection module, a positive and negative voltage jump module, and a variable resistor module;

[0008] The heat dissipation module is configured to dissipate heat from the MOS transistor selection module, the positive and negative voltage jump module, and the variable resistor module; the MOS transistor selection module is configured to select one working MOS transistor from the first NMOS transistor and the first PMOS transistor to connect to the output terminal of the chip under test, so as to select the first NMOS transistor for positive voltage jump or the first PMOS transistor for negative voltage jump. The gate of the working MOS transistor is connected to a signal generator, and the output current is the load jump current required by the chip under test; the variable resistor module is removably connected between the working MOS transistor and the output terminal of the chip under test, and its resistance value is adjusted to improve the accuracy of the output current of the working MOS transistor; the positive and negative voltage jump module includes an operational amplifier connected to the signal generator through a 1:1 isolation transformer, and a second NMOS transistor whose gate is connected to the output terminal of the operational amplifier. The 1:1 isolation transformer is used to isolate the reference ground of the signal generator from the reference ground of the chip under test. The operational amplifier is used to provide a gate voltage for driving the second NMOS transistor to conduct and turn off alternately. When the second NMOS transistor is fully conducting, an output current consistent with the output waveform of the signal generator is generated as the load jump current required by the chip under test.

[0009] The heat dissipation module includes a current limiting chip and a cooling fan powered by the current limiting chip, and the current limiting chip is powered by an external DC power supply.

[0010] The MOS transistor selection module further includes a drain selection slide switch and a source selection slide switch for switching the working MOS transistor between the first NMOS transistor and the first PMOS transistor; the sources of the first NMOS transistor and the first PMOS transistor are grounded, and the drain selection slide switch is connected to the output terminal of the chip under test.

[0011] The MOS transistor selection module further includes a mode selection slide switch with its Gmode moving contact connected to the static contact of the drain selection slide switch and its Rmode moving contact connected to the variable resistor module. Among them, the static contact of the mode selection slide switch is connected to the output terminal of the chip under test, so that the drain selection slide switch can be connected to the output terminal of the chip under test.

[0012] The MOS transistor selection module further includes a first gate discharge module connected between the signal generator and the gate of the first NMOS transistor and a second gate discharge module connected between the signal generator and the gate of the first PMOS transistor; both the first gate discharge module and the second gate discharge module include a gate resistor and a pull-down resistor. The gate resistor is connected between the signal generator and the gate of the working MOS transistor, and the pull-down resistor is connected between the signal generator and the ground.

[0013] The pull-down resistor is 1KΩ, and the gate resistor is 50Ω.

[0014] When the variable resistance module is moved into the circuit of the test device, it includes a first load resistor connected between the output terminal of the chip under test and the drain of the working MOS transistor, and a second load resistor connected between the output terminal of the chip under test and the source of the working MOS transistor. The resistance values of the first load resistor and the second load resistor are adjustable.

[0015] The variable resistance module includes a plurality of resistors connected in series as the first load resistor and a plurality of resistors connected in series as the second load resistor. There is a socket for a jumper cap above each resistor. By changing the position of the jumper cap, the resistance values of the first load resistor and the second load resistor can be changed. The adjustable range of the resistance value of the first load resistor is 1 - 99 Ω, and the adjustable range of the resistance value of the second load resistor is 100 - 9.9 KΩ.

[0016] The output terminal of the chip under test is connected to the drain of the second NMOS transistor. The ground terminal of the chip under test serves as the reference ground of the chip under test and is connected to the drain of the second NMOS transistor through a third capacitor. The source of the second NMOS transistor is connected to the reference ground of the chip under test through a 1 Ω detection resistor.

[0017] A 10 KΩ fourth resistor is connected between the output terminal and the output ground of the 1:1 isolation transformer to form a damping effect to suppress oscillation; when the operational amplifier is working normally, its output voltage is pulled to its power supply voltage.

[0018] The utility model covers most of the load jump requirements of the chips under test on the market, solves the problem that it is difficult to complete the rapid jump of positive and negative voltages in the current laboratory, can dissipate heat, and provides a more accurate jump current. Description of the Drawings

[0019] Figure 1 is the overall circuit schematic diagram of the test device for providing load transient jump of the utility model.

[0020] Figure 2 is the schematic diagram of the variable resistance module of the test device for providing load transient jump of the utility model.

[0021] Figure 3 is the measured waveform diagram of the positive and negative voltage load transient jump provided by the test device for providing load transient jump of the utility model. Among them, Pulse is the waveform diagram of the pulse signal provided by the signal generator, MOS - G is the waveform diagram of the gate G of the working MOS transistor, and ILOAD is the load jump current required by the chip under test. Detailed Embodiments

[0022] The following further describes the present utility model in conjunction with specific embodiments. It should be understood that the following embodiments are only used to illustrate the present utility model and not to limit the scope of the present utility model.

[0023] The test device for providing load transient jump of the present utility model is applicable to three test methods of providing load transient jump with positive pressure output, load transient jump with negative pressure output, and load transient jump with positive and negative pressure output, so as to basically meet the load jump required by most switching power supply ICs.

[0024] As Figure 1 shown, the test device for providing load transient jump of the present utility model mainly includes a heat dissipation module 10, a MOS transistor selection module 20, a positive and negative voltage jump module 30, and a variable resistor module 40.

[0025] The heat dissipation module 10 is arranged to dissipate heat from the MOS transistor selection module 20, the positive and negative voltage jump module 30, and the variable resistor module 40. The heat dissipation module 10 includes a current limiting chip U3 and a cooling fan 11 powered by the current limiting chip U3.

[0026] In this embodiment, the model of the current limiting chip U3 is OCP9227, which includes three input voltage pins VIN, three ground terminals GND, three output voltage pins OUT, a current limiting protection trigger pin OCFLAGB, a current limit pin ISET, and an enable pin ON. The output voltage pin OUT is used to provide a current-limited supply current. The enable pin ON uses a high level to cooperate with VIN to achieve the normal operation of OCP9227. The current limit pin ISET controls the maximum current limit through an external resistor. After the current limiting protection trigger pin OCFLAGB is connected to a pull-up resistor to "VIN" to trigger current limiting, the level of this pin will be pulled low to 0V. This pin is generally used as a feedback pin and has no actual function in this device. Among them, the three input voltage pins VIN and the enable pin ON are directly connected to the DC power supply VIN_2 and grounded through the fourth capacitor C4. The current limiting protection trigger pin OCFLAGB is connected to the input voltage VIN_2 through the fourth six-resistor R46 (with a resistance value of 10 kΩ). The three ground terminals GND are directly grounded. The current limit pin ISET is grounded through the fourth five-resistor R45 (i.e., the current limiting resistor). The three output voltage pins OUT are grounded through the fifth capacitor C5.

[0027] The current-limiting chip U3 provides power supply and current-limiting protection through its output voltage pin. The current-limiting chip U3 requires an external DC power supply VIN_2 to supply power to the current-limiting chip U3. The input of the current-limiting chip U3 is 5V input, and the output of the output voltage pin is 5V. The output voltage pin of the current-limiting chip is connected to the cooling fan, so as to provide power supply and current-limiting protection to the cooling fan 11 (fan parameters: 5V / 200mA) through the current-limiting chip. The cooling fan is set to dissipate heat from the continuously-conducting MOS transistors and heat sinks, and resistors in the MOS transistor selection module 20, the positive and negative voltage jump module 30, and the variable resistor module 40.

[0028] Thus, the maximum input current can be limited by changing the current-limiting resistor to prevent the cooling fan 11 from being damaged due to excessive input current. Since the output of the current-limiting chip U3 only supplies power to the fan, the working scenario of the fan is relatively single and the current is relatively constant, so the current-limiting chip U3 normally works at the default current-limiting value (1A is sufficient, that is, the fourth and fifth resistors R45 = 1KΩ).

[0029] The MOS transistor selection module 20 is the core of this utility model. The MOS transistor selection module 20 is set to select one working MOS transistor from the first NMOS transistor NM1 and the first PMOS transistor PM1 to be connected to the output end of the chip under test, so as to select the first NMOS transistor NM1 as the working MOS transistor for positive voltage jump or the first PMOS transistor PM1 as the working MOS transistor for negative voltage jump.

[0030] The gate of the working MOS transistor is connected to the signal generator and the output current is the load jump current required by the chip under test. The MOS transistor selection module 20 includes a signal generator connected to the gates of the first NMOS transistor NM1 and the first PMOS transistor PM1, so as to provide the required pulse signal to the gate of the working MOS transistor. The high and low levels of the pulse signal of the signal generator are adjustable to adjust the conduction degree of the working MOS through the gate voltage, so that the working MOS transistor works in the amplification region when it is conducting.

[0031] The MOS transistor selection module 20 further includes a first gate discharge module connected between the signal generator and the gate of the first NMOS transistor NM1 and a second gate discharge module connected between the signal generator and the gate of the first PMOS transistor PM1.

[0032] The MOS transistor selection module 20 includes a first NMOS transistor NM1 for positive voltage transition, a first PMOS transistor PM1 for negative voltage transition, a drain selection sliding switch Drain Select and a source selection sliding switch Source Select for switching the working MOS transistor between the first NMOS transistor NM1 and the first PMOS transistor PM1, a mode selection sliding switch ModeSelect with its Gmode moving contact connected to the static contact of the drain selection sliding switch Drain Select and its Rmode moving contact connected to the variable resistance module 20, a chip output terminal pin VOUT_1 connected to the static contact of the mode selection sliding switch ModeSelect and the output terminal of the chip to be tested, a first Gate terminal N-Gate for connecting the gate of the first NMOS transistor NM1 and the signal generator, a second Gate terminal P-Gate for connecting the gate of the first PMOS transistor PM1 and the signal generator, a first gate discharge module connected between the gate of the first NMOS transistor NM1 and the first Gate terminal N-Gate, a second gate discharge module connected between the gate of the first PMOS transistor PM1 and the second Gate terminal P-Gate, a first source terminal V-Source-1 connected to the source of the first NMOS transistor NM1, and a second source terminal V-Source-2 connected to the source of the first PMOS transistor PM1.

[0033] Among them, the first gate discharge module includes a first gate voltage pin V-Gate-1 connected to the signal generator through the first Gate terminal N-Gate, a first resistor R1 as a gate resistor, and a second resistor R2 as a pull-down resistor. The other end of the first resistor R1 is connected to the gate of the first NMOS transistor NM1, and the other end of the second resistor R2 is grounded at GND_N. In this embodiment, the first resistor R1 is 50Ω and the second resistor R2 is 1kΩ. Similarly, the second gate discharge module includes a second gate voltage pin V-Gate-2 connected to the second Gate terminal P-Gate, a fourth resistor R4 as a gate resistor, and a fifth resistor R5 as a pull-down resistor. The other end of the fourth resistor R4 is connected to the gate of the first PMOS transistor PM1, and the other end of the fifth resistor R5 is grounded at GND_P. In this embodiment, the first resistor R1 is 50Ω and the second resistor R2 is 1kΩ.

[0034] The first source terminal V-Source-1 is grounded at GND_N through a 1Ω third resistor R3, and the second source terminal V-Source-2 is grounded at GND_P through a 1Ω sixth resistor R6.

[0035] The MOS transistor selection module 20 further includes a "GND-AVDD" pin, a "GND-AVEE" pin, and a MOS transistor heat sink.

[0036] Among them, the first moving contact ND and the second moving contact PD of the drain selection slide switch Drain Select are respectively connected to the drains of the first NMOS transistor NM1 and the first PMOS transistor PM1, and the first moving contact NS and the second moving contact PS of the source selection slide switch Source Select are respectively connected to the sources of the first NMOS transistor NM1 and the first PMOS transistor PM1. Therefore, when both the drain selection slide switch Drain Select and the source selection slide switch Source Select select the first moving contacts ND and NS representing the N gear (N represents the first NMOS, that is, positive voltage jump), the drain and source of the first NMOS can be connected. When both select the second moving contacts representing the P gear, the source and drain of the first PMOS transistor PM1 can be connected.

[0037] When the output voltage of the chip under test is a positive voltage output, its ground terminal GND is connected to the "GND-AVDD" pin. When the output voltage of the chip under test is a positive voltage output, its ground terminal GND is connected to the "GND-AVEE" pin. Figure 1 In the figure, the dashed box where GND-N is located is the "GND-AVDD" pin, and the dashed box where GND-P is located is the "GND-AVEE" pin.

[0038] The "GND-AVDD" pin is connected to GND-N, which is actually a common ground (ground means the lowest reference level). Specifically, GND-N is the ground for positive voltage jump. The "GND-AVEE" pin is connected to GND-P, and GND-P is the ground for negative voltage jump. Since the first NMOS transistor NM1 is responsible for positive voltage jump and the first PMOS transistor PM1 is responsible for negative voltage jump, the grounds of the two working MOS transistors need to be isolated. Otherwise, a current loop will be formed in the PMOS transistor during positive voltage jump, which will cause problems.

[0039] The variable resistance module 20 is enabled or disabled to be connected to the MOS transistor selection module through the mode selection slide switch ModeSelect. The variable resistance module 20 is used to provide a relatively accurate output current. Among them, the static contact of the mode selection slide switch is connected to the output terminal of the chip under test, so that the drain selection slide switch can be connected to the output terminal of the chip under test.

[0040] When the moving contact of the mode selection slide switch ModeSelect selects the Gmode, it means that the variable resistor module mode is not enabled. The output terminal of the chip under test is short-circuited to the drain of the working MOS transistor via the chip output terminal pin VOUT_1 and the drain selection slide switch Drain Select. At this time, the source-drain current provided by the saturation region of the working MOS transistor is used to achieve current variation. At this time, the variable resistor module 20 is disconnected and removed from the circuit and not connected to the MOS transistor selection module.

[0041] When the moving contact of the mode selection slide switch ModeSelect selects the Rmode, it means that the variable resistor module mode is enabled. The output terminal of the chip under test is connected to the high voltage side VR of the variable resistor module 20 via the chip output terminal pin VOUT_1, and one end of it is short-circuited to the drain of the working MOS transistor through the first load resistor RH (corresponding to Figure 1 R7 - R24 in it, with a resistance value of 1 - 99 Ω) and the drain selection slide switch Drain Select. The other end of the output terminal of the chip under test is short-circuited to the source of the working MOS transistor through the second load resistor RL (corresponding to Figure 1 R25 - R42 in it, with a resistance value of 100 - 9.9 KΩ) and the source selection slide switch Source Select.

[0042] The mode of the mode selection slide switch ModeSelect (that is, not enabling the variable resistor module mode and enabling the variable resistor module mode) can be manually selected according to the user's requirements for current accuracy.

[0043] It should be noted that when the variable resistor module is enabled, the pins on the right side of the drain selection slide switch Drain Select need to be short-circuited so that the variable resistor module 20 forms a path with both the drain and source of the MOS transistor. When the variable resistor module is not enabled, the pins on the right side of the slide switch Drain Select should be in an open state to prevent current from flowing from the drain of the working MOS transistor through the variable resistor module 20 to the source of the working MOS transistor and forming a natural conduction path with the body diode of the working MOS transistor.

[0044] According to the output characteristics of the MOS transistor, the MOS transistor has three working regions, namely the cut-off region, the variable resistance region, and the amplification region. The present invention is based on when the MOS transistor works in the amplification region, at this time the MOS transistor is similar to a VCCS (voltage-controlled current source), VDS = (IC Out -IC Gnd )(IC Out is the output voltage of the chip under test, IC Gndis the ground voltage of the chip to be tested. The output voltage of the vast majority of the chips IC to be tested is above 1V, which can ensure that the working MOS transistor is in the amplification region. The present invention changes the gate voltage of the working MOS by connecting the signal generator to the V-Gate pin to achieve the change of the MOS output current (in the amplification region, if the channel modulation effect is ignored, the output current at this time is completely controlled by the gate voltage, that is, VCCS).

[0045] Conditions for the MOS transistor to work in the amplification region: when the gate-source voltage VGS > VGS(th) and VDS >= VGS - VGS(th).

[0046] VGS: Gate-source voltage

[0047] VGS(th): MOS turn-on voltage

[0048] VDS: MOS drain-source voltage

[0049] When selecting the first NMOS transistor NM1 as the working MOS transistor to achieve the load transient jump of the positive voltage output, the specific setting method is as follows:

[0050] Through the MOS transistor selection module 20, the two sliding switches of the drain selection sliding switch Drain Select and the source selection sliding switch Source Select are respectively turned to their first moving contacts ND and NS (N represents selecting the first NMOS transistor NM1, and the D and S after the letter are the drain and source of the first NMOS transistor NM1). Connect the output terminal of the chip to be tested to the chip output terminal pin VOUT_1 of the test device of the present invention, and connect the ground of the chip terminal to the "GND-AVDD" pin.

[0051] The signal generator is connected to the first Gate terminal N-Gate of the test device of the present invention through a signal line. The settings of the signal generator are as follows: select the pulse mode, small duty cycle, and at the same time monitor the first gate voltage pin V-Gate-1 with an oscilloscope, measure the source current with a current probe or measure the voltage across the ground resistance at the source with a voltage range to monitor the real-time output current of the first NMOS transistor NM1 (that is, the load jump current required by the chip to be tested). Adjust the gate-source voltage VGS of the first NMOS transistor NM1 by changing the high and low levels of the signal generator to achieve the load jump current required by the chip to be tested. Specifically, utilize the working characteristics of the working MOS transistor in the amplification region: VGS is proportional to the output current, to obtain the load jump current required by the chip to be tested.

[0052] The first source terminal V-Source-1 of the first NMOS transistor NM1 is connected to the 1Ω third resistor R3 to the ground GND_N. Note that for the 1Ω resistor, a large package (1206 is sufficient) should be selected to withstand the current flowing through the MOS, so as to complete the 1:1 conversion of current and voltage. When the current probe is in short supply, the voltage range (measuring the voltage of the first source terminal V-Source-1) can be used to monitor the current proportionally.

[0053] When selecting the first NMOS transistor NM1 as the working MOS transistor to achieve the load transient jump of the positive voltage output, the specific setting method is similar to that of the load transient jump of the positive voltage output. The difference lies in:

[0054] One: The drain select slide switch and the source select slide switch are toggled to their second moving contacts PD and PS (P is the first PMOS transistor PM1, and D / S is the drain / source electrode);

[0055] Two, due to the inherent characteristics of the first PMOS transistor PM1, it needs to be turned on by a low level (VGS < VGS (TH) ). Therefore, attention should be paid to the use of the signal generator. The signal generator needs to be changed to output a large duty cycle (a larger proportion of the high level) to ensure that the conduction time will not be too long, preventing the MOS from overheating and thus affecting the output current and causing temperature drift.

[0056] The second source terminal V-Source-2 of the first PMOS transistor PM1 is connected to the 1Ω third resistor R3 to the ground GND_N to complete the 1:1 conversion of current and voltage. When the current probe is in short supply, the voltage range (measuring the voltage of the first source terminal V-Source-1) can be used to monitor the current proportionally.

[0057] The first resistor R1 and the fourth resistor R4 mentioned above are gate resistors, and the second resistor R2 and the fifth resistor R5 are pull-down resistors.

[0058] The functions of the gate resistor are as follows: ① When the MOSFET is turned on, there will be current to charge the gate-source capacitor. Therefore, within a short period of time, a large amount of charge may accumulate. The gate resistor is used to ensure that this transient current is not too high for the chip (or other connected things); ② When the gate is turned off, when the D-S pole of the MOS transistor changes from the conducting state to the cut-off state, the drain-source voltage VDS will increase rapidly. If it is too large, it will break down the device. Therefore, a gate resistor is needed to allow the gate capacitor to discharge slowly so as not to break down the device. However, when the gate resistor used is too large, the opening / closing speed of the MOSFET will be slower, resulting in unnecessary losses.

[0059] The gate resistance value can be calculated according to Ohm's law:

[0060] I = V / R,

[0061] where I is the current flowing into the gate of the working MOS transistor; V is the output voltage of the signal generator; and R is the gate resistance.

[0062] For example, when the output pin of the signal generator has a voltage of 5V and the gate resistance is 1000 Ω to provide a maximum current of 5 mA: I = 5V / 1000 Ω.

[0063] Function and selection of the pull-down resistor:

[0064] Because of the manufacturing process, MOS transistors will form parasitic capacitors. Taking a PMOS transistor as an example, when the signal generator provides a pulse signal to the Gate terminal, it will first charge the parasitic capacitor C gd This involves the Miller plateau. When the signal generator is turned off, the MOS transistor should be in the off state at this time. However, in fact, the parasitic capacitor C gd has been charged during normal operation. Since the voltage of the capacitor cannot change suddenly, although the signal generator no longer provides a low level to the Gate terminal of the MOS transistor, the Gate is still in the low level state that can turn on the MOS transistor at this time. And because there is no good discharge path, this voltage will be maintained for a long time. Therefore, a resistor needs to be connected from the Gate terminal to GND to provide a discharge path for the capacitor.

[0065] The resistance value of the pull-down resistor is generally in the order of kiloohms.

[0066] The variable resistor module 20 is removably connected between the working MOS transistor and the output terminal of the chip under test, and is used to select the corresponding resistance value according to the actual output voltage of the chip under test and the load jump current required by the chip under test, so as to improve the accuracy of the output current of the working MOS transistor by adjusting the resistance value.

[0067] Please refer to Figure 1 , the variable resistor module 20 includes a high-voltage side VR of the variable resistor module 20 connected to the Rmode moving contact of the mode selection slide switch ModeSelect, a seventh resistor R7 - a twenty-fourth resistor R24 connected in series with the high-voltage side VR and serving as a first load resistor RH, a twenty-fifth resistor R25 - a forty-second resistor R42 connected in series with the high-voltage side VR and serving as a second load resistor RL, a jumper cap for shorting the resistors R7 - R45 to adjust the resistance values of the first load resistor RH and the second load resistor RL, a first pin for shorting the low-voltage side of the first load resistor RH to the stationary contact of the drain selection slide switch Drain Select, and a second pin for shorting the low-voltage side of the second load resistor RL to the stationary contact of the source selection slide switch Drain Select.

[0068] Therefore, when the variable resistance module 20 is moved into the circuit of the test device, it includes a first load resistor RH connected between the output terminal of the chip under test and the drain of the working MOS transistor, and a second load resistor RL connected between the output terminal of the chip under test and the source of the working MOS transistor. The resistance values of the first load resistor RH and the second load resistor RL are adjustable.

[0069] Above each of the resistors R7 - R45, there is a socket for a jumper cap. By changing the position of the jumper cap, different resistance values of the first load resistor RH and the second load resistor RL can be freely combined. The adjustable range of the resistance value of the first load resistor RH is 1 - 99 Ω, and the adjustable range of the resistance value of the second load resistor RL is 100 - 9.9 KΩ.

[0070] As Figure 2 shown, when the variable resistance module 20 is enabled, on the one hand, the output terminal of the chip under test is connected to the first load resistor RH to the drain of the working MOS transistor and then via the source of the working MOS transistor to GND. On the other hand, it is connected to the second load resistor RL to the source of the working MOS transistor to GND. Therefore, when the working MOS transistor is turned on, the chip under test obtains the current value after the load jump current jumps. The current value after the load jump current jumps is equal to the current flowing from the output terminal of the chip under test through the working MOS transistor plus the current directly flowing through the second load resistor RL to GND. When the working MOS transistor is turned off, the chip under test obtains the current value before the load jump current jumps (i.e., the small current before the jump). The current value before the load jump current jumps is equal to the current directly flowing from the output terminal of the chip under test through the second load resistor RL to GND.

[0071] From the working principle, we know that when the working MOS transistor is turned on, at this time, it corresponds to the current value after the load jump current jumps, which is generally relatively large (the load jump range of general products: 50 mA - 1 A). In the device, the resistance value of the corresponding first load resistor RH (corresponding to the seventh resistor R7 - the twenty-fourth resistor R24) is 1 - 99 Ω. When the working MOS transistor is turned off, at this time, it corresponds to the current value before the load jump current jumps, and its current value is generally 0 - 10 mA. Therefore, the resistance value of the corresponding second load resistor RL (corresponding to the twenty-fifth resistor R25 - the forty-second resistor R42) is relatively large, which is 100 - 9.9 KΩ. It can also be selected to be disconnected to make the resistance value infinite to achieve a jump of 0 mA.

[0072] Thus, by changing the resistance values of the first load resistor RH and the second load resistor RL, the current values before and after the load jump current jumps can be precisely adjusted.

[0073] During normal operation, the RH resistor controls the magnitude of the high current output. The specific resistance value can be calculated using the formula R = U / I based on the output voltage of the load and the required load current. Generally, the resistance value of the RL resistor is relatively large to provide a low current approximately equal to zero. When different low currents are required, the resistance value of this resistor can be changed to achieve it.

[0074] The positive and negative voltage jump module 30 includes an operational amplifier U2 connected to the signal generator through a 1:1 isolation transformer D1, and a second NMOS transistor NM2 whose gate is connected to the output terminal of the operational amplifier U2. The 1:1 isolation transformer D1 is used to isolate the reference ground GND_A of the signal generator from the reference ground GND_B of the chip under test. The operational amplifier U2 is used to provide the gate voltage for driving the second NMOS transistor NM2 to alternately conduct and turn off. When the second NMOS transistor NM2 is fully conducting, an output current consistent with the output waveform of the signal generator is generated through the resistor at its source as the load jump current required by the chip under test.

[0075] Among them, the positive and negative voltage jump module 30 is applicable to the chip under test with positive and negative voltage outputs, and can perform rapid load jumps for the chip under test with positive and negative voltage outputs.

[0076] The positive and negative voltage jump module 30 further includes a MOS transistor heat sink for the second NMOS transistor NM2, a positive voltage test pin AVDD for connecting to the positive voltage output terminal and the negative voltage output terminal of the chip under test, a ground test pin AVEE, amplifier power pins OPA+ and OPA- for the operational amplifier U2, and an amplifier ground pin OPA-GND for the operational amplifier U2. Among them, the amplifier power pins OPA+ and OPA- for the operational amplifier U2 are used to supply dual power to the operational amplifier U2. Therefore, the total power supply of the operational amplifier U2 is (OPA+)-(OPA-), and this total power supply determines the highest output voltage of the operational amplifier U2.

[0077] The positive voltage output terminal of the chip to be tested is connected to the drain of the second NMOS transistor NM2 through the positive voltage test pin AVDD. The ground terminal of the chip to be tested is used as the reference ground GND_B of the chip to be tested, connected to the ground test pin AVEE, and connected to the drain of the second NMOS transistor NM2 through the third capacitor C3. The source of the second NMOS transistor NM2 is connected to the reference ground GND_B of the chip to be tested through the third source terminal V-Source-3 and a 1Ω fourth resistor R44 (i.e., the detection resistor). The fourth resistor R44 is used to convert the current flowing through the second NMOS transistor NM2 into a voltage of the same magnitude for easy measurement of the current, and is configured with an SMA port to be directly connected to an oscilloscope through a signal line and display the measured current. In the case of a shortage of current probes, the fourth resistor R44 replaces the current probe to determine whether the current provided by the test device is accurate.

[0078] The input terminal VIN1 of the 1:1 isolation transformer D1 is connected to the output terminal of the signal generator through the third gate voltage pin V-Gate-3. The input ground GNDA is connected to the reference ground GND-A of the signal generator. The output terminal VOUT2 is connected to the positive input terminal +IN of the operational amplifier U2. The output ground GNDB is connected to the reference ground GND_B of the chip to be tested, and a fourth resistor R43 is provided between the output terminal VOUT2 and the output ground GNDB.

[0079] The negative input terminal +IN of the operational amplifier U2 is connected to the reference ground GND_B of the chip to be tested through the fourth resistor R44. The output terminal VOUT of the operational amplifier U2 is connected to the gate of the second NMOS transistor NM2. The operational amplifier U2 is powered by an external power supply through the amplifier power pins OPA+ and OPA-, and the output terminal VOUT is connected to the gate of the second NMOS.

[0080] The significant difference between the positive and negative voltage jump module 30 and the MOS transistor selection module 20 is the 1:1 isolation transformer D1. In addition, the principle of generating transient current is also different.

[0081] The specific principle of generating transient current is as follows: The positive and negative voltage jump module 30 drives the gate of the second NMOS transistor NM2 to conduct and turn off alternately through the operational amplifier U2. At this time, the output current of the second NMOS transistor NM2 is equal to the current flowing through the detection resistor (the forty-fourth resistor R44). The second NMOS transistor NM2 is quickly turned on and off by the voltage provided by the signal generator amplified by the operational amplifier U2 to achieve the effect of load jump. The second NMOS transistor NM2 has a conduction threshold voltage. When the voltage provided by the signal generator is lower than the conduction threshold voltage, the second NMOS transistor NM2 turns off. The second NMOS transistor NM2 is equivalent to a switch. The signal generator provides different gate-source voltages VGS of the second NMOS transistor NM2 to correspond to different drain-source currents IDS of the second NMOS transistor NM2, and then corresponds to the transient jump current of the chip to be tested. That is to say, when the second NMOS transistor NM2 is fully conducting, its output current is equal to the pulse high level of the output voltage of the signal generator / 1Ω. 1Ω is the resistance value of the forty-fourth resistor R44. At this time, the output current of the second NMOS transistor can be converted according to the level set by the signal generator and used as the current value after the jump of the required load jump current. The purpose of the resistance value of 1Ω of the forty-fourth resistor R44 is to convert the output current into the same value of voltage. For example, if the load current is 1 ampere, the voltage generated on this resistor is 1V. Therefore, only a voltage probe needs to be used to detect the voltage to obtain the required output current.

[0082] Therefore, when the voltage provided by the signal generator turns off the second NMOS transistor NM2, doesn't the load jump current become 0? Sometimes the load transient jump current needs to jump from 0 to another value. If the signal generator gives 0A, then this second NMOS transistor NM2 will not conduct, and then the load jump current will be 0A.

[0083] For the positive and negative voltage jump module 20, if the output voltage of the signal generator is directly connected to the fourth-fourth resistor R44, there is no reference ground at this time. It is short-circuited from positive voltage to negative voltage. If following the positive / negative voltage jump method, there will be instability in the output voltage provided by the signal generator at the third gate voltage pin V-Gate-3 with respect to the reference ground, and the possibility of reference ground floating. Therefore, an isolation device is needed to divide the IC reference ground and the MOS reference ground. The present utility model selects a 1:1 isolation transformer D1, and the output signal of the signal generator is used as its input terminal. However, during isolation, it will further deteriorate the original waveform and generate overshoot or undershoot. Therefore, a 10KΩ forty-third resistor R43 is selected between the output terminal VOUT2 and the output ground GNDB of the 1:1 isolation transformer D1 to achieve a damping effect. Although there will be some power loss, it is acceptable. In addition, the output terminal VOUT2 of the 1:1 isolation transformer D1 is connected to the non-inverting input terminal +IN of the operational amplifier U2, and the inverting input terminal -IN is connected to the fourth-fourth resistor R44 (i.e., the detection resistor) to the reference ground GND_B of the chip to be tested. Thus, by using the virtual short / virtual open characteristics of the operational amplifier U2, the output waveform of the signal generator can be equivalent to the resistor terminal (i.e., the third source terminal V-Source-3). Therefore, the jump current at this time is controlled by the output voltage of the signal generator at the third gate voltage pin V-Gate-3 / the resistance value of the fourth-fourth resistor R44 (Ohm's law). For example, the signal generator generates a 0 - 0.5V pulse signal at the third gate voltage pin V-Gate-3, which is output to the non-inverting input terminal +IN of the operational amplifier through the 1:1 isolation transformer D1. Using virtual short, the voltage difference across the fourth-fourth resistor R44 is also 0 - 0.5V. The output terminal VOUT of the operational amplifier U2 supplies power to the gate of the second NMOS transistor NM2 to turn it on. At this time, a loop is formed, and the output current flowing through the second NMOS transistor is the same as the current flowing through the 1Ω fourth-fourth resistor R44, and a current of 0 - 500mA can be obtained. The resistance value of the fourth-fourth resistor R44 is 1Ω and remains constant (used for voltage→current ratio conversion). In actual applications, the Gate voltage can be directly changed. It should be noted that the operational amplifier U2 needs to be powered separately, either with dual power supply or single power supply. The absolute values of the voltages at the amplifier power pins OPA+ and OPA- at both ends are the same. The output of the operational amplifier U2 is connected to the gate of the second NMOS transistor. When the operational amplifier U2 is working normally (at this time, the operational amplifier is in the amplification region), it will pull the output voltage to its power supply voltage (that is, the output of the operational amplifier U2 = the OPA+(-)OPA- of the operational amplifier U2). Therefore, the second NMOS transistor NM2 is normally working in the amplification region.

[0084] The amplifier power supply pins OPA+ and OPA- at both ends of the operational amplifier U2 are connected to the reference ground GND_B of the chip under test through the first capacitor C1 and the second capacitor C2. The first capacitor C1 and the second capacitor C2 are small capacitors used to filter out the input ripple.

[0085] When using this device, connect the positive voltage output of the test chip to the positive voltage test pin AVDD, and the negative voltage output to the ground test pin AVEE. According to the load jump current required by the chip under test, select the same magnitude of high and low levels with a signal generator.

[0086] Figure 3 It is the measured waveform diagram of the positive and negative voltage load transient jump provided by the test device for providing load transient jump of the present utility model. Among them, Pulse is the waveform diagram of the pulse signal provided by the signal generator, MOS-G is the waveform diagram of the gate G of the working MOS transistor, and ILOAD is the load jump current required by the chip under test. Figure 3 It is the waveform of the actual test of the positive and negative voltage jump module of the invention, which shows the effect of the positive and negative voltage load transient jump current provided by the test device for providing load transient jump of the present utility model. Figure 3 Among them, AVDD is the positive voltage output signal of the chip under test (or called DUT, device under test), and AVEE is the negative voltage output signal of the chip under test. Generally speaking, the chip under test includes two-way voltage outputs, that is, it includes both positive voltage and negative voltage outputs, that is Figure 3 AVDD + AVEE in it simultaneously includes the positive voltage output signal of the chip under test connected to the positive voltage test pin AVDD and the negative voltage output signal of the chip under test connected to the ground test pin AVEE. Therefore, the present invention is needed to meet the load jump of the positive and negative voltage combined output.

[0087] The above are only the preferred embodiments of the present utility model and are not intended to limit the scope of the present utility model. Various changes can be made to the above embodiments of the present utility model. All simple, equivalent changes and modifications made according to the claims and the content of the specification of the present utility model application fall within the scope of the claims of the present utility model patent. The content not described in detail in the present utility model is all conventional technical content.

Claims

1. A test device for providing load transient jumps, characterized in that It includes a heat dissipation module, a MOS transistor selection module, a positive and negative voltage jump module, and a variable resistor module; The heat dissipation module is configured to dissipate heat from the MOS transistor selection module, the positive and negative voltage jump module, and the variable resistor module; The MOS transistor selection module is configured to select one working MOS transistor from a first NMOS transistor and a first PMOS transistor to connect to the output terminal of the chip under test, so as to select the first NMOS transistor for positive voltage jump or the first PMOS transistor for negative voltage jump. The gate of the working MOS transistor is connected to a signal generator, and the output current is the load jump current required by the chip under test; The variable resistor module is removably connected between the working MOS transistor and the output terminal of the chip under test, and it improves the accuracy of the output current of the working MOS transistor by adjusting the resistance value; The positive and negative voltage jump module includes an operational amplifier connected to the signal generator through a 1:1 isolation transformer, and a second NMOS transistor whose gate is connected to the output terminal of the operational amplifier. The 1:1 isolation transformer is used to isolate the reference ground of the signal generator from the reference ground of the chip under test. The operational amplifier is used to provide a gate voltage for driving the second NMOS transistor to conduct and turn off alternately. The second NMOS transistor generates an output current consistent with the output waveform of the signal generator in the fully conducting state as the load jump current required by the chip under test.

2. The test device for providing load transient jumps according to claim 1, wherein, The heat dissipation module includes a current limiting chip and a cooling fan powered by the current limiting chip, and the current limiting chip is powered by an external DC power supply.

3. The test device for providing load transient jumps according to claim 1, characterized in that, The MOS transistor selection module further includes a drain selection slide switch and a source selection slide switch for switching the working MOS transistor between the first NMOS transistor and the first PMOS transistor; the sources of the first NMOS transistor and the first PMOS transistor are grounded, and the drain selection slide switch is connected to the output terminal of the chip under test.

4. The test device for providing load transient jumps according to claim 3, characterized in that, The MOS transistor selection module further includes a mode selection slide switch with its Gmode moving contact connected to the static contact of the drain selection slide switch and its Rmode moving contact connected to the variable resistor module. Among them, the static contact of the mode selection slide switch is connected to the output terminal of the chip under test, so that the drain selection slide switch can be connected to the output terminal of the chip under test.

5. The test device for providing load transient jumps according to claim 3, characterized in that The MOS transistor selection module further includes a first gate discharge module connected between the signal generator and the gate of the first NMOS transistor and a second gate discharge module connected between the signal generator and the gate of the first PMOS transistor; both the first gate discharge module and the second gate discharge module include a gate resistor and a pull-down resistor. The gate resistor is connected between the signal generator and the gate of the working MOS transistor, and the pull-down resistor is connected between the signal generator and the ground.

6. The test device for providing load transient jumps according to claim 5, wherein, The pull-down resistor is 1KΩ, and the gate resistor is 50Ω.

7. The test device for providing load transient jumps according to claim 1, characterized in that When the variable resistor module is moved into the circuit of the test device, it includes a first load resistor connected between the output terminal of the chip under test and the drain of the working MOS transistor and a second load resistor connected between the output terminal of the chip under test and the source of the working MOS transistor. The resistance values of the first load resistor and the second load resistor are adjustable.

8. The test device for providing load transient jumps according to claim 7, characterized in that, The variable resistor module includes a plurality of resistors connected in series in sequence as the first load resistor and a plurality of resistors connected in series in sequence as the second load resistor. An insertion port for a jumper cap is provided above each resistor. By changing the position of the jumper cap, the resistance values of the first load resistor and the second load resistor are changed. The adjustable range of the resistance value of the first load resistor is 1 - 99 Ω, and the adjustable range of the resistance value of the second load resistor is 100 - 9.9 KΩ.

9. The test device for providing load transient jumps according to claim 1, characterized in that, The output terminal of the chip under test is connected to the drain of the second NMOS transistor. The ground terminal of the chip under test serves as the reference ground of the chip under test and is connected to the drain of the second NMOS transistor through a third capacitor. The source of the second NMOS transistor is connected to the reference ground of the chip under test through a 1 Ω detection resistor.

10. The test device for providing load transient jumps according to claim 1, characterized in that, A 10 KΩ fourth resistor is connected between the output terminal and the output ground of the 1:1 isolation transformer to form a damping effect to suppress oscillations; when the operational amplifier is operating normally, its output voltage is pulled to its supply voltage.

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