Offset voltage temperature compensation circuit of single-channel operational amplifier

Abstract

The utility model belongs to the technical field of operational amplifiers, and relates to a single-channel operational amplifier offset voltage temperature compensation circuit which comprises an operational amplifier U2, and the output end of the operational amplifier U2 is connected with a same-direction amplification circuit composed of a resistor R9 and a resistor R10. The offset voltage regulating circuit is composed of an operational amplifier U2, a primary operational amplifier, a secondary operational amplifier, a resistor and a capacitor, and the temperature compensating circuit is composed of a JFET (Junction Field Effect Transistor) triode Q1, a JFET triode Q2, a Zener diode D2 and a Zener diode D3. An internal adjusting method is adopted, and a temperature compensation circuit is added to an offset voltage adjusting pin, so that the adverse effect of the offset voltage on the amplification precision of the operational amplifier U2 when the temperature changes is eliminated while the offset voltage is adjusted.

Description

Technical Field

[0001] The utility model belongs to the technical field of operational amplifiers, and particularly relates to a single-channel operational amplifier offset voltage temperature compensation circuit. Background Art

[0002] In power system measurement, since the input stage circuit parameters of an integrated operational amplifier cannot be absolutely symmetrical, when the input voltage is zero, the offset voltage is not zero, and the offset voltage changes with the change of temperature. Due to the existence of the offset voltage, the output accuracy of the operational amplifier is affected. Summary of the Invention

[0003] In order to solve the technical problem of the offset voltage changing with temperature, the utility model utilizes the offset voltage calibration pin provided by a single-channel operational amplifier to solve the technical problem of the offset voltage of the operational amplifier drifting with temperature. The technical scheme adopted by the utility model is as follows:

[0004] A single-channel operational amplifier offset voltage temperature compensation circuit includes an operational amplifier U2. The non-inverting input terminal of the operational amplifier U2 is electrically connected to the non-inverting input terminal of a first-stage operational amplifier U3A. The inverting input terminal of the first-stage operational amplifier U3A is electrically connected to the output terminal. Pins 4, 5, and 10 of the first-stage operational amplifier U3A are left floating. The output terminal of the first-stage operational amplifier U3A is electrically connected to one ends of a resistor R1, a capacitor C1, and a capacitor C2 respectively. The other ends of the resistor R1 and the capacitor C1 are electrically connected to one end of a resistor R3 respectively. The other end of the resistor R3 is electrically connected to one end of a capacitor C3 and the non-inverting input terminal of a second-stage operational amplifier U3B respectively. The other end of the capacitor C3 is grounded. The other end of the capacitor C2 is electrically connected to one ends of a resistor R2 and a resistor R4 respectively. The other end of the resistor R2 is electrically connected to the inverting input terminal of the operational amplifier U2. The other end of the resistor R4 is electrically connected to the inverting input terminal of the second-stage operational amplifier U3B, one end of a capacitor C4, and the gate of a JFET transistor Q1 respectively. The other end of the capacitor C4 is electrically connected to the output terminal of the second-stage operational amplifier U3B and the positive electrode of a zener diode D3 respectively. Pin 6 of the second-stage operational amplifier U3B is left floating. The resistance value of the resistor R1 is equal to that of the resistor R2. The resistance value of the resistor R3 is equal to that of the resistor R4. The capacitance value of the capacitor C1 is equal to that of the capacitor C2. The capacitance value of the capacitor C3 is equal to that of the capacitor C4. The output terminal of the second-stage operational amplifier U3B is electrically connected to one end of a resistor R6. The other end of the resistor R6 is electrically connected to one end of a resistor R5 and pin 8 of the operational amplifier U2 respectively. The other end of the resistor R5 is electrically connected to one end of a resistor R7. The other end of the resistor R7 is electrically connected to one end of a resistor R8 and pin 1 of the operational amplifier U2 respectively. The other end of the resistor R8 is grounded. The resistance value of the resistor R5 is equal to that of the resistor R7. The resistance value of the resistor R6 is equal to that of the resistor R8. The drain and source of the JFET transistor Q1 are electrically connected to the gate of a JFET transistor Q2 respectively. The drain and source of the JFET transistor Q2 are electrically connected to one end of the capacitor C4 respectively. The gate of the JFET transistor Q2 is electrically connected to the positive electrode of a zener diode D2. The negative electrode of the zener diode D2 is electrically connected to the negative electrode of the zener diode D3.

[0005] Preferably, the output terminal of the operational amplifier U2 is electrically connected to one end of a resistor R9. The other end of the resistor R9 is electrically connected to one end of a resistor R10. The other end of the resistor R10 is grounded. The other end of the resistor R9 and one end of the resistor R10 are electrically connected to the inverting input terminal of the operational amplifier U2 respectively.

[0006] Preferably, the positive power input terminal of the operational amplifier U2 is connected to a VDD 5V power supply. The negative power input terminal of the operational amplifier U2 is connected to a VDD -5V power supply.

[0007] Preferably, the output terminal of the operational amplifier U2 is electrically connected to the positive input terminal of a voltmeter XMM1. The negative input terminal of the voltmeter XMM1 is grounded.

[0008] Preferably, the positive electrode of the signal generator XFG1 is electrically connected to the non-inverting input terminal of the operational amplifier U2 and the non-inverting input terminal of the first-stage operational amplifier U3A respectively, the negative electrode of the signal generator XFG1 is left floating, and the common terminal of the signal generator XFG1 is grounded.

[0009] Preferably, the positive power input terminal of the second-stage operational amplifier U3B is connected to the VCC 5.0V power supply, and the negative power input terminal of the second-stage operational amplifier U3B is connected to the VEE -5.0V power supply.

[0010] Preferably, the other end of the resistor R5 and one end of the resistor R7 are electrically connected to the VDD 5V power supply respectively.

[0011] Advantages of the present utility model:

[0012] First, by taking the negative feedback value of the amplifier circuit to introduce the offset voltage into the temperature compensation circuit, and at the same time, before taking the input voltage for differential processing, it passes through the first-stage operational amplifier U3A (first-stage voltage follower circuit), making the input resistance of the offset voltage compensation circuit infinite, so as to minimize the influence of the offset voltage temperature compensation circuit on the amplifier circuit. At the same time, a capacitor is used in series at the differential end, so that when the non-inverting / inverting input terminals of the second-stage operational amplifier U3B perform differential operations, the interference of the DC component in the input signal to the DC offset voltage compensation is eliminated.

[0013] Second, the zener diode is incorporated into the capacitor of the integral amplifier circuit, which can not only provide a suitable voltage value to compensate the offset voltage, but also adjust the temperature drift of the offset voltage through the negative temperature coefficient of the zener diode. In order to prevent the zener diode from being broken down, here the JFET triode is used to protect the zener diode, increasing the stability of the offset voltage temperature compensation circuit. Description of the drawings

[0014] The drawings are used to provide a further understanding of the present utility model, and constitute a part of the specification. They are used together with the embodiments of the present utility model to explain the present utility model, and do not constitute a limitation to the present utility model. In the drawings:

[0015] Figure 1 is a schematic circuit diagram of the external adjustment method of the offset voltage in the prior art;

[0016] Figure 2 is a schematic circuit diagram of the internal adjustment method of the offset voltage in the prior art;

[0017] Figure 3 is a schematic structural diagram of the offset voltage temperature compensation circuit of the embodiment of the present utility model. Detailed implementation manners

[0018] The technical solution of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present utility model, rather than all embodiments.

[0019] Currently, there are mainly two methods for adjusting the offset voltage of an operational amplifier. Here, a reverse amplifier circuit is used as an example for both:

[0020] 1. External adjustment method: According to the adder principle of the operational amplifier, a voltage adjustment circuit is incorporated into the negative input terminal of the operational amplifier. As Figure 1 shown, the newly added voltage adjustment circuit does not affect the original input. Therefore, the voltage at the negative input terminal can be adjusted by a sliding rheostat, thereby playing a role in adjusting the offset voltage. The adjustment range of the offset voltage is: .

[0021] 2. Internal adjustment method: Many single-channel operational amplifiers have an offset voltage adjustment circuit inside and provide an offset voltage adjustment pin externally. Therefore, only a sliding rheostat needs to be connected to the offset voltage adjustment pin to adjust the offset voltage of the operational amplifier. As Figure 2 shown.

[0022] For the above two methods of adjusting the offset voltage of the operational amplifier, as long as the position of the sliding rheostat is accurate, the compensation for the offset voltage is accurate. However, in practical applications, after the detection device is produced, its circuit is fixed, and the compensation for the offset voltage is also fixed. However, the application environment where the detection device is located is not fixed, and the external temperature change will cause the offset voltage of the operational amplifier to drift, deviating from the original offset voltage, thereby affecting the accuracy of the detection device.

[0023] The embodiment of the present utility model adopts the internal adjustment method and adds an offset voltage temperature compensation circuit to the offset voltage adjustment pin to eliminate the adverse effect on the amplification accuracy of the operational amplifier caused by the change in temperature of the offset voltage while adjusting the offset voltage.

[0024] The operational amplifier used in the embodiment of the present utility model is U2. This operational amplifier U2 is single-channel and has offset voltage adjustment pins (pin 1 and pin 8). As Figure 3As shown in the figure, a single-channel operational amplifier offset voltage temperature compensation circuit includes an operational amplifier U2. The output terminal (pin 6) of the operational amplifier U2 is electrically connected to the positive input terminal of the voltmeter XMM1 and one end of the resistor R9 respectively, and the negative input terminal of the voltmeter XMM1 is grounded. The other end of the resistor R9 is electrically connected to one end of the resistor R10, and the other end of the resistor R10 is grounded. The other end of the resistor R9 and one end of the resistor R10 are electrically connected to the inverting input terminal (pin 2) of the operational amplifier U2 respectively. The positive power supply input terminal (pin 7) of the operational amplifier U2 is connected to the VDD 5V power supply, and the negative power supply input terminal (pin 4) of the operational amplifier U2 is connected to the VDD -5V power supply.

[0025] In Figure 3 it, the signal input is provided by the signal generator XFG1. The positive pole of the signal generator XFG1 is electrically connected to the non-inverting input terminal (pin 3) of the operational amplifier U2 and the non-inverting input terminal (pin 3) of the first-stage operational amplifier U3A respectively. The negative pole of the signal generator XFG1 is left floating, and the common terminal (COM terminal) of the signal generator XFG1 is grounded. The inverting input terminal (pin 2) of the first-stage operational amplifier U3A is electrically connected to the output terminal (pin 1). Since the application circuit of the first-stage operational amplifier U3A is a voltage follower function, pins 4, 5, and 10 can be left floating. The output terminal of the first-stage operational amplifier U3A is electrically connected to one end of the resistor R1, the capacitor C1, and the capacitor C2 respectively. The other ends of the resistor R1 and the capacitor C1 are electrically connected to one end of the resistor R3 respectively. The other end of the resistor R3 is electrically connected to one end of the capacitor C3 and the non-inverting input terminal (pin 7) of the second-stage operational amplifier U3B respectively. The other end of the capacitor C3 is grounded. The other end of the capacitor C2 is electrically connected to one end of the resistor R2 and the resistor R4 respectively. The other end of the resistor R2 is electrically connected to the inverting input terminal of the operational amplifier U2. The other end of the resistor R4 is electrically connected to the inverting input terminal (pin 8) of the second-stage operational amplifier U3B, one end of the capacitor C4, and the gate of the JFET transistor Q1 respectively. The source and drain of the JFET transistor Q2 are connected together. The other end of the capacitor C4 is electrically connected to the output terminal (pin 9) of the second-stage operational amplifier U3B and the positive pole of the zener diode D3 respectively. The positive power supply input terminal (pin 10) of the second-stage operational amplifier U3B is connected to the VCC 5.0V power supply, and the negative power supply input terminal (pin 4) of the second-stage operational amplifier U3B is connected to the VEE -5.0V power supply. Pin 6 of the second-stage operational amplifier U3B is left floating. Among them, the resistance values of the resistor R1 and the resistor R2 are equal, the resistance values of the resistor R3 and the resistor R4 are equal, the capacitance values of the capacitor C1 and the capacitor C2 are equal, and the capacitance values of the capacitor C3 and the capacitor C4 are equal.

[0026] The output terminal of the secondary operational amplifier U3B is electrically connected to one end of the resistor R6. The other end of the resistor R6 is electrically connected to one end of the resistor R5 and the pin 8 of the operational amplifier U2 respectively. The other end of the resistor R5 is electrically connected to one end of the resistor R7. The other end of the resistor R7 is electrically connected to one end of the resistor R8 and the pin 1 of the operational amplifier U2 respectively. The other end of the resistor R8 is grounded. The other end of the resistor R5 and one end of the resistor R7 are electrically connected to the VDD 5V power supply respectively. Among them, the resistance values of the resistor R5 and the resistor R7 are equal, and the resistance values of the resistor R6 and the resistor R8 are equal.

[0027] The drain and source of the JFET transistor Q1 are electrically connected to the gate of the JFET transistor Q2 respectively. The drain and source of the JFET transistor Q2 are electrically connected to one end of the capacitor C4 respectively. The gate of the JFET transistor Q2 is electrically connected to the positive electrode of the zener diode D2. The negative electrode of the zener diode D2 is electrically connected to the negative electrode of the zener diode D3.

[0028] The operational amplifier offset voltage temperature compensation circuit provided by the embodiment of the present invention is mainly divided into three modules.

[0029] Module 1: A non-inverting amplifier circuit mainly constructed by the operational amplifier U2, the resistor R9 and the resistor R10, and its amplification factor is: A = 1 + R9 / R10.

[0030] Module 2: An offset voltage adjustment circuit mainly composed of the operational amplifier U2, the primary operational amplifier U3A (voltage follower), resistors and capacitors. The secondary operational amplifier in the offset voltage adjustment circuit is U3B. The non-inverting input terminal of the secondary operational amplifier U3B is provided by the input signal V in+ through the pin 1 of the primary operational amplifier U3A. The inverting input terminal of the operational amplifier U3B is provided by the pin 2 of the operational amplifier U2. Considering that there is a DC offset voltage in the operational amplifier U2, the input signal V in+ of the operational amplifier U2 and the feedback signal V in- will not be exactly equal. The difference between the two is the DC offset voltage V os of the operational amplifier U2, and its relational expression is Formula 1:

[0031] V in- = V in+ + V os (1)

[0032] This offset voltage adjustment circuit mainly compensates the offset voltage for temperature by adjusting the pin 1 and pin 8 of the operational amplifier U2. In order to reduce the influence on the normal amplifier circuit, here at V in+A first - stage operational amplifier U3A is added at this point to make the input impedance of its compensation circuit infinite, thereby reducing the influence on the amplification circuit of operational amplifier U2. Generally, the offset voltage is at the uV level. If there are other DC biases in V in+ when, then the influence of the DC offset voltage will be negligible. Here, a differential operation is performed at the input end of the second - stage operational amplifier U3B. First, the resistor R1 and the capacitor C1 form a complete signal path to keep it consistent with the normal amplification circuit, and at the same time, the capacitor C2 is added. The function of the capacitor C2 is to introduce the AC signal in V in+ into V in- to eliminate the DC bias. Then, when performing differential operation at the non - inverting / inverting input ends of the second - stage operational amplifier U3B, the DC component in the signal can be eliminated. The DC component only contains the DC offset voltage of the operational amplifier U2 to ensure better compensation of the DC offset voltage. Since differential operation needs to be performed at the non - inverting / inverting input ends of the second - stage operational amplifier U3B, the consistency of the signal path must be ensured. Therefore, in the design, it is necessary to ensure that: the resistance values of resistor R1 and resistor R2 are equal, the resistance values of resistor R3 and resistor R4 are equal, the capacitance values of capacitor C1 and capacitor C2 are equal, and the capacitance values of capacitor C3 and capacitor C4 are equal. After differential operation, the actual operating voltage is the signal V in+ composed of the AC component of V in and the DC offset voltage of the operational amplifier U2. At the same time, since capacitors C1 and C2 are respectively connected in parallel to the input resistors R1 and R2, this circuit actually forms a PI regulator. When the JFET transistors Q1, JFET transistors Q2, zener diodes D2, and zener diodes D3 are not added, the input - output relationship formula of its circuit is formula 2:

[0033] (2)

[0034] where, V out is the output voltage of pin 9 of the second - stage operational amplifier U3B, and V in is the input voltage of the second - stage operational amplifier U3B.

[0035] Module three: A temperature compensation circuit mainly composed of JFET transistors Q1, JFET transistors Q2, zener diodes D2, and zener diodes D3. According to formula 2 mentioned in module two, in the signal actually input to the PI regulator, when V in+When it is 0, there is still a DC bias in the integrating circuit. As time goes by, the integrating circuit will tend to saturate. At this time, the integral part output by the circuit tends to the supply voltage of the second-stage operational amplifier U3B. However, once the power supply of the analog part in the circuit is determined, the supply voltage is also correspondingly determined. If it is changed, it will affect other analog circuit parts. In order to adjust the compensation circuit to the appropriate input voltage value, we incorporate the capacitor C4 into the zener diodes D2 and D3. Here, the zener diodes have two functions. First, by the voltage-regulating characteristic of the zener diodes, the integral part in formula 2 is changed, and the output is adjusted by the voltage regulation of the zener diodes. Second, because the zener diodes are relatively sensitive to temperature changes, the DC offset voltage of most operational amplifiers will increase with the increase in temperature. Here, the negative temperature coefficient characteristics of the zener diodes D2 and D3 are utilized. When the temperature rises, the stable value across the zener diodes will also change accordingly, thereby achieving the effect of temperature compensation for the offset voltage.

[0036] When the temperature compensation circuit only has the zener diodes D2 and D3, although it has the functions of voltage regulation and temperature compensation, there are two problems. First, because there is still a breakdown current in the zener diodes, when the AC component in V in is too large, it is still possible to burn out the zener diodes. Second, the voltage-regulated value of the zener diodes changing with temperature only acts on the integral part in formula 2, and its temperature drift compensation for the offset voltage is limited.

[0037] Here, we add the JFET transistors Q1 and Q2 to the temperature compensation circuit. Due to the structural properties of the JFET, there are equivalent capacitors between the gate (g), source (s), and drain (d) electrodes. In order to make the channel between the formed d-s of the zener diode have an equal width, the d-s is connected. When a voltage Ugs is applied between the g-s, an equivalent capacitor ∆C will be formed. This capacitor will affect the input and output of the compensation circuit. The final relationship between its input and output is formula 3:

[0038] (3)

[0039] The equivalent capacitor ∆C here is affected by Ugs. When Ugs increases, the channel becomes wider and its equivalent capacitor ∆C will become smaller, and vice versa. The JFET transistors Q1 and Q2 are in a series relationship. Therefore, Ugs will be affected by the voltage-regulated values of the zener diodes D2 and D3. When the temperature of the zener diodes changes, their voltage-regulated values will also change accordingly, thereby causing a change in Ugs and ultimately affecting the output of the compensation circuit.

[0040] Although the gate-source of the JFET transistor is equivalent to an open circuit, the JFET transistor is used as an equivalent capacitor here. When the voltage changes, there is a voltage difference across its equivalent capacitor, and the charges in the circuit can still accumulate on the equivalent capacitor of the JFET transistor, which will not affect the operation of the circuit. At the same time, due to the existence of JFET transistor Q1 and JFET transistor Q2, when there are high-energy pulses in the input voltage, it can protect the zener diodes D2 and D3.

[0041] For Module 3, a negative temperature coefficient resistor can also be incorporated across the capacitor in the integrating circuit to change its output value. At the same time, since the negative temperature coefficient can also compensate for the offset voltage drift, but it is relatively complicated to select the appropriate resistance value and negative temperature coefficient for this method.

[0042] In the embodiments of the present utility model, the technical features not described in detail are all prior arts or conventional technical means, and will not be elaborated herein.

[0043] Finally, it should be noted that: the above embodiments are only specific implementation manners of the present utility model, used to illustrate the technical solutions of the present utility model, rather than limiting it. The protection scope of the present utility model is not limited thereto. Those skilled in the art should understand that: any person skilled in the art within the technical scope disclosed by the present utility model can modify the technical solutions recorded in the foregoing embodiments or can easily think of changes, or perform equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present utility model, and should all be covered within the protection scope of the present utility model.

Claims

1. A single-channel operational amplifier offset voltage temperature compensation circuit, comprising an operational amplifier U2, characterized in that: The non-inverting input terminal of the operational amplifier U2 is electrically connected to the non-inverting input terminal of the first-stage operational amplifier U3A, the inverting input terminal of the first-stage operational amplifier U3A is electrically connected to the output terminal, pins 4, 5 and 10 of the first-stage operational amplifier U3A are left floating, the output terminal of the first-stage operational amplifier U3A is electrically connected to the resistor R1, the capacitor C1 and one end of the capacitor C2 respectively, the other ends of the resistor R1 and the capacitor C1 are electrically connected to one end of the resistor R3 respectively, the other ends of the resistor R3 are electrically connected to one end of the capacitor C3 and the non-inverting input terminal of the second-stage operational amplifier U3B, the other end of the capacitor C3 is grounded, the other end of the capacitor C2 is electrically connected to one end of the resistor R2 and the resistor R4 respectively, the other end of the resistor R2 is electrically connected to the inverting input terminal of the operational amplifier U2, the other end of the resistor R4 is electrically connected to the inverting input terminal of the second-stage operational amplifier U3B, one end of the capacitor C4 and the gate of the JFET transistor Q1, the other end of the capacitor C4 is electrically connected to the output terminal of the second-stage operational amplifier U3B and the positive electrode of the voltage-stabilizing diode D3 respectively, and the second-stage operational amplifier U3B is electrically connected to the positive electrode of the voltage-stabilizing diode D3. Pin 6 of amplifier U3B is suspended, the resistance values of resistors R1 and R2 are equal, the resistance values of resistors R3 and R4 are equal, the capacitance values of capacitors C1 and C2 are equal, and the capacitance values of capacitors C3 and C4 are equal. The output end of the secondary operational amplifier U3B is electrically connected to one end of resistor R6, and the other end of resistor R6 is electrically connected to one end of resistor R5 and pin 8 of operational amplifier U2. The other end of resistor R5 is electrically connected to one end of resistor R7, and the other end of resistor R7 is electrically connected to one end of resistor R8. and pin 1 of the operational amplifier U2, the other end of the resistor R8 is grounded, the resistance values of the resistors R5 and R7 are equal, and the resistance values of the resistors R6 and R8 are equal; the drain and source of the JFET transistor Q1 are electrically connected to the gate of the JFET transistor Q2 respectively, the drain and source of the JFET transistor Q2 are electrically connected to one end of the capacitor C4 respectively, the gate of the JFET transistor Q2 is electrically connected to the anode of the Zener diode D2, and the cathode of the Zener diode D2 is electrically connected to the cathode of the Zener diode D3.

2. The single-channel operational amplifier offset voltage temperature compensation circuit according to claim 1, characterized in that: The output end of the operational amplifier U2 is electrically connected to one end of the resistor R9, the other end of the resistor R9 is electrically connected to one end of the resistor R10, the other end of the resistor R10 is grounded, and the other end of the resistor R9 and one end of the resistor R10 are respectively electrically connected to the inverting input end of the operational amplifier U2.

3. The single-channel operational amplifier offset voltage temperature compensation circuit according to claim 2, characterized in that: The positive power input terminal of the operational amplifier U2 is connected to the VDD 5V power supply, and the negative power input terminal of the operational amplifier U2 is connected to the VDD -5V power supply.

4. The single-channel operational amplifier offset voltage temperature compensation circuit according to claim 2, characterized in that: The output terminal of the operational amplifier U2 is electrically connected to the positive input terminal of the voltmeter XMM1 , and the negative input terminal of the voltmeter XMM1 is grounded.

5. The single-channel operational amplifier offset voltage temperature compensation circuit according to claim 2, characterized in that: The positive electrode of the signal generator XFG1 is electrically connected to the non-inverting input terminal of the operational amplifier U2 and the non-inverting input terminal of the first-stage operational amplifier U3A, respectively. The negative electrode of the signal generator XFG1 is suspended, and the common terminal of the signal generator XFG1 is grounded.

6. The single-channel operational amplifier offset voltage temperature compensation circuit according to claim 2, characterized in that: The positive power input terminal of the secondary operational amplifier U3B is connected to the VCC 5.0V power supply, and the negative power input terminal of the secondary operational amplifier U3B is connected to the VEE -5.0V power supply.

7. The single-channel operational amplifier offset voltage temperature compensation circuit according to claim 2, characterized in that: The other end of the resistor R5 and one end of the resistor R7 are electrically connected to the VDD 5V power supply respectively.

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