Efficient heat dissipation chip packaging structure and chip with same
By setting heat dissipation parts on the top and bottom of the chip and designing a thermoelectric separation structure on the PCB substrate, the problem of uneven heat dissipation of the chip is solved, and efficient double-sided heat dissipation and stable operation are achieved.
Patent Information
- Application Number
- CN202422569026.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-19
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2034-10-19
AI Technical Summary
In the prior art, the heat dissipation of high-power chips is mainly concentrated at the system level. The front of the die and the welding surface of the substrate are unevenly dissipated due to the insulation layer barrier, forming a temperature difference, which affects the performance of the chip and system.
The double-sided heat dissipation design is adopted, and the double-sided heat dissipation and temperature difference of the chip are leveled by setting heat dissipation on the top and bottom of the chip and designing a thermoelectric separation structure on the PCB substrate.
It improves the heat dissipation efficiency of the chip, flattens the temperature difference, improves the instability of the chip in high-speed operation or calculation, and ensures the stable operation of the chip.
Smart Images
Figure CN223206266U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of chip heat dissipation, and in particular relates to a chip packaging structure with high-efficiency heat dissipation and a chip with the structure. Background Art
[0002] Against the backdrop of increasing demand for supercomputing services, the use of Ai chips and supercomputing chips has begun to increase. These chips have more advanced manufacturing processes, high power consumption, and high heat generation. The heat dissipation solution is still at the system level. Although these chips use the Open Moding process during packaging and use the back of the die as the exposed heat dissipation surface, this single heat dissipation surface can no longer meet the heat dissipation needs of higher-manufactured chips. The front of the die and the soldering surface of the substrate are separated by an insulating layer, and the existing process does not perform special heat dissipation treatment in a targeted manner. This will accumulate a lot of heat on the front of the chip, resulting in a temperature difference between the two sides of the chip. This temperature difference will further affect the performance of the chip and the system. Utility Model Content
[0003] The purpose of the utility model is to provide a chip packaging structure with high-efficiency heat dissipation and a chip with the structure, so as to solve the above-mentioned problems existing in the prior art.
[0004] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0005] In a first aspect, the present invention provides a chip packaging structure with high-efficiency heat dissipation, comprising a chip housing, a chip die, and a PCB substrate, wherein the chip housing is arranged on the PCB substrate, a first heat sink is provided on the top of the chip die, the first heat sink is connected to the chip housing, and the chip die is encapsulated in the chip housing, a heat dissipation conductive member is provided on the bottom of the chip die, the heat dissipation conductive member is connected to the PCB substrate, the PCB substrate includes a connected substrate heat dissipation layer, the contact surface of the PCB substrate and the heat dissipation conductive member exposes the substrate heat dissipation layer, so that the substrate heat dissipation layer is connected to the heat dissipation conductive member, and a second heat sink is connected to the side of the substrate heat dissipation layer facing away from the heat dissipation conductive member.
[0006] When it is used, the chip die is exposed through the process, so that the first heat sink on the top of the chip die can effectively dissipate heat for the top surface of the chip die, dissipating the heat on the top surface of the chip die to the external environment. The heat dissipation conductive member at the bottom of the chip die can effectively dissipate heat for the bottom surface of the chip die, conducting the heat from the bottom surface of the chip die to the substrate heat dissipation layer of the PCB substrate, and then conducting it to the second heat sink through the substrate heat dissipation layer, and finally dissipating the heat to the external environment through the second heat sink. The design of heat dissipation at both ends can form an efficient heat conduction path from the inside to the outside of the chip, greatly increasing the heat dissipation efficiency of the chip after packaging. In addition, by dissipating heat from the two end surfaces of the chip die, the temperature difference between the two sides of the chip die can be effectively leveled, greatly improving the instability problem of the chip caused by temperature difference during high-speed operation or calculation.
[0007] In one possible design, the PCB substrate further includes a connected electrical connection layer. This electrically conductive layer provides a conductive pad on the bottom surface of the chip die, which is connected to the PCB substrate. The electrical connection layer is exposed at the interface between the PCB substrate and the conductive pad, electrically connecting the electrical connection layer and the conductive pad. In use, the electrical connection layer connects to the conductive pad on the chip die through the PCB substrate's electrical connection layer, providing electrical pathways for various signals and power to the chip die, ensuring proper operation of the chip.
[0008] In one possible design, the PCB substrate further includes a connecting insulating adhesive layer, disposed between the substrate heat dissipation layer and the electrical connection layer, for bonding the two layers together and thermally and electrically isolating them. In this embodiment, through a thermoelectrical separation process design, the insulating adhesive layer can be used to bond the two layers separately while also thermally and electrically isolating them, ensuring that the thermal conductivity path of the substrate heat dissipation layer and the conductive conductivity path of the electrical connection layer are independent and do not affect each other.
[0009] In one possible design, the PCB substrate is further provided with functional electronic components, the conductive ends of which are electrically connected to the electrical connection layer, and the heat dissipation surfaces of which are connected to the substrate heat dissipation layer. In application, by integrating other functional electronic components on the PCB substrate, they can be used in conjunction with the main chip die to assist with corresponding computing functions. The PCB substrate connects the conductive ends of the functional electronic components via the electrical connection layer, effectively connecting the functional electronic components to the conductive path. The PCB substrate connects the heat dissipation surfaces of the functional electronic components via the substrate heat dissipation layer, effectively connecting the functional electronic components to the thermal path, simultaneously ensuring the stable operation of the functional electronic components.
[0010] In one possible design, the PCB substrate is a copper substrate. When used, the copper substrate has excellent thermal conductivity, which is beneficial to the operation and heat dissipation of the chip, and the copper substrate has good processing performance and stability.
[0011] In one possible design, the heat dissipation conductive member is made of a copper-based material, an aluminum-based material, or a ceramic material. When used, the heat dissipation conductive member made of the copper-based material, the aluminum-based material, or the ceramic material has good heat dissipation performance and can effectively absorb and dissipate heat from the bottom surface of the chip die.
[0012] In a possible design, the chip housing is a plastic housing, a ceramic housing or a metal housing. In its application, the plastic housing is lighter and cheaper, while the ceramic housing and the metal housing have good thermal conductivity. The choice can be made according to actual conditions.
[0013] In a possible design, the first heat sink and the second heat sink are both made of aluminum alloy. When used, the first heat sink and the second heat sink made of aluminum alloy have good heat dissipation performance, are light in weight, and have low cost.
[0014] In one possible design, the first and second heat sinks are each provided with integrally formed heat dissipating fins. In practice, the design of heat dissipating fins on the first and second heat sinks can increase the contact area between the heat sinks and the external medium, facilitating rapid heat dissipation and improving the heat dissipation efficiency of the heat sinks.
[0015] In a second aspect, the present invention provides a chip with high-efficiency heat dissipation, wherein the chip comprises any one of the packaging structures in the first aspect.
[0016] Beneficial effects: The utility model opens a heat dissipation channel on one side and separately adds a heat conduction channel on the other side under the premise of complex signal transmission and large power supply plane of the existing packaging process, thereby achieving double-sided heat dissipation of the chip and effectively improving the heat dissipation effect of the chip; and can level the temperature difference between the two sides of the chip, greatly improving the instability problem of the chip caused by temperature difference during high-speed operation or calculation; at the same time, in conjunction with the corresponding layered PCB board design, it can achieve thermal and electrical separation effect to ensure stable operation of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0018] Figure 1 This is a schematic diagram of the packaging structure of the present invention from a first perspective;
[0019] Figure 2 This is a schematic diagram of the packaging structure of the present invention from a second viewing angle.
[0020] In the figure: 1. Chip housing; 2. Chip bare die; 3. PCB substrate; 31. Substrate heat dissipation layer; 32. Electrical connection layer; 33. Insulation adhesive layer; 4. First heat dissipation member; 5. Heat dissipation conductive member; 6. Second heat dissipation member; 7. Conductive pad; 8. Functional electronic components. DETAILED DESCRIPTION
[0021] It should be noted that the description of these embodiments is intended to aid understanding of the present invention and does not constitute a limitation of the present invention. The specific structural and functional details disclosed herein are merely intended to describe exemplary embodiments of the present invention. However, the present invention may be embodied in many alternative forms, and should not be construed as being limited to the embodiments set forth herein.
[0022] It should be understood that, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, it can mean a fixed connection, a detachable connection, or an integral connection; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean internal communication between two components. Those skilled in the art will be able to understand the specific meanings of the above terms in the embodiments based on specific circumstances.
[0023] In the following description, certain details are provided to facilitate a complete understanding of the example embodiments. However, one of ordinary skill in the art will appreciate that the example embodiments can be practiced without these specific details. For example, a system may be shown in a block diagram to avoid obscuring the example with unnecessary detail. In other embodiments, well-known processes, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiment.
[0024] Example 1:
[0025] This embodiment provides a chip packaging structure with high efficiency heat dissipation, such as Figure 1 and Figure 2As shown, it includes a chip housing 1, a chip die 2 and a PCB substrate 3. The chip housing 1 is arranged on the PCB substrate 3. A first heat sink 4 is provided on the top of the chip die 2. The first heat sink 4 is connected to the chip housing 1 to encapsulate the chip die 2 in the chip housing 1. A heat dissipation conductive member 5 is provided on the bottom of the chip die 2. The heat dissipation conductive member 5 is connected to the PCB substrate 3. The PCB substrate 3 includes a connected substrate heat dissipation layer 31. The contact surface between the PCB substrate 3 and the heat dissipation conductive member 5 exposes the substrate heat dissipation layer 31, so that the substrate heat dissipation layer 31 is connected to the heat dissipation conductive member 5. The surface of the substrate heat dissipation layer 31 facing away from the heat dissipation conductive member 5 is connected to a second heat sink 6.
[0026] In a specific implementation, by exposing the chip die 2 through the process, the first heat sink 4 on the top of the chip die 2 can effectively dissipate heat for the top surface of the chip die 2, dissipating the heat on the top surface of the chip die 2 to the external environment. The heat dissipation conductive member 5 at the bottom of the chip die 2 can effectively dissipate heat for the bottom surface of the chip die 2, conducting the heat on the bottom surface of the chip die 2 to the substrate heat dissipation layer 31 of the PCB substrate 3, and then conducting it to the second heat sink 6 through the substrate heat dissipation layer 31, and finally dissipating the heat to the external environment through the second heat sink 6. By designing heat dissipation at both ends, an efficient heat conduction path can be formed from the inside to the outside of the chip, greatly increasing the heat dissipation efficiency of the chip after packaging (the heat dissipation efficiency can be increased by more than 30%). In addition, by dissipating heat from the two end surfaces of the chip die 2, the temperature difference between the two sides of the chip die 2 can be effectively leveled, greatly improving the instability problem of the chip caused by temperature difference during high-speed operation or calculation.
[0027] Furthermore, the PCB substrate 3 includes a connected electrical connection layer 32. This electrical connection layer 32 is conductive. A conductive pad 7 is provided on the bottom surface of the chip die 2. This conductive pad 7 is connected to the PCB substrate 3. The electrical connection layer 32 is exposed at the interface between the PCB substrate 3 and the conductive pad 7, electrically connecting the electrical connection layer 32 and the conductive pad 7. In practice, the electrical connection layer 32 of the PCB substrate 3 connects to the conductive pad 7 of the chip die 2, providing electrical pathways for various signals and power to the chip die 2, ensuring proper operation of the chip.
[0028] Furthermore, the PCB substrate 3 includes a communicating insulating adhesive layer 33, which is disposed between the substrate heat dissipation layer 31 and the electrical connection layer 32. The insulating adhesive layer 33 is used to bond the substrate heat dissipation layer 31 and the electrical connection layer 32 together, and to thermally and electrically separate the substrate heat dissipation layer 31 from the electrical connection layer 32. In specific implementations, through a thermoelectrical separation process design, the insulating adhesive layer 33 can be configured to bond the substrate heat dissipation layer 31 and the electrical connection layer 32 separately while also thermally and electrically separating the two layers. This ensures that the thermal conduction path of the substrate heat dissipation layer 31 and the electrical conduction path of the electrical connection layer 32 are independent of each other and do not affect each other.
[0029] Furthermore, the PCB substrate 3 is provided with a functional electronic component 8, the conductive end of the functional electronic component 8 being electrically connected to the electrical connection layer 32, and the heat dissipation surface of the functional electronic component 8 being connected to the substrate heat dissipation layer 31. In specific implementations, by integrating other functional electronic components 8 on the PCB substrate 3, they can be used in conjunction with the main chip die 2 to assist in the corresponding computing functions. The PCB substrate 3 is connected to the conductive end of the functional electronic component 8 via the electrical connection layer 32, effectively connecting the functional electronic component 8 to the conductive path. The PCB substrate 3 is connected to the heat dissipation surface of the functional electronic component 8 via the substrate heat dissipation layer 31, effectively connecting the functional electronic component 8 to the thermal path, thereby simultaneously ensuring the stable operation of the functional electronic component 8.
[0030] Furthermore, the PCB substrate 3 is a copper substrate. In specific implementation, the copper substrate has excellent thermal conductivity, which is beneficial for the heat dissipation of the chip during operation, and the copper substrate has good processing performance and stability. The heat dissipation conductive member 5 is made of copper-based material, aluminum-based material or ceramic material. In specific implementation, the heat dissipation conductive member 5 made of copper-based material, aluminum-based material or ceramic material has good heat dissipation performance and can effectively absorb and dissipate heat from the bottom surface of the chip die 2. The choice of copper-based material, aluminum-based material or ceramic material can be determined according to actual conditions. The chip housing 1 is a plastic housing, ceramic housing or metal housing. Plastic housings are lighter and cheaper, while ceramic housings and metal housings have good thermal conductivity and can be selected according to actual conditions.
[0031] Furthermore, the first heat sink 4 and the second heat sink 6 are both made of aluminum alloy. In a specific implementation, the first heat sink 4 and the second heat sink 6 made of aluminum alloy have good heat dissipation performance, are lightweight, and have low cost. The first heat sink 4 and the second heat sink 6 are both provided with integrally formed heat dissipating fins. In a specific implementation, by designing heat dissipating fins on the first heat sink 4 and the second heat sink 6, the contact area between the heat sink and the external medium can be increased, which is conducive to the rapid dissipation of heat and improves the heat dissipation efficiency of the heat sink.
[0032] Example 2:
[0033] This embodiment provides a chip with high efficiency in heat dissipation, wherein the chip includes a packaging structure and corresponding external electrical components and electrical connectors matched with the packaging structure, such as Figure 1 and Figure 2 As shown, the packaging structure includes a chip housing 1, a chip die 2 and a PCB substrate 3. The chip housing 1 is arranged on the PCB substrate 3. A first heat sink 4 is provided on the top of the chip die 2. The first heat sink 4 is connected to the chip housing 1, and the chip die 2 is encapsulated in the chip housing 1. A heat dissipation conductive member 5 is provided on the bottom of the chip die 2. The heat dissipation conductive member 5 is connected to the PCB substrate 3. The PCB substrate 3 includes a connected substrate heat dissipation layer 31. The contact surface between the PCB substrate 3 and the heat dissipation conductive member 5 exposes the substrate heat dissipation layer 31, so that the substrate heat dissipation layer 31 is connected to the heat dissipation conductive member 5. The surface of the substrate heat dissipation layer 31 facing away from the heat dissipation conductive member 5 is connected to a second heat sink 6.
[0034] In a specific implementation, by exposing the substrate of the chip die 2 through the process, the first heat sink 4 on the top of the chip die 2 can effectively dissipate heat for the top surface of the chip die 2, dissipating the heat from the top surface of the chip die 2 to the external environment. The heat dissipation conductive member 5 at the bottom of the chip die 2 can effectively dissipate heat for the bottom surface of the chip die 2, conducting the heat from the bottom surface of the chip die 2 to the substrate heat dissipation layer 31 of the PCB substrate 3, and then conducting it to the second heat sink 6 through the substrate heat dissipation layer 31, and finally dissipating the heat to the external environment through the second heat sink 6. The design of heat dissipation at both ends can form an efficient heat conduction path from the inside to the outside of the chip, greatly increasing the heat dissipation efficiency of the chip after packaging (the heat dissipation efficiency can be increased by more than 30%). In addition, by dissipating heat from the two end surfaces of the chip die 2, the temperature difference between the two sides of the chip die 2 can be effectively leveled, greatly improving the instability problem of the chip caused by temperature difference during high-speed operation or calculation.
[0035] Furthermore, the PCB substrate 3 includes a connected electrical connection layer 32. This electrical connection layer 32 is conductive. A conductive pad 7 is provided on the bottom surface of the chip die 2. This conductive pad 7 is connected to the PCB substrate 3. The electrical connection layer 32 is exposed at the interface between the PCB substrate 3 and the conductive pad 7, electrically connecting the electrical connection layer 32 and the conductive pad 7. In practice, the electrical connection layer 32 of the PCB substrate 3 connects to the conductive pad 7 of the chip die 2, providing electrical pathways for various signals and power to the chip die 2, ensuring proper operation of the chip.
[0036] Furthermore, the PCB substrate 3 includes a communicating insulating adhesive layer 33, which is disposed between the substrate heat dissipation layer 31 and the electrical connection layer 32. The insulating adhesive layer 33 is used to bond the substrate heat dissipation layer 31 and the electrical connection layer 32 together, and to thermally and electrically separate the substrate heat dissipation layer 31 from the electrical connection layer 32. In specific implementations, through a thermoelectrical separation process design, the insulating adhesive layer 33 can be configured to bond the substrate heat dissipation layer 31 and the electrical connection layer 32 separately while also thermally and electrically separating the two layers. This ensures that the thermal conduction path of the substrate heat dissipation layer 31 and the electrical conduction path of the electrical connection layer 32 are independent of each other and do not affect each other.
[0037] Furthermore, the PCB substrate 3 is provided with a functional electronic component 8, the conductive end of the functional electronic component 8 being electrically connected to the electrical connection layer 32, and the heat dissipation surface of the functional electronic component 8 being connected to the substrate heat dissipation layer 31. In specific implementations, by integrating other functional electronic components 8 on the PCB substrate 3, they can be used in conjunction with the main chip die 2 to assist in the corresponding computing functions. The PCB substrate 3 is connected to the conductive end of the functional electronic component 8 via the electrical connection layer 32, effectively connecting the functional electronic component 8 to the conductive path. The PCB substrate 3 is connected to the heat dissipation surface of the functional electronic component 8 via the substrate heat dissipation layer 31, effectively connecting the functional electronic component 8 to the thermal path, thereby simultaneously ensuring the stable operation of the functional electronic component 8.
[0038] Furthermore, the PCB substrate 3 is a copper substrate. In specific implementation, the copper substrate has excellent thermal conductivity, which is beneficial for the heat dissipation of the chip during operation, and the copper substrate has good processing performance and stability. The heat dissipation conductive member 5 is made of copper-based material, aluminum-based material or ceramic material. In specific implementation, the heat dissipation conductive member 5 made of copper-based material, aluminum-based material or ceramic material has good heat dissipation performance and can effectively absorb and dissipate heat from the bottom surface of the chip die 2. The choice of copper-based material, aluminum-based material or ceramic material can be determined according to actual conditions. The chip housing 1 is a plastic housing, ceramic housing or metal housing. Plastic housings are lighter and cheaper, while ceramic housings and metal housings have good thermal conductivity and can be selected according to actual conditions.
[0039] Furthermore, the first heat sink 4 and the second heat sink 6 are both made of aluminum alloy. In a specific implementation, the first heat sink 4 and the second heat sink 6 made of aluminum alloy have good heat dissipation performance, are lightweight, and have low cost. The first heat sink 4 and the second heat sink 6 are both provided with integrally formed heat dissipating fins. In a specific implementation, by designing heat dissipating fins on the first heat sink 4 and the second heat sink 6, the contact area between the heat sink and the external medium can be increased, which is conducive to the rapid dissipation of heat and improves the heat dissipation efficiency of the heat sink.
[0040] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.
Claims
1. A chip packaging structure with high heat dissipation efficiency, characterized in that: The invention comprises a chip housing (1), a chip die (2) and a PCB substrate (3), wherein the chip housing (1) is arranged on the PCB substrate (3), a first heat sink (4) is provided on the top of the chip die (2), the first heat sink (4) is connected to the chip housing (1), and the chip die (2) is encapsulated in the chip housing (1), a heat dissipation conductive member (5) is provided on the bottom of the chip die (2), the heat dissipation conductive member (5) is connected to the PCB substrate (3), the PCB substrate (3) comprises a connected substrate heat dissipation layer (31), the contact surface between the PCB substrate (3) and the heat dissipation conductive member (5) exposes the substrate heat dissipation layer (31), and the substrate heat dissipation layer (31) is connected to the heat dissipation conductive member (5), and the side of the substrate heat dissipation layer (31) facing away from the heat dissipation conductive member (5) is connected to a second heat sink (6).
2. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The PCB substrate (3) further includes a connected electrical connection layer (32), the electrical connection layer (32) is conductive, a conductive pad (7) is provided on the bottom surface of the chip bare die (2), the conductive pad (7) is connected to the PCB substrate (3), and the contact surface between the PCB substrate (3) and the conductive pad (7) exposes the electrical connection layer (32), so that the electrical connection layer (32) and the conductive pad (7) are electrically connected.
3. The chip packaging structure with high heat dissipation efficiency according to claim 2, characterized in that: The PCB substrate (3) further comprises a connected insulating adhesive layer (33), which is provided on the substrate heat dissipation layer (31) and the electrical connection layer (32) and is used to bond the substrate heat dissipation layer (31) and the electrical connection layer (32), and thermally and electrically separate the substrate heat dissipation layer (31) and the electrical connection layer (32).
4. The chip packaging structure with high heat dissipation efficiency according to claim 2, characterized in that: Functional electronic components (8) are also provided on the PCB substrate (3); the conductive ends of the functional electronic components (8) are electrically connected to the electrical connection layer (32); and the heat dissipation surface of the functional electronic components (8) is connected to the substrate heat dissipation layer (31).
5. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The PCB substrate (3) is a copper substrate.
6. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The heat dissipation conductive member (5) is made of copper-based material, aluminum-based material or ceramic material.
7. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The chip housing (1) is a plastic housing, a ceramic housing or a metal housing.
8. The chip packaging structure with high heat dissipation efficiency according to claim 1, characterized in that: The first heat sink (4) and the second heat sink (6) are both made of aluminum alloy.
9. The chip packaging structure with high heat dissipation efficiency according to claim 8, characterized in that: The first heat sink (4) and the second heat sink (6) are both provided with integrally formed heat sink fins.
10. A chip with high efficiency heat dissipation, characterized in that: The chip comprises the packaging structure according to any one of claims 1 to 9.