Trench gate IGBT device

Abstract

The utility model discloses a trench gate IGBT (Insulated Gate Bipolar Translator) device, which comprises at least two device unit cells positioned on a silicon wafer, a first N-type heavily doped emitter region and a second N-type heavily doped emitter region which are respectively positioned at the peripheries of a first trench and a second trench, and a deep trench which is arranged in an N-type lightly doped drift layer between adjacent MOS (Metal Oxide Semiconductor) device unit cells, an insulating medium column is filled in the deep groove, the upper end of the insulating medium column extends to the upper surface of the silicon wafer, and the lower end of the insulating medium column extends to the lower part of the N-type lightly doped drift layer; the upper surfaces of the first conductive polycrystalline silicon and the second conductive polycrystalline silicon in the device unit cells are respectively covered with a first dielectric layer and a second dielectric layer, an emitter metal layer covers the upper surfaces of at least two device unit cells, and a collector metal layer covers the lower surfaces of at least two device unit cells. When the trench gate IGBT device is turned off, an electric field curve tends to be gentle, and the situation that unit cells of the device interfere with each other and parasitic switch-on occurs is effectively avoided, so that the reliability of the trench gate IGBT device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a trench gate IGBT device. Background Art

[0002] The IGBT is a voltage-controlled MOS and bipolar hybrid device that combines the key advantages of both bipolar junction power transistors and power MOSFETs: high input impedance, low input drive power, low on-resistance, high current capacity, and fast switching speed. This makes the IGBT a key switching component for energy control and conversion in power electronics systems. Because it combines the advantages of both BJTs and FETs—high input impedance and low on-state voltage drop—it exhibits excellent switching characteristics and is widely used in applications requiring high voltage and high current.

[0003] When an existing IGBT device is turned off, interference occurs between the individual device cells, resulting in poor reliability of the IGBT device. Summary of the Invention

[0004] The purpose of the utility model is to provide a trench gate IGBT device, which makes the electric field curve tend to be flat when the device is turned off, effectively avoiding mutual interference between device cells and the occurrence of parasitic turn-on, thereby improving the reliability of the trench gate IGBT device.

[0005] To achieve the above-mentioned object, the technical solution adopted by the present invention is as follows: a trench gate IGBT device, comprising at least two device cells located on a silicon wafer, wherein the device cells further comprise: a P-well region located on the upper portion of the silicon wafer and an N-type lightly doped drift layer located below the P-well region, and an N-type electric field stop layer disposed between a P-type heavily doped collector region located on the lower portion of the silicon wafer and the N-type lightly doped drift layer;

[0006] A first trench and a second trench located in the P-well region extend into the N-type lightly doped drift layer, respectively. The first trench and the second trench respectively contain a first conductive polysilicon and a second conductive polysilicon. A first oxide layer and a second oxide layer are respectively formed between the first conductive polysilicon and the second conductive polysilicon and the inner walls of the first trench and the second trench;

[0007] A first N-type heavily doped emitter region and a second N-type heavily doped emitter region are respectively provided around the first trench and the second trench. A deep trench is provided in the N-type lightly doped drift layer between adjacent device cells. The deep trench is filled with an insulating dielectric column. The upper end of the insulating dielectric column extends to the upper surface of the silicon wafer, and the lower end of the insulating dielectric column extends to the lower part of the N-type lightly doped drift layer.

[0008] The upper surfaces of the first conductive polysilicon and the second conductive polysilicon in the device unit cell are respectively covered with a first dielectric layer and a second dielectric layer, an emitter metal layer covers the upper surfaces of at least two device units, and a collector metal layer covers the lower surfaces of at least two device units.

[0009] The further improved scheme in the above technical scheme is as follows:

[0010] 1. In the above solution, the lower ends of the first trench and the second trench are located on the upper part of the N-type lightly doped drift layer.

[0011] 2. In the above solution, the emitter metal layer covers the surfaces of the first dielectric layer and the second dielectric layer.

[0012] 3. In the above solution, the lower end of the deep trench is lower than the lower ends of the first trench and the second trench.

[0013] 4. In the above solution, the width of the deep trench is smaller than the width of the first trench and the second trench.

[0014] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0015] The utility model discloses a trench gate IGBT device, which includes at least two device cells located on a silicon wafer. A deep trench is provided in the N-type lightly doped drift layer between adjacent MOS device cells. The deep trench is filled with an insulating dielectric column. The upper end of the insulating dielectric column extends to the upper surface of the silicon wafer, and the lower end of the insulating dielectric column extends to the lower part of the N-type lightly doped drift layer. When the device is turned off, the electric field curve tends to be flat, effectively avoiding mutual interference between the device cells and the occurrence of parasitic turn-on, thereby improving the reliability of the trench gate IGBT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Attachment Figure 1 This is a schematic structural diagram of a trench gate IGBT device of the present invention.

[0017] In the above figures: 1. Silicon wafer; 2. P-well region; 3. N-type lightly doped drift layer; 4. P-type heavily doped collector region; 5. N-type electric field stop layer; 61. First trench; 62. Second trench; 71. First conductive polysilicon; 72. Second conductive polysilicon; 81. First oxide layer; 82. Second oxide layer; 91. First N-type heavily doped emitter region; 92. Second N-type heavily doped emitter region; 101. First dielectric layer; 102. Second dielectric layer; 11. Insulating dielectric column; 12. Emitter metal layer; 13. Collector metal layer; 14. Deep trench; 15. Device unit cell. DETAILED DESCRIPTION

[0018] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.

[0019] Embodiment 1: A trench gate IGBT device comprises at least two device cells 15 located on a silicon wafer 1, wherein the device cell 15 further comprises: a P-well region 2 located on an upper portion of the silicon wafer 1 and an N-type lightly doped drift layer 3 located below the P-well region 2; and an N-type electric field stop layer 5 disposed between a P-type heavily doped collector region 4 located on a lower portion of the silicon wafer 1 and the N-type lightly doped drift layer 3.

[0020] The first trench 61 and the second trench 62 located in the P-well region 2 extend into the N-type lightly doped drift layer 3 respectively. The first trench 61 and the second trench 62 respectively have a first conductive polysilicon 71 and a second conductive polysilicon 72 therein. The first conductive polysilicon 71 and the second conductive polysilicon 72 respectively have a first oxide layer 81 and a second oxide layer 82 between them and the inner walls of the first trench 61 and the second trench 62 respectively.

[0021] A first N-type heavily doped emitter region 91 and a second N-type heavily doped emitter region 92 are respectively formed around the first trench 61 and the second trench 62. A deep trench 14 is formed in the N-type lightly doped drift layer 3 between adjacent device cells 15. The deep trench 14 is filled with an insulating dielectric column 11. The upper end of the insulating dielectric column 11 extends to the upper surface of the silicon wafer 1, and the lower end of the insulating dielectric column 11 extends to the lower portion of the N-type lightly doped drift layer 3.

[0022] The first conductive polysilicon 71 and the second conductive polysilicon 72 in the device unit cell 15 are respectively covered with a first dielectric layer 101 and a second dielectric layer 102 on their upper surfaces, an emitter metal layer 12 covers the upper surfaces of at least two device units 15, and a collector metal layer 13 covers the lower surfaces of at least two device units 15.

[0023] The emitter metal layer 12 covers the surfaces of the first dielectric layer 101 and the second dielectric layer 102 .

[0024] The lower end of the deep trench 14 is lower than the lower ends of the first trench 61 and the second trench 62 .

[0025] The width of the deep trench 14 is smaller than the width of the first trench 61 and the second trench 62 .

[0026] Embodiment 2: A trench gate IGBT device comprises at least two device cells 15 located on a silicon wafer 1, wherein the device cell 15 further comprises: a P-well region 2 located on an upper portion of the silicon wafer 1 and an N-type lightly doped drift layer 3 located below the P-well region 2; and an N-type electric field stop layer 5 disposed between a P-type heavily doped collector region 4 located on a lower portion of the silicon wafer 1 and the N-type lightly doped drift layer 3.

[0027] The first trench 61 and the second trench 62 located in the P-well region 2 extend into the N-type lightly doped drift layer 3 respectively. The first trench 61 and the second trench 62 respectively have a first conductive polysilicon 71 and a second conductive polysilicon 72 therein. The first conductive polysilicon 71 and the second conductive polysilicon 72 respectively have a first oxide layer 81 and a second oxide layer 82 between them and the inner walls of the first trench 61 and the second trench 62 respectively.

[0028] A first N-type heavily doped emitter region 91 and a second N-type heavily doped emitter region 92 are respectively formed around the first trench 61 and the second trench 62. A deep trench 14 is formed in the N-type lightly doped drift layer 3 between adjacent device cells 15. The deep trench 14 is filled with an insulating dielectric column 11. The upper end of the insulating dielectric column 11 extends to the upper surface of the silicon wafer 1, and the lower end of the insulating dielectric column 11 extends to the lower portion of the N-type lightly doped drift layer 3.

[0029] The first conductive polysilicon 71 and the second conductive polysilicon 72 in the device unit cell 15 are respectively covered with a first dielectric layer 101 and a second dielectric layer 102 on their upper surfaces, an emitter metal layer 12 covers the upper surfaces of at least two device units 15, and a collector metal layer 13 covers the lower surfaces of at least two device units 15.

[0030] The lower ends of the first trench 61 and the second trench 62 are located on the upper portion of the N-type lightly doped drift layer 3 .

[0031] The lower end of the deep trench 14 is lower than the lower ends of the first trench 61 and the second trench 62 .

[0032] When the above-mentioned trench gate IGBT device is used, it includes at least two device cells located on a silicon wafer. A deep trench is provided in the N-type lightly doped drift layer between adjacent MOS device cells. The deep trench is filled with an insulating dielectric pillar. The upper end of the insulating dielectric pillar extends to the upper surface of the silicon wafer, and the lower end of the insulating dielectric pillar extends to the lower part of the N-type lightly doped drift layer. When the device is turned off, the electric field curve tends to be flat, effectively avoiding mutual interference between the device cells and the occurrence of parasitic turn-on, thereby improving the reliability of the trench gate IGBT device.

[0033] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those familiar with the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications based on the spirit of the present invention are intended to be included in the scope of protection of the present invention.

Claims

1. A trench gate IGBT device, characterized in that: The device unit cell (15) comprises at least two device units (15) located on a silicon wafer (1), wherein the device unit cell (15) further comprises: a P-type well region (2) located on the upper portion of the silicon wafer (1) and an N-type lightly doped drift layer (3) located below the P-type well region (2); and an N-type electric field stop layer (5) disposed between a P-type heavily doped collector region (4) located on the lower portion of the silicon wafer (1) and the N-type lightly doped drift layer (3); A first trench (61) and a second trench (62) located in the P-well region (2) extend into the N-type lightly doped drift layer (3), respectively. The first trench (61) and the second trench (62) respectively contain a first conductive polysilicon (71) and a second conductive polysilicon (72), and a first oxide layer (81) and a second oxide layer (82) are respectively formed between the first conductive polysilicon (71) and the second conductive polysilicon (72) and the inner walls of the first trench (61) and the second trench (62). A first N-type heavily doped emitter region (91) and a second N-type heavily doped emitter region (92) are respectively provided around the first trench (61) and the second trench (62); a deep trench (14) is provided in the N-type lightly doped drift layer (3) between adjacent device cells (15); an insulating dielectric column (11) is filled in the deep trench (14); the upper end of the insulating dielectric column (11) extends to the upper surface of the silicon wafer (1); and the lower end of the insulating dielectric column (11) extends to the lower part of the N-type lightly doped drift layer (3); The upper surfaces of the first conductive polysilicon (71) and the second conductive polysilicon (72) in the device unit cell (15) are respectively covered with a first dielectric layer (101) and a second dielectric layer (102); an emitter metal layer (12) covers the upper surfaces of at least two device units (15); and a collector metal layer (13) covers the lower surfaces of at least two device units (15).

2. The trench gate IGBT device according to claim 1, wherein: The lower ends of the first trench (61) and the second trench (62) are located on the upper part of the N-type lightly doped drift layer (3).

3. The trench gate IGBT device according to claim 1, wherein: The emitter metal layer (12) covers the surfaces of the first dielectric layer (101) and the second dielectric layer (102).

4. The trench gate IGBT device according to claim 1, wherein: The lower end of the deep groove (14) is lower than the lower ends of the first groove (61) and the second groove (62).

5. The trench gate IGBT device according to claim 1, wherein: The width of the deep groove (14) is smaller than the width of the first groove (61) and the second groove (62).

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