Insulated gate transistor device

Abstract

The utility model discloses an insulated gate transistor device which comprises a silicon wafer, the silicon wafer is provided with a P well region, an N-type lightly doped drift layer, an N-type electric field stop layer and a P-type heavily doped base region, and a first groove, a second groove and a third groove extend into the N-type lightly doped drift layer from the upper surface of the silicon wafer. A first N-type heavily doped emitter region is arranged on the periphery of one side, close to the second groove, of the first groove, a second N-type heavily doped emitter region is arranged on the periphery of one side, close to the second groove, of the third groove, and a P well region is arranged on the periphery of the second groove; and the upper surfaces of the first conductive polycrystalline silicon, the second conductive polycrystalline silicon and the third conductive polycrystalline silicon are respectively covered with a first dielectric layer, a second dielectric layer and a third dielectric layer. According to the insulated gate transistor device, holes mainly pass through the periphery of the second groove, and electrons mainly pass through the first groove and the third groove, so that carriers are extracted more uniformly, electric field distribution is more uniform, and the reliability of the device is effectively improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to an insulated gate transistor device. Background Art

[0002] Insulated-gate bipolar transistors (IGBTs) have become a mainstream power switching device in power electronics applications due to their advantages, including simple gate control, high current density, and low on-state voltage. IGBTs are three-terminal devices consisting of a gate, a collector, and an emitter. The IGBT's switching function is achieved by applying a positive gate voltage to form a channel, supplying base current to the PNP transistor and turning on the IGBT. Conversely, applying a reverse gate voltage eliminates the channel, allowing reverse base current to flow, turning the IGBT off. However, the reliability of existing IGBTs needs to be improved, and the switching losses are high. Utility Model Content

[0003] The purpose of the utility model is to provide an insulated gate transistor device, in which holes mainly pass through the periphery of the second groove, and electrons mainly pass through the vicinity of the first groove and the third groove, thereby more evenly extracting carriers, more evenly distributing the electric field, and effectively improving the reliability of the device.

[0004] To achieve the above-mentioned object, the technical solution adopted by the present invention is as follows: an insulated gate transistor device includes a silicon wafer, which has, from top to bottom, a P-well region, an N-type lightly doped drift layer, an N-type electric field stop layer, and a P-type heavily doped base region, wherein first, second, and third trenches spaced apart in the P-well region extend from the upper surface of the silicon wafer into the N-type lightly doped drift layer.

[0005] The first trench, the second trench and the third trench respectively contain a first conductive polysilicon, a second conductive polysilicon and a third conductive polysilicon, and the first conductive polysilicon, the second conductive polysilicon and the third conductive polysilicon respectively contain a first silicon dioxide layer, a second silicon dioxide layer and a third silicon dioxide layer between the first conductive polysilicon, the second conductive polysilicon and the inner wall of the first trench, the second trench and the third trench respectively;

[0006] The periphery of the first trench near the second trench has a first N-type heavily doped emitter region, the periphery of the third trench near the second trench has a second N-type heavily doped emitter region, and the periphery of the second trench is a P-well region;

[0007] The upper surfaces of the first conductive polysilicon, the second conductive polysilicon and the third conductive polysilicon are respectively covered with a first dielectric layer, a second dielectric layer and a third dielectric layer; an emitter metal layer covers the upper surfaces of the first N-type heavily doped emitter region, the second N-type heavily doped emitter region and the P-well region located between the first N-type heavily doped emitter region and the second N-type heavily doped emitter region; and a collector metal layer covers the surface of the P-type heavily doped base region.

[0008] The further improved scheme in the above technical scheme is as follows:

[0009] 1. In the above solution, the depth ratio of the first N-type heavily doped emitter region to the P-well region is 1:2-4.

[0010] 2. In the above solution, the depth ratio of the second N-type heavily doped emitter region to the P-well region is 1:2-4.

[0011] 3. In the above solution, the height of the N-type electric field stop layer is greater than the height of the P-type heavily doped base region.

[0012] 4. In the above solution, the width between the first trench and the second trench is 2 to 4 times the width of the first N-type heavily doped emitter region.

[0013] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0014] The utility model provides an insulated gate transistor device, wherein the first trench, the second trench and the third trench arranged at intervals in the P-well region all extend from the upper surface of the silicon wafer into the N-type lightly doped drift layer. The periphery of the first trench close to the second trench has a first N-type heavily doped emitter region, the periphery of the third trench close to the second trench has a second N-type heavily doped emitter region, the periphery of the second trench is the P-well region, holes mainly pass through the periphery of the second trench, and electrons mainly pass through the vicinity of the first trench and the third trench, thereby more evenly extracting carriers and more evenly distributing the electric field, thereby effectively improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Attachment Figure 1 This is a schematic structural diagram of an insulated gate transistor device of the present invention.

[0016] In the above figures: 1. silicon wafer; 2. P-well region; 3. N-type lightly doped drift layer; 4. P-type heavily doped base region; 5. N-type electric field stop layer; 61. first trench; 62. second trench; 63. third trench; 71. first conductive polysilicon; 72. second conductive polysilicon; 73. third conductive polysilicon; 81. first silicon dioxide layer; 82. second silicon dioxide layer; 83. third silicon dioxide layer; 91. first N-type heavily doped emitter region; 92. second N-type heavily doped emitter region; 101. first dielectric layer; 102. second dielectric layer; 103. third dielectric layer; 11. collector metal layer; 12. emitter metal layer. DETAILED DESCRIPTION

[0017] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.

[0018] Example 1: An insulated gate transistor device includes a silicon wafer 1. The silicon wafer 1 has, from top to bottom, a P-type well region 2, an N-type lightly doped drift layer 3, an N-type electric field stop layer 5, and a P-type heavily doped base region 4. A first trench 61, a second trench 62, and a third trench 63 are spaced apart within the P-type well region 2 and extend from the top surface of the silicon wafer into the N-type lightly doped drift layer 3.

[0019] The first trench 61, the second trench 62 and the third trench 63 respectively have a first conductive polysilicon 71, a second conductive polysilicon 72 and a third conductive polysilicon 73 therein, and a first silicon dioxide layer 81, a second silicon dioxide layer 82 and a third silicon dioxide layer 83 respectively between the first conductive polysilicon 71, the second conductive polysilicon 72 and the third conductive polysilicon 73 and the inner walls of the first trench 61, the second trench 62 and the third trench 63;

[0020] The first trench 61 has a first N-type heavily doped emitter region 91 around the side close to the second trench 62, and the third trench 63 has a second N-type heavily doped emitter region 92 around the side close to the second trench 62. The second trench 62 is surrounded by a P-well region 2.

[0021] The upper surfaces of the first conductive polysilicon 71, the second conductive polysilicon 72 and the third conductive polysilicon 73 are respectively covered with a first dielectric layer 101, a second dielectric layer 102 and a third dielectric layer 103, an emitter metal layer 12 covers the upper surfaces of the first N-type heavily doped emitter region 91, the second N-type heavily doped emitter region 92 and the P-well region 2 located between the first N-type heavily doped emitter region 91 and the second N-type heavily doped emitter region 92, and a collector metal layer 13 covers the surface of the P-type heavily doped base region 4.

[0022] The depth ratio of the first N-type heavily doped emitter region 91 to the P-well region 2 is 1:2.5.

[0023] The depth ratio of the second N-type heavily doped emitter region 92 to the P-well region 2 is 1:2.5.

[0024] The width between the first trench 61 and the second trench 62 is three times the width of the first N-type heavily doped emitter region 91 .

[0025] Example 2: An insulated gate transistor device includes a silicon wafer 1, which has, from top to bottom, a P-type well region 2, an N-type lightly doped drift layer 3, an N-type electric field stop layer 5, and a P-type heavily doped base region 4. A first trench 61, a second trench 62, and a third trench 63 are spaced apart within the P-type well region 2 and extend from the top surface of the silicon wafer into the N-type lightly doped drift layer 3.

[0026] The first trench 61, the second trench 62 and the third trench 63 respectively have a first conductive polysilicon 71, a second conductive polysilicon 72 and a third conductive polysilicon 73 therein, and a first silicon dioxide layer 81, a second silicon dioxide layer 82 and a third silicon dioxide layer 83 respectively between the first conductive polysilicon 71, the second conductive polysilicon 72 and the third conductive polysilicon 73 and the inner walls of the first trench 61, the second trench 62 and the third trench 63;

[0027] The first trench 61 has a first N-type heavily doped emitter region 91 around the side close to the second trench 62, and the third trench 63 has a second N-type heavily doped emitter region 92 around the side close to the second trench 62. The second trench 62 is surrounded by a P-well region 2.

[0028] The upper surfaces of the first conductive polysilicon 71, the second conductive polysilicon 72 and the third conductive polysilicon 73 are respectively covered with a first dielectric layer 101, a second dielectric layer 102 and a third dielectric layer 103, an emitter metal layer 12 covers the upper surfaces of the first N-type heavily doped emitter region 91, the second N-type heavily doped emitter region 92 and the P-well region 2 located between the first N-type heavily doped emitter region 91 and the second N-type heavily doped emitter region 92, and a collector metal layer 13 covers the surface of the P-type heavily doped base region 4.

[0029] The depth ratio of the first N-type heavily doped emitter region 91 to the P-well region 2 is 1:3.8.

[0030] The depth ratio of the second N-type heavily doped emitter region 92 to the P-well region 2 is 1:3.8.

[0031] The height of the N-type electric field stop layer 5 is greater than the height of the P-type heavily doped base region 4 .

[0032] The width between the first trench 61 and the second trench 62 is 3.5 times the width of the first N-type heavily doped emitter region 91 .

[0033] When using the above-mentioned insulated gate transistor device, the first trench, second trench and third trenches spaced apart in the P-well region all extend from the upper surface of the silicon wafer into the N-type lightly doped drift layer. The periphery of the first trench near the side of the second trench has a first N-type heavily doped emitter region, and the periphery of the third trench near the side of the second trench has a second N-type heavily doped emitter region. The periphery of the second trench is the P-well region. Holes mainly pass through the periphery of the second trench, and electrons mainly pass through the first trench and the third trench, thereby more evenly extracting carriers and distributing the electric field more evenly, thereby effectively improving the reliability of the device.

[0034] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those familiar with the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications based on the spirit of the present invention are intended to be included in the scope of protection of the present invention.

Claims

1. An insulated gate transistor device, characterized in that: The silicon wafer (1) comprises a P-type well region (2), an N-type lightly doped drift layer (3), an N-type electric field stop layer (5), and a P-type heavily doped base region (4) in order from top to bottom, wherein a first trench (61), a second trench (62), and a third trench (63) are arranged at intervals in the P-type well region (2) and extend from the upper surface of the silicon wafer into the N-type lightly doped drift layer (3); The first trench (61), the second trench (62) and the third trench (63) respectively contain a first conductive polysilicon (71), a second conductive polysilicon (72) and a third conductive polysilicon (73); and the first conductive polysilicon (71), the second conductive polysilicon (72) and the third conductive polysilicon (73) respectively contain a first silicon dioxide layer (81), a second silicon dioxide layer (82) and a third silicon dioxide layer (83) between the first conductive polysilicon (71), the second conductive polysilicon (72) and the third conductive polysilicon (73) and the inner walls of the first trench (61), the second trench (62) and the third trench (63); The periphery of the first trench (61) close to the second trench (62) has a first N-type heavily doped emitter region (91), the periphery of the third trench (63) close to the second trench (62) has a second N-type heavily doped emitter region (92), and the periphery of the second trench (62) is a P-well region (2); The upper surfaces of the first conductive polysilicon (71), the second conductive polysilicon (72) and the third conductive polysilicon (73) are respectively covered with a first dielectric layer (101), a second dielectric layer (102) and a third dielectric layer (103); an emitter metal layer (12) covers the upper surfaces of the first N-type heavily doped emitter region (91), the second N-type heavily doped emitter region (92) and the P-type well region (2) located between the first N-type heavily doped emitter region (91) and the second N-type heavily doped emitter region (92); and a collector metal layer (13) covers the surface of the P-type heavily doped base region (4).

2. The insulated gate transistor device according to claim 1, wherein: The depth ratio of the first N-type heavily doped emitter region (91) to the P-well region (2) is 1:2-4.

3. The insulated gate transistor device according to claim 1, wherein: The depth ratio of the second N-type heavily doped emitter region (92) to the P-well region (2) is 1:2-4.

4. The insulated gate transistor device according to claim 1, wherein: The height of the N-type electric field stopping layer (5) is greater than the height of the P-type heavily doped base region (4).

5. The insulated gate transistor device according to claim 1, wherein: The width between the first trench (61) and the second trench (62) is 2 to 4 times the width of the first N-type heavily doped emitter region (91).

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