MOS transistor assembly
By setting up multiple device units and P-type ion implantation units in the MOS transistor assembly, the gate structure is optimized, and the problem of large leakage current in the reverse bias state of the MOS device is solved, and the reliability and life of the device are improved.
Patent Information
- Application Number
- CN202421662885.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-15
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2034-07-15
AI Technical Summary
The existing MOS devices have a large leakage current in the reverse bias state, which affects their lifespan and reliability.
In the MOS transistor assembly, at least two device units are provided in the P-type doped base region and the N-type epitaxial region, and a P-type ion implantation part is provided in the P-type doped base region region between adjacent device units, an upper and lower gate sub-parts are provided in the trench, and the electric field strength is reduced under reverse bias, while controlling the trench depth and the metal layer connection method.
It effectively reduces leakage current in the contact surfaces of the P-type doped base region and the N-type epitaxial region, improves the reliability of the transistor assembly, and enhances its life and reliability while reducing the device size.
Smart Images
Figure CN223231509U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a MOS transistor component. Background Art
[0002] Power semiconductors are essential components for any electronic system, primarily used in various power supplies and load drivers. As power semiconductors evolve, newer generations are increasingly developing to achieve benefits such as energy conservation, material conservation, environmental protection, and miniaturization.
[0003] MOS devices are in the off state when VGS (gate-source voltage) is zero. When a suitable VGS is applied, majority carriers are attracted to the gate, thereby increasing the carriers under the polycrystalline gate and forming a conductive channel. Existing MOS devices have high leakage current under reverse bias, and their lifespan and reliability need to be improved. Utility Model Content
[0004] The purpose of the utility model is to provide a MOS transistor component, which is conducive to further reducing the device size under reverse bias and also reduces the leakage current at the contact surface between the P-type doped base region and the N-type epitaxial region, thereby ensuring the life and reliability of the device.
[0005] To achieve the above-mentioned object, the technical solution adopted by the present invention is: a MOS transistor component, comprising: an N-type doped drain layer located on the lower surface of a silicon wafer and a P-type doped base region located on the upper portion of the silicon wafer, wherein the region between the P-type doped base region and the N-type doped drain layer in the silicon wafer is an N-type epitaxial region.
[0006] At least two device units are spaced apart within the P-type doped base region and the N-type epitaxial region. The device unit further includes a trench in the P-type doped base region, the trench extending into the N-type epitaxial region, an N-type source region located above the P-type doped base region around the trench, an insulating dielectric layer on a surface of the silicon wafer opposite to the N-type doped drain layer, the insulating dielectric layer covering the surface of the P-type doped base region and above the trench, a gate portion in the trench, and a silicon dioxide layer between the gate portion and the inner wall of the trench;
[0007] The gate portion further includes an upper gate sub-portion located at the upper portion and a lower gate sub-portion located at the lower portion, the bottom of the upper gate sub-portion and the bottom of the P-type doped base region are on the same plane, the thickness of the silicon dioxide layer between the lower gate sub-portion and the inner wall of the trench gradually increases from top to bottom, and the thickness of the silicon dioxide layer between the lower gate sub-portion and the bottom of the trench is greater than the thickness of the gate portion and the sidewall of the trench;
[0008] The P-type doped base region between adjacent device units has a P-type ion implantation portion, the upper end of which contacts the insulating dielectric layer and the lower end extends into the N-type epitaxial region. An upper metal layer is located above the insulating dielectric layer and connected to the N-type source region, and a lower metal layer is located on the surface of the N-type doped drain layer opposite to the silicon wafer.
[0009] The further improved scheme in the above technical scheme is as follows:
[0010] 1. In the above solution, the depth of the trench is 2 to 3 times the depth of the P-type doped base region.
[0011] 2. In the above solution, the upper metal layer is connected to the end of the N-type source region away from the trench.
[0012] 3. In the above solution, the lower end of the P-type ion implantation portion is located in the middle of the N-type epitaxial region.
[0013] 4. In the above solution, there is an N-type epitaxial region between the P-type ion implantation portion and the N-type source region.
[0014] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:
[0015] 1. The MOS transistor assembly of the present invention has at least two device units spaced apart within its P-type doped base region and N-type epitaxial region. The P-type doped base region between adjacent device units has a P-type ion implantation portion, the upper end of which contacts the insulating dielectric layer and the lower end extends into the N-type epitaxial region. When the transistor assembly is in a reverse bias state, leakage current at the interface between the P-type doped base region and the N-type epitaxial region is greatly reduced, thereby reducing the probability of transistor assembly failure and further improving the reliability of the transistor assembly.
[0016] 2. The gate portion of the MOS transistor component of the present invention further includes an upper gate sub-portion located at the top and a lower gate sub-portion located at the bottom. The bottom of the upper gate sub-portion and the bottom of the P-type doped base region are on the same plane. The thickness of the silicon dioxide layer between the lower gate sub-portion and the inner wall of the trench gradually increases from top to bottom. The thickness of the silicon dioxide layer between the lower gate sub-portion and the bottom of the trench is greater than the thickness between the gate portion and the sidewall of the trench. When the trench mouth size is reduced, the electric field strength in the silicon dioxide layer below the P-type doped base region under reverse bias is reduced, which is conducive to further reducing the device size to cope with the increased electric field strength, thereby ensuring the life and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Attachment Figure 1 This is a schematic structural diagram of the MOS transistor component of the utility model.
[0018] In the above figures: 1. Silicon wafer; 2. N-type doped drain layer; 3. P-type doped base region; 4. N-type epitaxial region; 5. Trench; 6. N-type source region; 7. Insulating dielectric layer; 8. Gate portion; 81. Upper gate sub-portion; 82. Lower gate sub-portion; 9. Silicon dioxide layer; 10. Upper metal layer; 11. Lower metal layer; 12. Device unit; 13. P-type ion implantation portion. DETAILED DESCRIPTION
[0019] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.
[0020] Example 1: A MOS transistor assembly, comprising: an N-type doped drain layer 2 located on the lower surface of a silicon wafer 1 and a P-type doped base region 3 located on the upper portion of the silicon wafer 1; an N-type epitaxial region 4 located between the P-type doped base region 3 and the N-type doped drain layer 2 in the silicon wafer 1;
[0021] At least two device units 12 are spaced apart within the P-type doped base region 3 and the N-type epitaxial region 4. Each device unit 12 further includes a trench 5 in the P-type doped base region 3, the trench 5 extending into the N-type epitaxial region 4. An N-type source region 6 is formed above the P-type doped base region 3 around the trench 5. An insulating dielectric layer 7 is formed on the surface of the silicon wafer 1 opposite to the N-type doped drain layer 2. The insulating dielectric layer 7 covers the surface of the P-type doped base region 3 and above the trench 5. A gate portion 8 is formed in the trench 5, and a silicon dioxide layer 9 is formed between the gate portion 8 and the inner wall of the trench 5.
[0022] The gate portion 8 further includes an upper gate sub-portion 81 located at the top and a lower gate sub-portion 82 located at the bottom. The bottom of the upper gate sub-portion 81 is coplanar with the bottom of the P-type doped base region 3. The thickness of the silicon dioxide layer 9 between the lower gate sub-portion 82 and the inner wall of the trench 5 gradually increases from top to bottom. The thickness of the silicon dioxide layer 9 between the lower gate sub-portion 82 and the bottom of the trench 5 is greater than the thickness between the gate portion 8 and the sidewall of the trench 5.
[0023] The P-type doped base region 3 between adjacent device units 12 has a P-type ion implantation portion 13, the upper end of which is in contact with the insulating dielectric layer 7, and the lower end extends into the N-type epitaxial region 4. An upper metal layer 10 is located above the insulating dielectric layer 7 and connected to the N-type source region 6, and a lower metal layer 11 is located on the surface of the N-type doped drain layer 2 opposite to the silicon wafer 1.
[0024] The depth of the trench 5 is 2.4 times the depth of the P-type doped base region 3 .
[0025] The lower end of the P-type ion implantation portion 13 is located in the middle of the N-type epitaxial region 4 .
[0026] An N-type epitaxial region 4 is located between the P-type ion implantation portion 13 and the N-type source region 6 .
[0027] Example 2: A MOS transistor assembly, comprising: an N-type doped drain layer 2 located on the lower surface of a silicon wafer 1 and a P-type doped base region 3 located on the upper portion of the silicon wafer 1; an N-type epitaxial region 4 located between the P-type doped base region 3 and the N-type doped drain layer 2 in the silicon wafer 1;
[0028] At least two device units 12 are spaced apart within the P-type doped base region 3 and the N-type epitaxial region 4. Each device unit 12 further includes a trench 5 in the P-type doped base region 3, the trench 5 extending into the N-type epitaxial region 4. An N-type source region 6 is formed above the P-type doped base region 3 around the trench 5. An insulating dielectric layer 7 is formed on the surface of the silicon wafer 1 opposite to the N-type doped drain layer 2. The insulating dielectric layer 7 covers the surface of the P-type doped base region 3 and above the trench 5. A gate portion 8 is formed in the trench 5, and a silicon dioxide layer 9 is formed between the gate portion 8 and the inner wall of the trench 5.
[0029] The gate portion 8 further includes an upper gate sub-portion 81 located at the top and a lower gate sub-portion 82 located at the bottom. The bottom of the upper gate sub-portion 81 is coplanar with the bottom of the P-type doped base region 3. The thickness of the silicon dioxide layer 9 between the lower gate sub-portion 82 and the inner wall of the trench 5 gradually increases from top to bottom. The thickness of the silicon dioxide layer 9 between the lower gate sub-portion 82 and the bottom of the trench 5 is greater than the thickness between the gate portion 8 and the sidewall of the trench 5.
[0030] The P-type doped base region 3 between adjacent device units 12 has a P-type ion implantation portion 13, the upper end of which is in contact with the insulating dielectric layer 7, and the lower end extends into the N-type epitaxial region 4. An upper metal layer 10 is located above the insulating dielectric layer 7 and connected to the N-type source region 6, and a lower metal layer 11 is located on the surface of the N-type doped drain layer 2 opposite to the silicon wafer 1.
[0031] The depth of the trench 5 is 2.2 times the depth of the P-type doped base region 3 .
[0032] The upper metal layer 10 is connected to an end of the N-type source region 6 away from the trench 5 .
[0033] An N-type epitaxial region 4 is located between the P-type ion implantation portion 13 and the N-type source region 6 .
[0034] When the above-mentioned MOS transistor component is used, at least two device units are arranged at intervals in its P-type doped base region 3 and N-type epitaxial region 4. The P-type doped base region 3 between adjacent device units has a P-type ion implantation portion. The upper end of this P-type ion implantation portion contacts the insulating dielectric layer 7, and the lower end extends into the N-type epitaxial region 4. When the transistor component is in a reverse bias state, the leakage current at the contact surface between the P-type doped base region and the N-type epitaxial region is greatly reduced, thereby reducing the probability of the transistor component crashing and further improving the reliability of the transistor component. In addition, when the trench mouth size is reduced, the electric field strength in the silicon dioxide layer located below the P-type doped base region under the reverse bias condition is reduced, which is conducive to further reducing the device size to cope with the increased electric field strength, thereby ensuring the life and reliability of the device.
[0035] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those familiar with the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications based on the spirit of the present invention are intended to be included in the scope of protection of the present invention.
Claims
1. A MOS transistor component, characterized in that: include: An N-type doped drain layer (2) located on the lower surface of the silicon wafer (1) and a P-type doped base region (3) located on the upper part of the silicon wafer (1), wherein the region between the P-type doped base region (3) and the N-type doped drain layer (2) in the silicon wafer (1) is an N-type epitaxial region (4). At least two device units (12) are arranged at intervals in the P-type doped base region (3) and the N-type epitaxial region (4), and the device unit (12) further includes a trench (5) located in the P-type doped base region (3), the trench (5) extends to the inside of the N-type epitaxial region (4), and an N-type source region (6) is provided on the upper part of the P-type doped base region (3) around the trench (5). The surface of the silicon wafer (1) opposite to the N-type doped drain layer (2) has an insulating dielectric layer (7), and the insulating dielectric layer (7) covers the surface of the P-type doped base region (3) and above the trench (5). The trench (5) has a gate portion (8), and a silicon dioxide layer (9) is provided between the gate portion (8) and the inner wall of the trench (5); The gate portion (8) further includes an upper gate sub-portion (81) located at the upper portion and a lower gate sub-portion (82) located at the lower portion, the bottom of the upper gate sub-portion (81) and the bottom of the P-type doped base region (3) are on the same plane, the thickness of the silicon dioxide layer (9) between the lower gate sub-portion (82) and the inner wall of the groove (5) gradually increases from top to bottom, and the thickness of the silicon dioxide layer (9) between the lower gate sub-portion (82) and the bottom of the groove (5) is greater than the thickness of the gate portion (8) and the side wall of the groove (5); The P-type doped base region (3) between adjacent device units (12) has a P-type ion implantation portion (13), the upper end of the P-type ion implantation portion (13) contacts the insulating dielectric layer (7), and the lower end extends into the N-type epitaxial region (4), an upper metal layer (10) is located above the insulating dielectric layer (7) and connected to the N-type source region (6), and a lower metal layer (11) is located on the surface of the N-type doped drain layer (2) opposite to the silicon wafer (1).
2. The MOS transistor component according to claim 1, wherein: The depth of the trench (5) is 2 to 3 times the depth of the P-type doped base region (3).
3. The MOS transistor component according to claim 1, wherein: The upper metal layer (10) is connected to an end of the N-type source region (6) away from the trench (5).
4. The MOS transistor component according to claim 1, wherein: The lower end of the P-type ion implantation portion (13) is located in the middle of the N-type epitaxial region (4).
5. The MOS transistor component according to claim 1, wherein: An N-type epitaxial region (4) is provided between the P-type ion implantation portion (13) and the N-type source region (6).