Voltage regulator

Abstract

Disclosed is a voltage regulator for outputting a pixel power supply voltage supplied to a pixel of a display panel. The voltage regulator includes: a voltage divider configured to generate a feedback voltage by dividing a pixel power supply voltage; an error amplifier configured to generate an amplifier output voltage by comparing a reference voltage and a feedback voltage; the variable phase compensation circuit is configured to adjust the output voltage of the amplifier according to the load current; a source follower buffer configured to generate a control voltage by buffering the adjusted amplifier output voltage; and a transfer transistor configured to output an input voltage as a pixel power supply voltage based on the control voltage.

Description

Technical Field

[0001] Embodiments disclosed herein relate to a display device, and more particularly, to a voltage regulator for supplying a pixel power voltage to pixels of a display panel and a display device including the voltage regulator. Background Art

[0002] The pixel supply voltage supplied to the pixels of the display panel may need to be maintained at a constant voltage level even if the current drawn by the pixel changes. To generate a pixel supply voltage having a constant voltage level, the display device may include a voltage regulator, such as a low drop-out (LDO) regulator that regulates the pixel supply voltage. However, if the current flowing through the line that transmits the pixel supply voltage or the load current for the voltage regulator changes, the operation of the voltage regulator may become unstable, and the voltage regulator may not be able to maintain the pixel supply voltage at a constant voltage level. Utility Model Content

[0003] Some embodiments of the present disclosure provide a voltage regulator capable of stably operating over the entire load current range from a minimum load current to a maximum load current.

[0004] Some embodiments may provide a display device including a voltage regulator capable of stably operating over the entire load current range from a minimum load current to a maximum load current.

[0005] According to an embodiment, a voltage regulator can output a pixel power supply voltage that can be supplied to pixels of a display panel. The voltage regulator includes: a voltage divider configured to generate a feedback voltage by dividing the pixel power supply voltage; an error amplifier configured to generate an amplifier output voltage by comparing a reference voltage and the feedback voltage; a variable phase compensation circuit configured to adjust the amplifier output voltage according to a load current; a source follower buffer configured to generate a control voltage by buffering the adjusted amplifier output voltage; and a transfer transistor configured to output an input voltage as the pixel power supply voltage based on the control voltage.

[0006] In an embodiment, the voltage regulator may further include at least one compensation capacitor connected between an output node outputting the pixel power supply voltage and the error amplifier.

[0007] In an embodiment, the voltage regulator may further include an output capacitor connected between an output node outputting the pixel power supply voltage and a line for transmitting a ground voltage.

[0008] In an embodiment, a variable phase compensation circuit may include: a first transistor including a gate connected to the gate of the pass transistor, a first terminal for receiving a power supply voltage, and a second terminal; a first resistor including a first terminal connected to the second terminal of the first transistor and a second terminal; and a first capacitor including a first electrode connected to the second terminal of the first resistor and a second electrode connected to an amplifier output node of an output amplifier output voltage.

[0009] In an embodiment, the source follower buffer may include: a second transistor including a gate connected to an amplifier output node of an output amplifier output voltage, a first terminal connected to the gate of a pass transistor, and a second terminal for receiving a ground voltage; and a variable current source connected between a line for transmitting a power supply voltage and the gate of the pass transistor.

[0010] In an embodiment, the source follower buffer may include: a second transistor including a gate connected to an amplifier output node of an output amplifier output voltage, a first terminal connected to the gate of a pass transistor, and a second terminal for receiving a ground voltage; a first current source connected between a line for transmitting a power supply voltage and the gate of the pass transistor; a third transistor including a gate connected to the gate of the pass transistor, a first terminal for receiving a power supply voltage, and a second terminal; a fourth transistor including a gate connected to the second terminal of the third transistor, a first terminal connected to the second terminal of the third transistor, and a second terminal for receiving a ground voltage; a fifth transistor including a gate connected to the gate of the fourth transistor, a first terminal, and a second terminal; a second resistor including a first terminal connected to the second terminal of the fifth transistor and a second terminal for receiving a ground voltage; a sixth transistor including a gate connected to the first terminal of the fifth transistor, a first terminal for receiving a power supply voltage, and a second terminal connected to the first terminal of the fifth transistor; and a seventh transistor including a gate connected to the gate of the sixth transistor, a first terminal for receiving a power supply voltage, and a second terminal connected to the gate of the pass transistor.

[0011] In an embodiment, the voltage divider may include: a third resistor including a first terminal connected to an output node outputting a pixel supply voltage and a second terminal connected to a feedback node outputting a feedback voltage; and a fourth resistor including a first terminal connected to the feedback node and a second terminal for receiving a ground voltage.

[0012] In an embodiment, the error amplifier may include: an eighth transistor including a gate, a first terminal, and a second terminal for receiving a reference voltage; a ninth transistor including a gate, a first terminal, and a second terminal for receiving a feedback voltage; a second current source connected between a line for transmitting a power supply voltage and the first terminal of the eighth transistor and the first terminal of the ninth transistor; a tenth transistor including a gate connected to the second terminal of the eighth transistor, a first terminal connected to the second terminal of the eighth transistor, and a second terminal for receiving a ground voltage; an eleventh transistor including a gate connected to the second terminal of the ninth transistor, a first terminal connected to the second terminal of the ninth transistor, and a second terminal for receiving a ground voltage; a twelfth transistor including a gate connected to the gate of the tenth transistor, a first terminal, and a second terminal for receiving a ground voltage; a thirteenth transistor including a gate connected to the gate of the eleventh transistor, a first terminal, and a second terminal for receiving a ground voltage; and a fourteenth transistor , including a gate for receiving a direct current (DC) voltage, a first terminal, and a second terminal connected to the first terminal of a twelfth transistor; a fifteenth transistor, including a gate for receiving a DC voltage, a first terminal connected to an amplifier output node for outputting an output voltage of the output amplifier, and a second terminal connected to the first terminal of a thirteenth transistor; a sixteenth transistor, including a gate connected to the first terminal of a fourteenth transistor, a first terminal, and a second terminal connected to the first terminal of the fourteenth transistor; a seventeenth transistor, including a gate connected to the gate of the sixteenth transistor, a first terminal, and a second terminal connected to the amplifier output node; an eighteenth transistor, including a gate connected to the first terminal of the sixteenth transistor, a first terminal for receiving a power supply voltage, and a second terminal connected to the first terminal of the sixteenth transistor; and a nineteenth transistor, including a gate connected to the gate of the eighteenth transistor, a first terminal for receiving a power supply voltage, and a second terminal connected to the first terminal of the seventeenth transistor.

[0013] In an embodiment, the voltage regulator may further include a first compensation capacitor including a first electrode connected to an output node outputting the pixel power supply voltage and a second electrode connected to the second terminal of the fifteenth transistor.

[0014] In an embodiment, the voltage regulator may further include a second compensation capacitor including a first electrode connected to an output node outputting the pixel power supply voltage and a second electrode connected to the gate of the tenth transistor and the gate of the twelfth transistor.

[0015] In an embodiment, the voltage regulator may further include a third compensation capacitor including a first electrode connected to an output node outputting the pixel power supply voltage and a second electrode connected to the gate of the ninth transistor.

[0016] In an embodiment, the voltage regulator may further include a transient booster configured to adjust the pixel power supply voltage in a transient state of a load current change.

[0017] In an embodiment, the transient booster may include: a twentieth transistor including a gate connected to the gate of the transfer transistor, a first terminal for receiving a power supply voltage, and a second terminal; a third current source connected between the second terminal of the twentieth transistor and a line for transmitting a ground voltage; a twenty-first transistor including a gate connected to the gate of the transfer transistor, a first terminal for receiving the power supply voltage, and a second terminal; a twenty-second transistor including a gate, a first terminal connected to the second terminal of the twenty-first transistor, and a second terminal for receiving a ground voltage; a twenty-third transistor including a gate connected to the second terminal of the twenty-first transistor, a first terminal for receiving the power supply voltage, and a second terminal connected to the gate of the twenty-second transistor; a fifth resistor including a first terminal connected to the second terminal of the twenty-third transistor, and a second terminal for receiving a ground voltage; a second capacitor including a first electrode connected to the second terminal of the twentieth transistor, and a second electrode connected to the gate of the twenty-second transistor; and a twenty-fourth transistor including a gate connected to the gate of the twenty-second transistor, a first terminal connected to an output node for outputting a pixel power supply voltage, and a second terminal for receiving a ground voltage.

[0018] According to an embodiment, a voltage regulator can output a pixel power supply voltage that can be supplied to a pixel of a display panel. The voltage regulator includes: a voltage divider configured to generate a feedback voltage by dividing the pixel power supply voltage; an error amplifier configured to generate an amplifier output voltage by comparing a reference voltage and the feedback voltage; a first transistor including a gate connected to the gate of a transfer transistor, a first terminal for receiving the power supply voltage, and a second terminal; a first resistor including a first terminal connected to the second terminal of the first transistor and a second terminal; a first capacitor including a first electrode connected to the second terminal of the first resistor and a second electrode connected to an amplifier output node for outputting the amplifier output voltage; a second transistor including a gate connected to the amplifier output node, a first terminal connected to the gate of the transfer transistor, and a second terminal for receiving a ground voltage; a variable current source connected between a line for transmitting the power supply voltage and the gate of the transfer transistor; and a transfer transistor including a gate connected to the gate of the first transistor and the first terminal of the second transistor, a first terminal for receiving an input voltage, and a second terminal connected to an output node for outputting the pixel power supply voltage.

[0019] In an embodiment, the voltage regulator may further include at least one compensation capacitor connected between the output node and the error amplifier.

[0020] In an embodiment, the voltage regulator may further include an output capacitor connected between the output node and a line for transmitting a ground voltage.

[0021] According to an embodiment, a display device may include: a display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a scan driver configured to provide scan signals to the plurality of pixels; an emission driver configured to provide emission signals to the plurality of pixels; a controller configured to control the data driver, the scan driver, and the emission driver; and a voltage regulator configured to supply a pixel power supply voltage to the plurality of pixels. The voltage regulator includes: a voltage divider configured to generate a feedback voltage by dividing the pixel power supply voltage; an error amplifier configured to generate an amplifier output voltage by comparing a reference voltage and a feedback voltage; a variable phase compensation circuit configured to adjust the amplifier output voltage according to a load current; a source follower buffer configured to generate a control voltage by buffering the adjusted amplifier output voltage; and a transfer transistor configured to output a voltage input as the pixel power supply voltage based on the control voltage.

[0022] In an embodiment, a variable phase compensation circuit may include: a first transistor including a gate connected to the gate of the pass transistor, a first terminal for receiving a power supply voltage, and a second terminal; a first resistor including a first terminal connected to the second terminal of the first transistor and a second terminal; and a first capacitor including a first electrode connected to the second terminal of the first resistor and a second electrode connected to an amplifier output node of an output amplifier output voltage.

[0023] In an embodiment, the source follower buffer may include: a second transistor including a gate connected to an amplifier output node of an output amplifier output voltage, a first terminal connected to the gate of a pass transistor, and a second terminal for receiving a ground voltage; and a variable current source connected between a line for transmitting a power supply voltage and the gate of the pass transistor.

[0024] In an embodiment, the source follower buffer may include: a second transistor including a gate connected to an amplifier output node of an output amplifier output voltage, a first terminal connected to the gate of a pass transistor, and a second terminal for receiving a ground voltage; a first current source connected between a line for transmitting a power supply voltage and the gate of the pass transistor; a third transistor including a gate connected to the gate of the pass transistor, a first terminal for receiving a power supply voltage, and a second terminal; a fourth transistor including a gate connected to the second terminal of the third transistor, a first terminal connected to the second terminal of the third transistor, and a second terminal for receiving a ground voltage; a fifth transistor including a gate connected to the gate of the fourth transistor, a first terminal, and a second terminal; a second resistor including a first terminal connected to the second terminal of the fifth transistor and a second terminal for receiving a ground voltage; a sixth transistor including a gate connected to the first terminal of the fifth transistor, a first terminal for receiving a power supply voltage, and a second terminal connected to the first terminal of the fifth transistor; and a seventh transistor including a gate connected to the gate of the sixth transistor, a first terminal for receiving a power supply voltage, and a second terminal connected to the gate of the pass transistor.

[0025] As described above, in the voltage regulator and display device according to the embodiment, the voltage regulator can include a variable phase compensation circuit that adjusts the amplifier output voltage according to the load current, and a source follower buffer provided between the error amplifier and the pass transistor. Therefore, the voltage regulator according to the embodiment can have a phase margin greater than the reference phase margin over the entire load current range from the minimum load current to the maximum load current, and can operate stably even if the load current varies. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating a voltage regulator according to an embodiment of the present disclosure.

[0028] Figure 2A A Bode plot of a voltage regulator according to a comparative embodiment that does not include a variable phase compensation circuit and a source follower buffer and in which a compensation capacitor has a capacitance suitable for a maximum load current is shown.

[0029] Figure 2B A Bode plot of a voltage regulator according to a comparative embodiment that does not include a variable phase compensation circuit and a source follower buffer and in which a compensation capacitor has a capacitance suitable for a minimum load current is shown.

[0030] Figure 3An example of a Bode plot of a voltage regulator according to an embodiment of the present disclosure is shown.

[0031] Figure 4 is a circuit diagram illustrating a variable phase compensation circuit suitable for a voltage regulator according to an embodiment of the present disclosure.

[0032] Figure 5 is a circuit diagram illustrating an example of a source follower buffer suitable for a voltage regulator according to an embodiment of the present disclosure.

[0033] Figure 6 is a circuit diagram illustrating another example of a source follower buffer suitable for a voltage regulator according to an embodiment of the present disclosure.

[0034] Figure 7 is a circuit diagram illustrating a voltage divider suitable for a voltage regulator according to an embodiment of the present disclosure.

[0035] Figure 8 is a circuit diagram illustrating an error amplifier suitable for a voltage regulator according to an embodiment of the present disclosure.

[0036] Figure 9 is a circuit diagram illustrating a voltage regulator including a compensation capacitor according to an embodiment of the present disclosure.

[0037] Figure 10 2 is a Bode diagram illustrating a phase margin of a voltage regulator not including a variable phase compensation circuit and a source follower buffer according to a comparative example and a phase margin of a voltage regulator according to an embodiment of the present disclosure.

[0038] Figure 11 is a Bode diagram showing a pixel power supply voltage output by a voltage regulator according to an embodiment of the present disclosure when a load current varies.

[0039] Figure 12 is a block diagram illustrating a voltage regulator according to an embodiment of the present disclosure.

[0040] Figure 13 is a circuit diagram illustrating a transient voltage booster included in a voltage regulator according to an embodiment of the present disclosure.

[0041] Figure 14 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0042] Figure 15 is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure.

[0043] Figure 16 is a block diagram illustrating an electronic device including a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Hereinafter, specific embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0045] Figure 1 is a block diagram showing a voltage regulator according to an embodiment, Figure 2A showing a Bode plot of a voltage regulator according to a comparative embodiment that does not include a variable phase compensation circuit and a source follower buffer and in which the compensation capacitor has a capacitance suitable for a maximum load current, Figure 2B shows a Bode plot of a voltage regulator according to a comparative embodiment that does not include a variable phase compensation circuit and a source follower buffer and in which the compensation capacitor has a capacity suitable for a minimum load current, and Figure 3 An example of a Bode plot of a voltage regulator according to an embodiment of the present disclosure is shown.

[0046] Reference Figure 1 The voltage regulator 100 may be configured to generate and output a pixel supply voltage ELVDD that may be supplied to pixels of a display panel according to an embodiment of the present disclosure. The voltage regulator 100 may include a voltage divider 110, an error amplifier 130, a variable phase compensation circuit 150, a source follower buffer 170, and a transfer transistor TPASS. In some embodiments, the voltage regulator 100 may further include at least one compensation capacitor CC and at least one output capacitor OC.

[0047] The voltage divider 110 can generate the feedback voltage VFB by dividing the pixel power supply voltage ELVDD output by the voltage regulator 100. Figure 7 As shown in , the voltage divider 110 may include, but is not limited to, resistors R3 and R4 connected in series between an output node NO and a line for transmitting a ground voltage VGND to the voltage regulator 100, and the pixel power supply voltage ELVDD is output from the voltage regulator 100 at the output node NO.

[0048] The error amplifier 130 can generate an amplifier output voltage VAO by comparing a reference voltage VREF and a feedback voltage VFB. For example, a first input terminal of the error amplifier 130 can receive the reference voltage VREF from an external circuit, a second input terminal of the error amplifier 130 can receive the feedback voltage VFB from the voltage divider 110, and the error amplifier 130 can output the amplifier output voltage VAO at an amplifier output terminal or node NAO, where the amplifier output voltage VAO corresponds to the difference between the reference voltage VREF and the feedback voltage VFB. In some embodiments, the reference voltage VREF can be, but is not limited to, a bandgap reference voltage that is a substantially constant voltage regardless of power supply fluctuations, temperature changes, circuit load, etc.

[0049] The variable phase compensation circuit 150 can adjust the amplifier output voltage VAO generated by the error amplifier 130 according to the load current for the pixel power supply voltage ELVDD. In some embodiments, the variable phase compensation circuit 150 can adjust the amplifier output voltage VAO by an amount corresponding to the load current or the current flowing through the line for transmitting the pixel power supply voltage ELVDD to the pixel. For example, Figure 4 As shown in , the variable phase compensation circuit 150 may include a first transistor T1 having a gate connected to the gate of the transfer transistor TPASS. A load current may flow through the transfer transistor TPASS to a line that transmits the pixel power supply voltage ELVDD to the pixel, and a current proportional to the load current flowing through the transfer transistor TPASS may flow through the first transistor T1 (the gate of the first transistor T1 is connected to the gate of the transfer transistor TPASS). Therefore, by supplying a current proportional to the load current to the first resistor R1 and the first capacitor C1 in the variable phase compensation circuit 150, the amplifier output voltage VAO may be adjusted by an amount corresponding to the load current.

[0050] The source follower buffer 170 may be provided between the error amplifier 130 and the pass transistor TPASS, and may generate the control voltage VC by buffering the amplifier output voltage VAO adjusted by the variable phase compensation circuit 150. Since the source follower buffer 170 is located between the error amplifier 130 and the pass transistor TPASS, the gate of the pass transistor TPASS may be driven with low impedance. Figure 9 By using the source follower buffer 170 shown in FIG, the third pole TP of the feedback loop FBL generated at the gate of the pass transistor TPASS can be moved to a high frequency region. In some embodiments, the source follower buffer 170 may include a Figure 5 In this case, the variable current source VCS (for example, including Figure 6 The current of the first current source CS1, the third transistor T3 to the seventh transistor T7, and the second resistor R2 shown in FIG can increase as the load current (or the current flowing through the pass transistor TPASS) increases. Therefore, the driving capability of the pass transistor TPASS can be improved, and thus the performance of the voltage regulator 100 can be improved.

[0051] A first terminal of the transfer transistor TPASS receives an input voltage VIN, a second terminal of the transfer transistor TPASS is connected to an output node NO, and a gate of the transfer transistor TPASS receives a control signal VC from a source follower buffer 170. The transfer transistor TPASS can control a pixel power supply voltage ELVDD supplied to the pixel based on the input voltage VIN and the control voltage VC. In some embodiments, the input voltage VIN can be a voltage provided from an external device (e.g., a battery), or a voltage generated by a power management circuit (e.g., a power management integrated circuit (PMIC)) based on a voltage provided from an external device. The pixel power supply voltage ELVDD output by the transfer transistor TPASS can be provided to a pixel of the display panel, and the pixel can emit light based on the pixel power supply voltage ELVDD.

[0052] The output capacitor OC may be connected between the output node NO outputting the pixel power supply voltage ELVDD and a line transmitting the ground voltage VGND to the voltage regulator 100. The output capacitor OC may stabilize the pixel power supply voltage ELVDD. In some embodiments, the output capacitor OC may include a first electrode connected to the output node NO and a second electrode connected to the line transmitting the ground voltage VGND.

[0053] The compensation capacitor CC may be connected between the output node NO and the error amplifier 130. The compensation capacitor CC may compensate for the phase of the feedback voltage VFB in the feedback loop FBL. Figure 9 As shown in , the voltage regulator 100 may include (but is not limited to) a first compensation capacitor CC1 connected between the output node NO and the source of the fifteenth transistor T15, a second compensation capacitor CC2 connected between the output node NO and the gates of the tenth transistor T10 and the twelfth transistor T12, and a third compensation capacitor CC3 connected between the output node NO and the second input terminal of the error amplifier 130, the second input terminal of the error amplifier 130 being connected to receive the feedback voltage VFB.

[0054] As a comparative example of a voltage regulator similar to the voltage regulator 100 but not including the variable phase compensation circuit 150 and the source follower buffer 170 , the voltage regulator 100 may not operate stably, which may cause the pixel power supply voltage ELVDD to vary according to the load current. Figure 2A and Figure 2B The Bode plots of various voltage regulators similar to the voltage regulator 100 but not including the variable phase compensation circuit 150 and the source follower buffer 170 are shown. The Bode plots depict the frequency response of the system. For example, Figure 2A and Figure 2BThe Bode plot of φ may represent the gain of the feedback loop FBL according to the frequency of the sinusoidal signal when the sinusoidal signal is applied to the feedback loop FBL as the feedback voltage VFB in the comparative example.

[0055] Figure 2A This corresponds to a comparative example in which the compensation capacitor CC has a capacitance suitable for a maximum load current (eg, approximately 200 mA) as the load current and both the variable phase compensation circuit 150 and the source follower buffer 170 do not exist. Figure 2A As shown in FIG, the gain curve 210 of the feedback loop FBL for the maximum load current may have a second pole at a gain lower than approximately 0 dB (i.e., lower than unity gain). However, in this case, the gain curve 220 of the feedback loop FBL for the minimum load current (or no load current) (e.g., approximately 0 mA) may have a second pole SPa at a gain higher than approximately 0 dB (i.e., higher than unity gain). Since each pole shifts the phase of the feedback voltage VFB or the sinusoidal signal in the feedback loop FBL by approximately -90 degrees, if the second pole SPa is greater than unity gain, the feedback loop FBL may not have sufficient phase margin, and the voltage regulator 100 may not operate stably when the load current is the minimum load current.

[0056] Figure 2B This corresponds to a comparative example in which the compensation capacitor CC has a capacitance suitable for a minimum load current (eg, approximately 0 mA) as the load current and both the variable phase compensation circuit 150 and the source follower buffer 170 do not exist. Figure 2B As shown in FIG, the gain curve 230 of the feedback loop FBL for the minimum load current may have a second pole below unity gain. However, in this case, the gain curve 240 of the feedback loop FBL for the maximum load current (e.g., approximately 200 mA) may have a zero Z adjacent to the second pole. When the pole and the zero Z are adjacent to each other, the feedback loop FBL may be unstable and Figure 2B The voltage regulator 100 including the feedback loop FBL in the corresponding comparative example may oscillate.

[0057] In the voltage regulator 100 according to the embodiment, the variable phase compensation circuit 150 can adjust or compensate the phase of the signal at the amplifier output node NAO by an amount suitable for the load current. That is, the variable phase compensation circuit 150 can offset the change in impedance of each element of the voltage regulator 100 due to the change in load current. In addition, the source follower buffer 170 provided between the error amplifier 130 and the transfer transistor TPASS can drive the gate of the transfer transistor TPASS with low impedance. Therefore, as Figure 3As shown in , in the voltage regulator 100 including the variable phase compensation circuit 150 and the source follower buffer 170 according to the embodiment, the gain curve 250 of the feedback loop FBL for the minimum load current and the gain curve 260 of the feedback loop FBL for the maximum load current can both have a second pole below unity gain. Therefore, the voltage regulator 100 can have a phase margin greater than the reference phase margin over the entire load current range from the minimum load current to the maximum load current, and the voltage regulator 100 can operate stably. That is, even if the load current changes, the voltage regulator 100 according to the embodiment can operate stably. Although Figure 3 An example of a Bode diagram of the voltage regulator 100 including two poles is shown, but the Bode diagram of the voltage regulator 100 according to the embodiment is not limited to Figure 3 , and in other embodiments the feedback loop FBL of the voltage regulator 100 may have three or more poles.

[0058] Figure 4 is a circuit diagram showing a variable phase compensation circuit suitable for a voltage regulator according to an embodiment of the present disclosure.

[0059] according to Figure 4 The variable phase compensation circuit 150 of the embodiment shown in FIG may include a first transistor T1 , a first resistor R1 , and a first capacitor C1 .

[0060] Reference Figure 4 , the gate of the first transistor T1 can be connected to the gate of the transfer transistor TPASS. That is, the gate of the first transistor T1 and the gate of the transfer transistor TPASS can receive the same control voltage. Therefore, depending on the size ratio between the transfer transistor TPASS and the first transistor T1, a current proportional to the load current flowing through the transfer transistor TPASS can flow through the first transistor T1. For example, the transfer transistor TPASS and the first transistor T1 can have a size ratio of (but not limited to) 1000:1, and a current of approximately 1 / 1000 of the load current of the transfer transistor TPASS can flow through the first transistor T1. In some embodiments, the first transistor T1 may include a gate connected to the gate of the transfer transistor TPASS, a first terminal for receiving the power supply voltage VDD, and a second terminal connected to the first resistor R1. In addition, in some embodiments, the transfer transistor TPASS and the first transistor T1 can be implemented as (but not limited to) P-type metal oxide semiconductor (PMOS) transistors.

[0061] The first resistor R1 and the first capacitor C1 may be connected in series between the first transistor T1 and the amplifier output node NAO (eg, Figure 1In some embodiments, the first resistor R1 may include a first terminal connected to the second terminal of the first transistor T1 and a second terminal connected to the first capacitor C1, and the first capacitor C1 may include a first electrode connected to the second terminal of the first resistor R1 and a second electrode connected to the amplifier output node NAO of the output amplifier output voltage VAO.

[0062] The current flowing through the first transistor T1 can be provided to the first resistor R1 and the first capacitor C1, and thus the amplifier output voltage VAO at the amplifier output node NAO can be adjusted. Specifically, because the current flowing through the first transistor T1 is proportional to the load current flowing through the pass transistor TPASS, the variable phase compensation circuit 150 can adjust the amplifier output voltage VAO by an amount corresponding to the load current. Therefore, for any load current level within the entire load current range from the minimum load current to the maximum load current, the variable phase compensation circuit 150 can perform a phase compensation operation appropriate to the load current.

[0063] Figure 5 is a circuit diagram illustrating an example of a source follower buffer suitable for a voltage regulator according to an embodiment of the present disclosure.

[0064] according to Figure 5 The source follower buffer 170 of the embodiment shown in FIG may include a second transistor T2 and a variable current source VCS.

[0065] Reference Figure 5 , the second transistor T2 can receive the amplifier output voltage VAO as an input voltage at the gate of the second transistor T2, and the control voltage VC from the source follower buffer 170 can be the output voltage at the first terminal (e.g., the source) of the second transistor T2. In some embodiments, the second transistor T2 may include a gate connected to the amplifier output node that outputs the amplifier output voltage VAO, a first terminal connected to the gate of the pass transistor TPASS, and a second terminal for receiving the ground voltage VGND. In addition, in some embodiments, the second transistor T2 may be implemented as a PMOS transistor.

[0066] The variable current source VCS can provide current to the second transistor T2. In some embodiments, the current provided by the variable current source VCS can increase as the load current increases. In addition, in some embodiments, the variable current source VCS can be connected between a line for transmitting the power supply voltage VDD and the gate of the pass transistor TPASS or the first terminal of the second transistor T2.

[0067] Source follower buffer 170 can output a control voltage VC having substantially the same voltage level as amplifier output voltage VAO. Since amplifier output voltage VAO is not directly applied to the gate of pass transistor TPASS, and instead, control voltage VC generated by source follower buffer 170 based on amplifier output voltage VAO is applied to the gate of pass transistor TPASS, the gate of pass transistor TPASS can be driven with low impedance. Furthermore, source follower buffer 170 can move the third pole generated at the gate of pass transistor TPASS to a high-frequency region.

[0068] Figure 6 is a circuit diagram illustrating another example of a source follower buffer suitable for use in a voltage regulator according to an embodiment of the present disclosure.

[0069] Reference Figure 6 The source follower buffer 170a may include a second transistor T2, a first current source CS1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a second resistor R2, a sixth transistor T6, and a seventh transistor T7. Figure 5 The source follower buffer 170 is the same as Figure 6 The source follower buffer 170a includes a second transistor T2 connected between a current source and a ground voltage VGND, but the source follower buffer 170a may include a first current source CS1, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a second resistor R2, a sixth transistor T6, and a seventh transistor T7.

[0070] The first current source CS1 may be connected between a line for transmitting the power supply voltage VDD and the gate of the pass transistor TPASS. Even when the load current is the minimum load current or even when the seventh transistor T7 does not provide current to the second transistor T2, the first current source CS1 may provide current to the second transistor T2.

[0071] The gate of the third transistor T3 can be connected to the gate of the transfer transistor TPASS. Therefore, a current corresponding to the load current of the transfer transistor TPASS can flow through the third transistor T3. In some embodiments, the third transistor T3 may include a gate connected to the gate of the transfer transistor TPASS, a first terminal for receiving a power supply voltage VDD, and a second terminal connected to the fourth transistor T4. In addition, in some embodiments, the third transistor T3 can be implemented as a PMOS transistor.

[0072] The fourth transistor T4 can be connected in series to the third transistor T3. Therefore, the current flowing through the third transistor T3 can flow through the fourth transistor T4. In addition, the fourth transistor T4 and the fifth transistor T5 can form a current mirror, and the second resistor R2 can be connected to the second terminal (for example, source) of the fifth transistor T5. Therefore, a current proportional to the current flowing through the fourth transistor T4 can flow through the fifth transistor T5. In some embodiments, the fourth transistor T4 may include a gate connected to the second terminal of the third transistor T3, a first terminal connected to the second terminal of the third transistor T3, and a second terminal for receiving a ground voltage VGND, the fifth transistor T5 may include a gate connected to the gate of the fourth transistor T4, a first terminal connected to the sixth transistor T6, and a second terminal connected to the second resistor R2, and the second resistor R2 may include a first terminal connected to the second terminal of the fifth transistor T5 and a second terminal for receiving a ground voltage VGND. In addition, in some embodiments, the fourth transistor T4 and the fifth transistor T5 can be implemented as N-type metal oxide semiconductor (NMOS) transistors.

[0073] The sixth transistor T6 can be connected in series to the fifth transistor T5. Therefore, the current flowing through the fifth transistor T5 can flow through the sixth transistor T6. In addition, the sixth transistor T6 and the seventh transistor T7 can form a current mirror. Therefore, a current having the same current level as the current flowing through the sixth transistor T6 or the current flowing through the fifth transistor T5 can flow through the seventh transistor T7. In addition, through the third transistor T3 and the fourth transistor T4, the current flowing through the fifth transistor T5 can be proportional to the load current. Therefore, the seventh transistor T7 can provide a current proportional to the load current to the second transistor T2. Therefore, when the load current increases from the minimum load current to the maximum load current, the current provided to the second transistor T2 can increase, and the driving capability of the source follower buffer 170a can be improved. Therefore, the source follower buffer 170a can quickly generate the control voltage VC and can quickly drive the transfer transistor TPASS. In some embodiments, the sixth transistor T6 may include a gate connected to the first terminal of the fifth transistor T5, a first terminal for receiving the power supply voltage VDD, and a second terminal connected to the first terminal of the fifth transistor T5, and the seventh transistor T7 may include a gate connected to the gate of the sixth transistor T6, a first terminal for receiving the power supply voltage VDD, and a second terminal connected to the gate of the pass transistor TPASS. In addition, in some embodiments, the sixth transistor T6 and the seventh transistor T7 may be implemented as PMOS transistors.

[0074] Figure 7 is a circuit diagram illustrating a voltage divider suitable for a voltage regulator according to an embodiment of the present disclosure.

[0075] according to Figure 7 The voltage divider 110 of the embodiment shown in FIG may include a third resistor R3 and a fourth resistor R4 .

[0076] Reference Figure 7 , the third resistor R3 and the fourth resistor R4 can be connected in series between the output node NO outputting the pixel power supply voltage ELVDD and the line for transmitting the ground voltage VGND. Thus, the voltage divider 110 can generate a feedback voltage VFB that depends on the pixel power supply voltage ELVDD and the resistances of the third resistor R3 and the fourth resistor R4. In some embodiments, the third resistor R3 may include a first terminal connected to the output node NO and a second terminal connected to the feedback node NFB outputting the feedback voltage VFB. The fourth resistor R4 may include a first terminal connected to the feedback node NFB and a second terminal for receiving the ground voltage VGND.

[0077] Figure 8 is a circuit diagram illustrating an error amplifier suitable for a voltage regulator according to an embodiment of the present disclosure.

[0078] Figure 8 FIG. 1 shows an error amplifier 130 according to an embodiment, which may include an eighth transistor T8, a ninth transistor T9, a second current source CS2, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19. The error amplifier 130 may generate an amplifier output voltage VAO corresponding to a difference between a reference voltage VREF and a feedback voltage VFB.

[0079] In some embodiments, the eighth transistor T8 may include a gate, a first terminal, and a second terminal for receiving a reference voltage VREF. The ninth transistor T9 may include a gate, a first terminal, and a second terminal for receiving a feedback voltage VFB. The second current source CS2 may be connected between a line for transmitting a power supply voltage VDD and the first terminal of the eighth transistor T8 and the first terminal of the ninth transistor T9. Therefore, the current from the second current source CS2 may be divided into a current flowing through the eighth transistor T8 and a current flowing through the ninth transistor T9.

[0080] The tenth transistor T10 may include a gate connected to the second terminal of the eighth transistor T8, a first terminal connected to the second terminal of the eighth transistor T8, and a second terminal for receiving the ground voltage VGND. The eleventh transistor T11 may include a gate connected to the second terminal of the ninth transistor T9, a first terminal connected to the second terminal of the ninth transistor T9, and a second terminal for receiving the ground voltage VGND. The twelfth transistor T12 may include a gate connected to the gate of the tenth transistor T10, a first terminal, and a second terminal for receiving the ground voltage VGND, and the thirteenth transistor T13 may include a gate connected to the gate of the eleventh transistor T11, a first terminal, and a second terminal for receiving the ground voltage VGND. The tenth transistor T10 and the twelfth transistor T12 may form a current mirror, and the eleventh transistor T11 and the thirteenth transistor T13 may form a current mirror.

[0081] The fourteenth transistor T14 may include a gate for receiving a direct current (DC) voltage VDC, a first terminal, and a second terminal connected to the first terminal of the twelfth transistor T12, and the fifteenth transistor T15 may include a gate for receiving the DC voltage VDC, a first terminal connected to an amplifier output node NAO outputting the amplifier output voltage VAO, and a second terminal connected to the first terminal of the thirteenth transistor T13. Since the fourteenth transistor T14 and the fifteenth transistor T15 receive the DC voltage VDC, the gates of the fourteenth transistor T14 and the fifteenth transistor T15 may be grounded with respect to the alternating current (AC) component.

[0082] The sixteenth transistor T16 may include a gate connected to the first terminal of the fourteenth transistor T14, a first terminal, and a second terminal connected to the first terminal of the fourteenth transistor T14. The seventeenth transistor T17 may include a gate connected to the gate of the sixteenth transistor T16, a first terminal, and a second terminal connected to the amplifier output node NAO. The eighteenth transistor T18 may include a gate connected to the first terminal of the sixteenth transistor T16, a first terminal for receiving a power supply voltage VDD, and a second terminal connected to the first terminal of the sixteenth transistor T16, and the nineteenth transistor T19 may include a gate connected to the gate of the eighteenth transistor T18, a first terminal for receiving a power supply voltage VDD, and a second terminal connected to the first terminal of the seventeenth transistor T17.

[0083] In some embodiments, as Figure 8As shown in FIG, the eighth transistor T8, the ninth transistor T9, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, and the nineteenth transistor T19 may be implemented as PMOS transistors, and the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 may be implemented as NMOS transistors. Although Figure 8 An example of the error amplifier 130 is shown, but the error amplifier 130 of the voltage regulator according to an embodiment of the present disclosure is not limited to Figure 8 .

[0084] Figure 9 is a circuit diagram illustrating a voltage regulator including a compensation capacitor according to an embodiment of the present disclosure.

[0085] Reference Figure 9 , the voltage regulator 100 may include a first compensation capacitor CC1 , a second compensation capacitor CC2 , and a third compensation capacitor CC3 .

[0086] The first compensation capacitor CC1 may be connected between the output node NO outputting the pixel power supply voltage ELVDD and the second terminal (e.g., source) of the fifteenth transistor T15 of the error amplifier 130, and the second compensation capacitor CC2 may be connected between the output node NO and the gate of the tenth transistor T10 and the gate of the twelfth transistor T12 of the error amplifier 130. The first compensation capacitor CC1 and the second compensation capacitor CC2 may perform a phase compensation operation at a signal frequency at which a node of the feedback loop of the voltage regulator 100 has a phase opposite to that of the pixel power supply voltage ELVDD (e.g., approximately 180 degrees out of phase with the pixel power supply voltage ELVDD). The phase compensation operation may shift the second pole SP in the Bode plot for the feedback loop to a region below unity gain by shifting the frequency corresponding to unity gain to a lower frequency. In some embodiments, the first compensation capacitor CC1 may include a first electrode connected to the output node NO and a second electrode connected to the second terminal of the fifteenth transistor T15, and the second compensation capacitor CC2 may include a first electrode connected to the output node NO and a second electrode connected to the gate of the tenth transistor T10 and the gate of the twelfth transistor T12.

[0087] The third compensation capacitor CC3 can be connected between the output node NO and the gate of the ninth transistor T9 of the error amplifier 130, to which the feedback voltage VFB is applied. The third compensation capacitor CC3 can function as a high-pass filter and can form a zero in the Bode plot for the feedback loop, thereby shifting the second pole SP to a higher frequency. As a result, the frequency interval between the first pole FP and the second pole SP for the feedback loop can be increased, and the voltage regulator 100 can have a sufficient phase margin. In some embodiments, the third compensation capacitor CC3 may include a first electrode connected to the output node NO and a second electrode connected to the gate of the ninth transistor T9.

[0088] In the voltage regulator 100 according to the embodiment, the first pole FP can be generated at the second terminal of the fifteenth transistor T15, the second pole SP can be generated at the output node NO, and the third pole TP can be generated at the gate of the transfer transistor TPASS. By placing the source follower buffer 170 between the amplifier output node NAO and the gate of the transfer transistor TPASS where the third pole TP is generated, the third pole TP can be moved to a high frequency, and the voltage regulator 100 can have a further sufficient phase margin.

[0089] Figure 10 2 is a Bode diagram illustrating a phase margin of a voltage regulator not including a variable phase compensation circuit and a source follower buffer according to a comparative example and a phase margin of a voltage regulator according to an embodiment of the present disclosure.

[0090] like Figure 10 As shown in FIG, if the voltage regulator does not include a variable phase compensation circuit and a source follower buffer, the voltage regulator may have a phase margin 310 that is approximately 65 degrees less than the reference phase margin over most of the range of the load current I LOAD. However, the voltage regulator according to an embodiment of the present disclosure may have a phase margin 330 that is higher than the reference phase margin over the entire range of the load current I LOAD from the minimum load current (e.g., approximately 0 mA) to the maximum load current (e.g., approximately 200 mA). Therefore, the voltage regulator according to the disclosed embodiment may operate stably over the entire range of the load current I LOAD.

[0091] Figure 11 is a Bode diagram showing a pixel power supply voltage output by a voltage regulator according to an embodiment of the present disclosure when a load current varies.

[0092] Figure 11 Specifically, a graph 350 of the load current ILOAD and a graph 370 of the pixel supply voltage ELVDD are shown over time. Figure 11Even if the load current ILOAD changes between about 200 mA and about 80 mA, the voltage regulator according to an embodiment of the present disclosure can output the pixel power supply voltage ELVDD having a substantially constant voltage level. That is, even if the load current ILOAD changes, the voltage regulator according to the disclosed embodiment can operate stably.

[0093] Figure 12 is a block diagram illustrating a voltage regulator according to an embodiment of the present disclosure, Figure 13 1 is a circuit diagram showing a transient voltage booster included in a voltage regulator according to an embodiment of the present disclosure, and Figure 13 As shown in , a transient booster may be included in a voltage regulator according to an embodiment of the present disclosure.

[0094] Figure 12 Specifically, the voltage regulator 400 according to the embodiment may include a voltage divider 110, an error amplifier 130, a variable phase compensation circuit 150, a source follower buffer 170, a pass transistor TPASS, at least one compensation capacitor CC, an output capacitor OC, and a transient booster 490. In addition to the transient booster 490, the voltage regulator 400 may also include Figure 12 The voltage regulator 400 can be used with Figure 1 The voltage regulator 100 is substantially the same.

[0095] The transient booster 490 can adjust the pixel supply voltage ELVDD during transient changes in the load current ILOAD. In some embodiments, when the load current ILOAD changes from a maximum load current to a minimum load current and the pixel supply voltage ELVDD suddenly increases, the transient booster 490 can quickly adjust the pixel supply voltage ELVDD to a desired voltage level by reducing the current from the output node NO.

[0096] In some embodiments, as Figure 13As shown in FIG, the transient booster 490 may include a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a third current source CS3, a fifth resistor R5, and a second capacitor C2. The twentieth transistor T20 has a gate connected to the gate of the pass transistor TPASS, a first terminal for receiving the power supply voltage VDD, and a second terminal connected to the third current source CS3. The third current source CS3 is connected between the second terminal of the twentieth transistor T20 and a line for transmitting the ground voltage VGND. The twenty-first transistor T21 has a gate connected to the gate of the pass transistor TPASS, a first terminal for receiving the power supply voltage VDD, and a second terminal connected to the twenty-second transistor T22. The twenty-second transistor T22 has a gate, a first terminal connected to the second terminal of the twenty-first transistor T21, and a second terminal for receiving the ground voltage VGND. The twenty-third transistor T23 has a gate connected to the second terminal of the twenty-first transistor T21, a first terminal for receiving the power supply voltage VDD, and a second terminal connected to the gate of the twenty-second transistor T22. The fifth resistor R5 has a first terminal connected to the second terminal of the twenty-third transistor T23 and a second terminal for receiving the ground voltage VGND. The second capacitor C2 has a first electrode connected to the second terminal of the twentieth transistor T20 and a second electrode connected to the gate of the twenty-second transistor T22. The twenty-fourth transistor T24 has a gate connected to the gate of the twenty-second transistor T22, a first terminal connected to the output node NO for outputting the pixel power supply voltage ELVDD, and a second terminal for receiving the ground voltage VGND. In addition, in some embodiments, the twenty-first transistor T21 can be implemented as (but not limited to) an NMOS transistor, and the twentieth transistor T20, the twenty-second transistor T22, the twenty-third transistor T23, and the twenty-fourth transistor T24 can be implemented as (but not limited to) PMOS transistors.

[0097] Figure 14 is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 15 is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure.

[0098] Reference Figure 14The display device 600 according to the illustrated embodiment may include: a display panel 610 including a plurality of pixels PX; a data driver 620 providing a data signal DS to the plurality of pixels PX; a scan driver 630 providing a scan signal SS (e.g., a write signal GW, a compensation signal GC, and a bypass signal GB) to the plurality of pixels PX; an emission driver 640 providing an emission signal EM to the plurality of pixels PX; a controller 650 controlling the data driver 620, the scan driver 630, and the emission driver 640; and a voltage regulator 660 supplying a pixel power supply voltage ELVDD to the plurality of pixels PX.

[0099] The display panel 610 may include data lines, scan lines, emission lines, and a plurality of pixels PX connected to the data lines, scan lines, and emission lines. Figure 15 As shown in , each pixel PX may include a first transistor PXT1 , a second transistor PXT2 , a third transistor PXT3 , a fourth transistor PXT4 , a fifth transistor PXT5 , a first capacitor PXC1 , a second capacitor PXC2 , and a light emitting element EL.

[0100] The first transistor PXT1 may include a gate connected to the first capacitor PXC1 and the second capacitor PXC2, a first terminal for receiving the pixel supply voltage ELVDD, and a second terminal. The second transistor PXT2 may include a gate for receiving the write signal GW, a first terminal connected to the data line DL, and a second terminal connected to the first capacitor PXC1. The third transistor PXT3 may include a gate for receiving the compensation signal GC, a first terminal connected to the second terminal of the first transistor PXT1, and a second terminal connected to the gate of the first transistor PXT1. The fourth transistor PXT4 may include a gate for receiving the emission signal EM, a first terminal connected to the second terminal of the first transistor PXT1, and a second terminal connected to the light-emitting element EL. The fifth transistor PXT5 may include a gate for receiving the bypass signal GB, a first terminal connected to the light-emitting element EL, and a second terminal for receiving the ground voltage VGND. Furthermore, the first capacitor PXC1 may include a first electrode connected to the second terminal of the second transistor PXT2 and a second electrode connected to the gate of the first transistor PXT1. The second capacitor PXC2 may include a first electrode for receiving the pixel supply voltage ELVDD and a second electrode connected to the gate of the first transistor PXT1. The light-emitting element EL may include an anode connected to the second electrode of the fourth transistor PXT4 and the first terminal of the fifth transistor PXT5, and a cathode for receiving the low power supply voltage ELVSS. In some embodiments, the light-emitting element EL may be (but is not limited to) an organic light-emitting diode OLED. In other embodiments, the light-emitting element EL may be a micro light-emitting diode, a nano light-emitting diode (NED), a quantum dot (QD) light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0101] The data driver 620 can generate a data signal DS based on the output image data ODAT and the data control signal DCTRL received from the controller 650, and the data driver 620 can provide the data signal DS to the plurality of pixels PX via the data lines. In some embodiments, the data control signal DCTRL may include (but is not limited to) an output data enable signal, a horizontal start signal, and a load signal. In addition, in some embodiments, the data driver 620 and the controller 650 can be implemented as a single integrated circuit, and the single integrated circuit can be referred to as a timing controller embedded data driver (TED). In other embodiments, the data driver 620 and the controller 650 can be implemented as separate integrated circuits.

[0102] The scan driver 630 may generate a scan signal SS based on a scan control signal SCTRL received from the controller 650, and may sequentially provide the scan signal SS to a plurality of pixels PX via scan lines, row by row. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal, a scan clock signal, etc. Furthermore, the scan signal SS provided to each pixel PX may include, but is not limited to, a write signal GW, a compensation signal GC, and a bypass signal GB. In some embodiments, the scan driver 630 may be integrated or formed in a peripheral region of the display panel 610. In other embodiments, the scan driver 630 may be integrated or formed in a display region of the display panel 610. In other embodiments, the scan driver 630 may be implemented as one or more integrated circuits.

[0103] The emission driver 640 may generate an emission signal EM based on an emission control signal EMCTRL received from the controller 650, and the emission driver 640 may sequentially provide the emission signal EM to a plurality of pixels PX via emission lines row by row. In some embodiments, the emission control signal EMCTRL may include, but is not limited to, an emission start signal, an emission clock signal, etc. In addition, in some embodiments, the emission driver 640 may be integrated or formed in a peripheral area of the display panel 610. In other embodiments, the emission driver 640 may be integrated or formed in a display area of the display panel 610. In other embodiments, the emission driver 640 may be implemented as one or more integrated circuits.

[0104] The controller 650 (e.g., a timing controller) can receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a master clock signal. The controller 650 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and an emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL. The controller 650 can control the data driver 620 by providing the output image data ODAT and the data control signal DCTRL, control the scan driver 630 by providing the scan control signal SCTRL, and control the emission driver 640 by providing the emission control signal EMCTRL.

[0105] The voltage regulator 660 can supply a pixel power supply voltage ELVDD to a plurality of pixels PX of the display panel 610 based on an input voltage VIN and a reference voltage VREF. In some embodiments, the input voltage VIN can be provided from an external device (e.g., a battery), or can be generated by a power management circuit (e.g., a power management integrated circuit (PMIC)) based on a voltage provided from an external device. In addition, in some embodiments, the reference voltage VREF can be (but is not limited to) a bandgap reference voltage that is a substantially constant voltage regardless of power supply fluctuations, temperature changes, circuit loads, etc. The voltage regulator 660 can be Figure 1 The voltage regulator 100 or Figure 12 In some embodiments, the voltage regulator 660 may be integrated or formed in the peripheral area of the display panel 610. In other embodiments, the voltage regulator 660 may be integrated or formed in the display area of the display panel 610. In other embodiments, the voltage regulator 660 may be included in the data driver 620, the controller 650, or the power management circuit.

[0106] In the display device 600 according to the embodiment, the voltage regulator 660 may include a variable phase compensation circuit that adjusts the amplifier output voltage according to the load current, and a source follower buffer provided between the error amplifier and the pass transistor. Therefore, the voltage regulator 660 can have a phase margin greater than a reference phase margin over the entire load current range from the minimum load current to the maximum load current, and can operate stably even if the load current varies.

[0107] Figure 16 is a block diagram illustrating an electronic device including a display device according to an embodiment of the present disclosure.

[0108] Reference Figure 16 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0109] The processor 1110 can perform various computing functions or tasks. The processor 1110 can be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 can be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, in some embodiments, the processor 1110 can also be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0110] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0111] The storage device 1130 may be a solid-state drive (SSD), a hard disk drive (HDD), a compact disc read-only memory (CD-ROM), etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication link.

[0112] In the display device 1160, the voltage regulator may include a variable phase compensation circuit that adjusts the amplifier output voltage according to the load current, and a source follower buffer disposed between the error amplifier and the pass transistor. Thus, the voltage regulator can have a phase margin greater than a reference phase margin over the entire load current range from the minimum load current to the maximum load current, and can operate stably even when the load current varies.

[0113] The concepts disclosed herein can be applied to any electronic device 1100 that includes a display device 1160. For example, the concepts disclosed herein can be applied to mobile phones, smart phones, virtual reality (VR) devices, televisions (TVs) (e.g., digital TVs, 3D TVs, etc.), wearable electronic devices, personal computers (PCs) (e.g., tablet computers or laptop computers), home appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0114] The foregoing describes some specific embodiments but should not be construed as limiting those specific embodiments. Although several embodiments have been described, it will be readily apparent to those skilled in the art that many modifications may be made to the embodiments without materially departing from the novel teachings and advantages disclosed herein. Therefore, all such modifications are intended to be included within the scope defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various embodiments and should not be construed as limiting the specific embodiments disclosed, and that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A voltage regulator, characterized in that: The voltage regulator is used to output a pixel power supply voltage supplied to pixels of the display panel, and the voltage regulator includes: a voltage divider configured to generate a feedback voltage by dividing the pixel power supply voltage; an error amplifier configured to generate an amplifier output voltage by comparing a reference voltage and the feedback voltage; a variable phase compensation circuit configured to adjust the amplifier output voltage according to a load current; a source follower buffer configured to generate a control voltage by buffering the regulated amplifier output voltage; and The transfer transistor is configured to output an input voltage as the pixel power supply voltage based on the control voltage.

2. The voltage regulator according to claim 1, wherein: The voltage regulator further includes: At least one compensation capacitor is connected between the error amplifier and an output node outputting the pixel power supply voltage.

3. The voltage regulator according to claim 1, wherein: The voltage regulator further includes: An output capacitor is connected between an output node outputting the pixel power supply voltage and a line for transmitting a ground voltage.

4. The voltage regulator according to claim 1, wherein: The variable phase compensation circuit comprises: a first transistor including a gate connected to the gate of the pass transistor, a first terminal for receiving a power supply voltage, and a second terminal; a first resistor including a first terminal and a second terminal, the first terminal being connected to the second terminal of the first transistor; and A first capacitor includes a first electrode connected to the second terminal of the first resistor and a second electrode connected to an amplifier output node outputting the amplifier output voltage.

5. The voltage regulator according to claim 1, wherein: The source follower buffer comprises: a second transistor including a gate connected to an amplifier output node outputting the amplifier output voltage, a first terminal connected to the gate of the pass transistor, and a second terminal for receiving a ground voltage; and A variable current source is connected between a line for transmitting a power supply voltage and the gate of the pass transistor.

6. The voltage regulator according to claim 1, wherein: The source follower buffer comprises: a second transistor including a gate connected to an amplifier output node outputting the amplifier output voltage, a first terminal connected to the gate of the pass transistor, and a second terminal for receiving a ground voltage; a first current source connected between a line for transmitting a power supply voltage and the gate of the pass transistor; a third transistor including a gate connected to the gate of the pass transistor, a first terminal for receiving the power supply voltage, and a second terminal; a fourth transistor comprising a gate connected to the second terminal of the third transistor, a first terminal connected to the second terminal of the third transistor, and a second terminal for receiving the ground voltage; a fifth transistor comprising a gate connected to the gate of the fourth transistor, a first terminal, and a second terminal; a second resistor comprising a first terminal connected to the second terminal of the fifth transistor and a second terminal for receiving the ground voltage; a sixth transistor including a gate connected to the first terminal of the fifth transistor, a first terminal for receiving the power supply voltage, and a second terminal connected to the first terminal of the fifth transistor; and A seventh transistor includes a gate connected to the gate of the sixth transistor, a first terminal for receiving the power supply voltage, and a second terminal connected to the gate of the pass transistor.

7. The voltage regulator according to claim 1, wherein: The voltage divider comprises: a third resistor including a first terminal connected to an output node outputting the pixel power supply voltage and a second terminal connected to a feedback node outputting the feedback voltage; and The fourth resistor includes a first terminal connected to the feedback node and a second terminal for receiving a ground voltage.

8. The voltage regulator according to claim 1, wherein: The error amplifier comprises: an eighth transistor comprising a gate for receiving the reference voltage, a first terminal, and a second terminal; a ninth transistor comprising a gate for receiving the feedback voltage, a first terminal, and a second terminal; a second current source connected between a line for transmitting a power supply voltage and the first terminal of the eighth transistor and the first terminal of the ninth transistor; a tenth transistor comprising a gate connected to the second terminal of the eighth transistor, a first terminal connected to the second terminal of the eighth transistor, and a second terminal for receiving a ground voltage; an eleventh transistor comprising a gate connected to the second terminal of the ninth transistor, a first terminal connected to the second terminal of the ninth transistor, and a second terminal for receiving the ground voltage; a twelfth transistor comprising a gate connected to the gate of the tenth transistor, a first terminal, and a second terminal for receiving the ground voltage; a thirteenth transistor comprising a gate connected to the gate of the eleventh transistor, a first terminal, and a second terminal for receiving the ground voltage; a fourteenth transistor comprising a gate for receiving a DC voltage, a first terminal, and a second terminal connected to the first terminal of the twelfth transistor; a fifteenth transistor comprising a gate for receiving the DC voltage, a first terminal connected to an amplifier output node outputting the amplifier output voltage, and a second terminal connected to the first terminal of the thirteenth transistor; a sixteenth transistor including a gate connected to the first terminal of the fourteenth transistor, a first terminal, and a second terminal connected to the first terminal of the fourteenth transistor; a seventeenth transistor comprising a gate connected to the gate of the sixteenth transistor, a first terminal, and a second terminal connected to the amplifier output node; an eighteenth transistor including a gate connected to the first terminal of the sixteenth transistor, a first terminal for receiving the power supply voltage, and a second terminal connected to the first terminal of the sixteenth transistor; and A nineteenth transistor includes a gate connected to the gate of the eighteenth transistor, a first terminal for receiving the power supply voltage, and a second terminal connected to the first terminal of the seventeenth transistor.

9. The voltage regulator according to claim 8, wherein: The voltage regulator further includes: A first compensation capacitor includes a first electrode connected to an output node outputting the pixel power supply voltage and a second electrode connected to the second terminal of the fifteenth transistor.

10. The voltage regulator according to claim 8, wherein The voltage regulator further includes: A second compensation capacitor includes a first electrode connected to an output node outputting the pixel power supply voltage and a second electrode connected to the gate of the tenth transistor and the gate of the twelfth transistor.

11. The voltage regulator according to claim 8, wherein The voltage regulator further includes: The third compensation capacitor includes a first electrode connected to an output node outputting the pixel power supply voltage and a second electrode connected to the gate of the ninth transistor.

12. The voltage regulator according to claim 1, wherein The voltage regulator further includes: A transient voltage booster is configured to adjust the pixel power supply voltage in a transient state when the load current changes.

13. The voltage regulator according to claim 12, wherein: The transient voltage booster comprises: a twentieth transistor including a gate connected to the gate of the pass transistor, a first terminal for receiving a power supply voltage, and a second terminal; a third current source connected between the second terminal of the 20th transistor and a line for transmitting a ground voltage; a twenty-first transistor including a gate connected to the gate of the pass transistor, a first terminal for receiving the power supply voltage, and a second terminal; a twenty-second transistor comprising a gate, a first terminal connected to the second terminal of the twenty-first transistor, and a second terminal for receiving the ground voltage; a twenty-third transistor including a gate connected to the second terminal of the twenty-first transistor, a first terminal for receiving the power supply voltage, and a second terminal connected to the gate of the twenty-second transistor; a fifth resistor comprising a first terminal connected to the second terminal of the twenty-third transistor and a second terminal for receiving the ground voltage; a second capacitor including a first electrode connected to the second terminal of the twentieth transistor and a second electrode connected to the gate of the twenty-second transistor; and The twenty-fourth transistor includes a gate connected to the gate of the twenty-second transistor, a first terminal connected to an output node outputting the pixel power supply voltage, and a second terminal for receiving the ground voltage.

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