Transistor with improved thermal stability

Abstract

Various embodiments of the utility model relate to a transistor. The thermal stability of the transistor can be improved in different ways. An interface layer between the source / drain electrode and the semiconductor layer is formed of a material having a higher bond dissociation energy than indium oxide. Alternatively, the interface layer is formed of a metal-doped oxide semiconductor material. Alternatively, a metal layer or a metal oxide layer is formed between the source / drain electrode and the interface layer.

Description

Technical Field

[0001] An embodiment of the utility model relates to a transistor with improved thermal stability. Background Art

[0002] Integrated circuits are made up of a large number of transistors. Field-effect transistors typically consist of a substrate with a conductive gate electrode that controls the flow of current between source and drain electrodes. An electrically insulating gate dielectric layer separates the gate electrode from the source and drain electrodes. A semiconductor layer bridges the source and drain electrodes and contacts the gate dielectric layer. Utility Model Content

[0003] Various embodiments disclosed herein relate to a transistor comprising at least one source / drain electrode; an adhesion layer contacting the at least one source / drain electrode; a semiconductor layer; and at least one interface layer between the adhesion layer and the semiconductor layer. The at least one interface layer comprises a material having a higher bond dissociation energy than indium oxide.

[0004] Other embodiments of the present disclosure relate to a transistor comprising at least one source / drain electrode, an adhesion layer contacting the at least one source / drain electrode, a semiconductor layer, and at least one interface layer between the adhesion layer and the semiconductor layer. The at least one interface layer comprises a metal-doped oxide semiconductor material.

[0005] Another embodiment of the present disclosure relates to a transistor comprising at least one source / drain electrode, an adhesion layer contacting the at least one source / drain electrode, and a semiconductor layer, wherein at least one interface layer and at least one metal layer or metal oxide layer are located between the adhesion layer and the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are provided for illustrative purposes only. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a flow chart illustrating a first method for fabricating a transistor, according to some embodiments.

[0008] Figure 2 In the formation of Figure 1 A cross-sectional view of a wafer substrate prior to the transistor described in FIG.

[0009] Figure 3 is a cross-sectional view of the process steps used to form a transistor.

[0010] Figure 4is a cross-sectional view of the process steps used to form a transistor.

[0011] Figure 5 is a cross-sectional view of the process steps used to form a transistor.

[0012] Figure 6 is a cross-sectional view of the process steps used to form a transistor.

[0013] Figure 7 is a cross-sectional view of the process steps used to form a transistor.

[0014] Figure 8 is a cross-sectional view of the process steps used to form a transistor.

[0015] Figure 9 is a cross-sectional view of the process steps used to form a transistor.

[0016] Figure 10 is a cross-sectional view of the process steps used to form a transistor.

[0017] Figure 11 A cross-sectional view of the final transistor is shown, which is a bottom-gate transistor.

[0018] Figure 12 is a flow chart illustrating a second method for fabricating a transistor, according to some embodiments.

[0019] Figure 13 is a cross-sectional view of the process steps used to form a transistor.

[0020] Figure 14 is a cross-sectional view showing the final transistor.

[0021] Figure 15 is a flow chart illustrating a third method for fabricating a transistor according to some embodiments. In this method, a metal layer or a metal oxide layer is deposited between two interface layers.

[0022] Figure 16 is a cross-sectional view of the process steps used to form a transistor.

[0023] Figure 17 is a cross-sectional view showing the final transistor.

[0024] Figure 18 is a cross-sectional view of a transistor having a metal-doped interface layer.

[0025] Figure 19 is a flow chart illustrating a fourth method for fabricating a transistor, according to some embodiments.

[0026] Figure 20 In the formation of Figure 19A cross-sectional view of a wafer substrate before the transistor described in FIG.

[0027] Figure 21 is a cross-sectional view of the process steps used to form a transistor.

[0028] Figure 22 is a cross-sectional view of the process steps used to form a transistor.

[0029] Figure 23 is a cross-sectional view of the process steps used to form a transistor.

[0030] Figure 24 is a cross-sectional view of the process steps used to form a transistor.

[0031] Figure 25 is a cross-sectional view of the process steps used to form a transistor.

[0032] Figure 26 is a cross-sectional view of the process steps used to form a transistor.

[0033] Figure 27 is a cross-sectional view showing a first embodiment of the final transistor.

[0034] Figure 28 is a cross-sectional view showing a second embodiment of the final transistor.

[0035] Figure 29 is a cross-sectional view showing a third embodiment of the final transistor.

[0036] Figure 30 is a flow chart illustrating a fifth method for fabricating a transistor, according to some embodiments.

[0037] Figure 31 is a cross-sectional view of a process step in a first variation of a process for forming a transistor.

[0038] Figure 32 is a cross-sectional view of a process step in a first variation of a process for forming a transistor.

[0039] Figure 33 is a cross-sectional view of a process step in a second variation of a process for forming a transistor.

[0040] Figure 34 are cross-sectional views of process steps in a second variation of a process for forming a transistor.

[0041] Figure 35 are cross-sectional views of process steps in a second variation of a process for forming a transistor.

[0042] Figure 36 is a cross-sectional view showing a first embodiment of the final transistor.

[0043] Figure 37 is a cross-sectional view showing a second embodiment of the final transistor.

[0044] Figure 38 is a cross-sectional view showing a third embodiment of the final transistor. DETAILED DESCRIPTION

[0045] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0046] Additionally, for ease of description, spatially relative terms, such as "underlying," "below," "lower," "overlying," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of an element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0047] It should be understood that the numerical values herein include the same numerical values when reduced to the same number of significant figures and the numerical values that differ from the stated value by less than the experimental error of routine measurement techniques of the type described in this application to determine the value. All ranges disclosed herein include the stated endpoints.

[0048] The term "about" can be used to include any value that can vary without changing the basic function of the value. When used in conjunction with a range, "about" also discloses the range defined by the absolute values of the two endpoints, for example, "about 2 to about 4" also discloses a range of "from 2 to 4". The term "about" can mean plus or minus 10% of the specified digit.

[0049] The singular forms "a," "an," and "the" include plural referents unless the disclosure clearly dictates otherwise.

[0050] As used in the specification and claims, the term "comprising" may include the embodiments "consisting of" and "consisting essentially of." As used herein, the terms "comprise," "include," "have," "may," "contain," and variations thereof are intended to be open-ended transitional phrases, terms, or words that require the presence of specified components / steps and allow the presence of other components / steps. However, such descriptions should be interpreted as also describing a composition or process as "consisting of" and "consisting essentially of the listed components / steps," which allow the presence of only the specified components / steps and exclude other components / steps.

[0051] The present disclosure relates to transistors and other structures composed of different layers. When the terms "on" or "over" are used to refer to two different layers (including a substrate), they simply mean that one layer is on or above another layer. These terms do not require that the two layers are in direct contact with each other and allow other layers to be located between the two layers. For example, all layers of a transistor can be considered to be "on" a substrate even if they are not all in direct contact with the substrate. The term "directly" can be used to mean that two layers are in direct contact with each other without any layers in between.

[0052] The present disclosure relates to methods for producing transistors with improved thermal stability. In this regard, oxide semiconductor (OS) materials have high charge mobility, which allows for high-speed driving and low off-current (Ioff) for low energy consumption. Therefore, OS materials are often used as the semiconductor channel material in metal-oxide-semiconductor field-effect transistor (MOSFET) devices.

[0053] V t is the gate threshold voltage, I on is the on-state current, which is the maximum current when the drain voltage is constant. These two properties are generally inversely proportional to each other. V t and I on The trade-off between these two properties can be optimized to improve device performance, but both properties are susceptible to stress instability. t While enhancing I on One approach is to use hydrogen-doped or high-conductivity OS materials with a high indium (In) atomic percentage (at%).

[0054] However, UV exposure during photolithography can cause high-power damage, which can lead to the creation / ionization of photogenerated holes and oxygen vacancy states (Vo) in the bulk of the OS material and on its surface. Exposure to energies as low as 0.001 to 1 joule can cause heating issues at small pattern sizes. In addition, photoionization generates free electrons, and the transition from neutral to ionized Vo is accompanied by lattice relaxation, which increases the energy of ionized Vo. This can promote "defect generation" of atomic exchanges with weakly bound hydrogen, causing high delta-Vt instability, threshold voltage drift, and reduced reliability during operation.

[0055] Furthermore, oxide semiconductors such as indium oxide (InO) begin to dissolve at temperatures exceeding 300°C, which is easily reached during the various steps in forming integrated circuits. Indium oxide can react with the adhesive layer (also known as the glue layer) used to improve the bonding between transistor layers, resulting in an interface layer with high S / D contact resistance (Rcsd). This thermal instability also increases with the generation of more oxygen defects, leading to performance degradation and I on decline.

[0056] The present disclosure provides multiple methods for improving the thermal stability of transistors. In a first method, the interface layer between the source / drain electrodes and the semiconductor layer is formed of a material having a higher bond dissociation energy than indium oxide. In a second method, the interface layer between the source / drain electrodes and the semiconductor layer is formed of a metal-doped oxide semiconductor material. In a third method, a metal layer or a metal oxide layer is formed between the source / drain electrodes and the interface layer.

[0057] These methods increase the thermal stability and electrical conductivity of the transistor and can improve the functional interconnections in the transistor. This reduces the reaction with the adhesive layer and improves R csd It also improves the mobility of transistors and the resistance to chemical / physical damage.

[0058] Figure 1 is a flow chart illustrating a first method 100 for fabricating a transistor according to some embodiments of the present disclosure. Figures 2 to 11 The various steps of the first method are shown and the figures are discussed together.The figures are explained with reference to bottom-gate transistors.

[0059] Reference first Figure 2, receiving or providing a substrate 205. This figure illustrates the starting state of the substrate before transistor fabrication. The substrate is typically a wafer made of a semiconductor material. Such material may include silicon, for example in the form of crystalline Si or polycrystalline Si. The substrate may also be made of other base semiconductors, such as germanium or Al2O3 (sapphire), or may include compound semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In a specific embodiment, the wafer substrate is silicon.

[0060] Now, in Figure 1 In step 105, Figure 3 As shown, a gate electrode 210 is formed. This can be accomplished by forming an electrically insulating (or dielectric) layer, applying and patterning a photoresist layer to place the gate electrode at the desired location, etching the electrically insulating layer, depositing a conductive material to form the gate electrode, and then removing the photoresist layer. Note that Figure 3 The electrically insulating layer is not shown.

[0061] The electrically insulating layer is typically formed using thermal oxidation of a silicon substrate. However, other processes such as thermal oxidation, atomic layer deposition (ALD) or chemical vapor deposition (CVD), including plasma-enhanced ALD (PEALD) or plasma-enhanced chemical vapor deposition (PECVD), may also be used. The insulating layer may be formed of silicon dioxide (SiO2), but may also be made of a high-k dielectric material (having a dielectric constant greater than 3.9). Examples of suitable high-k dielectric materials include silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), silicon oxynitride (SiO x N y ), Hafnium Oxynitride (HfO x N y ) or zirconium oxynitride (ZrO x N y ) or hafnium silicate (ZrSi x O y ) or zirconium silicate (ZrSi x O y ) or silicon oxycarbonitride (SiC x O y N z), or hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta2O5), nitrides (such as silicon nitride), polysilicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), and borosilicate glass (BSG).

[0062] The photoresist layer can be applied by, for example, spin coating, spray coating, roller coating, dip coating or extrusion coating. Usually, in spin coating, the substrate is placed on a rotating platform, and the platform may include a vacuum chuck that fixes the substrate on a plate. The photoresist layer composition is then applied to the center of the substrate. The speed of the rotating platform is then increased, and the resist is evenly spread to the periphery of the substrate from the center of the substrate. The rotating speed of the fixed platform can then control the thickness of the final photoresist layer.

[0063] The photoresist layer can then be baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90° C. to about 110° C. Baking can be performed using a hot plate or an oven or similar equipment.

[0064] The photoresist layer is then patterned by being exposed to radiation. Radiation can be any wavelength of light that brings the desired mask pattern, although ultraviolet (" UV ") radiation is commonly used currently. UV radiation has a wavelength in the range of about 10 nanometers (" nanometers ") to about 400 nanometers, for example, from a KrF laser (248 nanometers) or an ArF laser (193 nanometers). In a specific embodiment, extreme ultraviolet (" EUV ") light with a wavelength of about 13.5 nanometers is used for patterning because this allows to obtain smaller feature sizes. This causes some parts of the photoresist layer to be exposed to radiation, while some parts of the photoresist layer are not exposed to radiation. Exposure causes some parts in the photoresist layer to become soluble in a developer, while other parts in the photoresist layer remain insoluble in a developer.

[0065] An additional resist bake step (post-exposure bake, or PEB) may be performed after exposure to radiation. This may, for example, help release acid leaving groups (ALGs) or other molecules of interest in the chemically amplified resist layer.

[0066] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solution. The soluble portion of the photoresist layer is dissolved and washed away during the development step, leaving behind the photoresist layer pattern. An example of a common developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developers can include 2-heptanone, n-butyl acetate, isoamylacetate, cyclohexanone, 5-methyl-2-hexanone, methyl-2-hydroxyisobutyrate, ethyl lactate or propylene glycol monomethyl ether acetate, n-pentyl acetate, n-butyl propionate, n-hexyl acetate, n-butylbutyrate, isobutyl butyrate, and methyl 2-hydroxyisobutyrate. The developer may be a 2,5-dimethyl-4-hexanone, a 2,6-dimethyl-4-heptanone, a propylisobutyrate, or an isobutyl propionate. In general, any suitable developer may be used. Sometimes, a post-development bake or "hard bake" may be performed to stabilize the developed photoresist layer pattern, thereby achieving optimal performance in subsequent steps.

[0067] Generally speaking, any etching step used herein may be performed using a wet etch, dry etch, or plasma etch process (eg, reactive ion etching (RIE) or inductively coupled plasma (ICP), or a combination thereof), as appropriate. The etching may be anisotropic. Depending on the material, the etchant may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), carbon fluoride, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2) or the like or combinations thereof in various proportions. For example, silicon dioxide can be wet-etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry-etched using various mixtures of CHF3, O2, CF4 and / or H2.

[0068] The gate electrode and any other conductive members may be deposited from any suitable conductive material. Such materials may include, for example, polycrystalline silicon (polysilicon); metals (e.g., Al, Zr, W, Ru, Co, Ni, Pt, Au, Rh, Pd, Bi, Ti, Ta, or the like); compositions such as TiN, WN, or TaN; or alloys thereof. For example, the material may be deposited by evaporation, sputtering, plating, ALD, CVD, or other suitable methods. Annealing may then be performed, in which the metal reacts with the exposed silicon below. Excess deposited material may be removed using chemical mechanical planarization (CMP) or selective etching. The gate electrode may have a thickness 215 of about 10 nanometers to about 100 nanometers, but values outside this range may also be acceptable.

[0069] Next, in Figure 1 In step 110, Figure 4As shown, a gate dielectric layer 220 is formed over the substrate. More specifically, the gate dielectric layer 220 is formed over the gate electrode 210. This can be formed in the same manner as described above. In a particular embodiment, the gate dielectric layer 220 is formed of a high-k dielectric material. In some embodiments of the present disclosure, the dielectric constant of the high-k dielectric material is higher than 5, or higher than 7, or higher than 10. Examples of high-k dielectric materials include those discussed previously. Other examples of suitable high-k dielectric materials may include Al2O3, HfO2, HfLaO, and HfSiO. Other suitable dielectric materials may include ferroelectric materials (whose dielectric constant may change with temperature) and oxide-nitride-oxide (ONO) films. The gate dielectric layer may have a thickness 225 of about 1 nanometer to about 10 nanometers, but values outside this range may also be acceptable.

[0070] Then, in Figure 1 step 115 and as Figure 5 shown, a semiconductor layer 230 is formed over the substrate. More specifically, the semiconductor layer 230 is formed over the gate dielectric layer 220. The semiconductor layer can be formed using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). In some specific embodiments, the semiconductor layer may have a thickness 233 of about 3 nanometers to about 20 nanometers, but values outside this range may also be acceptable.

[0071] In a particular embodiment, the semiconductor layer is formed of an oxide semiconductor. Oxide semiconductors generally provide high electrical conductivity, high electron mobility, and a wide bandgap. N-type and p-type oxide semiconductors are known. Examples of oxide semiconductors may include zinc oxide (ZnO), magnesium oxide (MgO), gadolinium oxide (GdO), gallium oxide (Ga2O3), tin oxide (SnO2), indium oxide (In2O3), indium tin oxide (ITO), cuprous oxide (Cu2O), and their binary, ternary, or quaternary combinations. In a more specific embodiment, the oxide semiconductor is InGaZnO (IGZO), whose general formula is In x Ga y Zn z O, where 0 < x ≤ 1; 0 < y ≤ 1; and 0 < z ≤ 1. InGaZnO is optionally doped with a metal and has the formula In x Ga y Zn zO:M, wherein M is Ti, Al, Ag, W, Ce, Sn, V or Sc.

[0072] Next, in Figure 1 In step 120, Figure 6 As shown, a channel cap layer 240 having a thickness 245 is formed over the substrate, more specifically, over the semiconductor layer 230. The cap layer can reduce the exposure of the semiconductor layer to hydrogen atoms, which are known to damage oxide semiconductors. The channel cap layer can be formed by PVD, CVD, or ALD or other suitable processes. Suitable materials may include oxides (such as silicon oxide); nitrides (such as silicon nitride); or another dielectric material. It should be noted that the presence of the channel cap layer is optional, and the presence of such a layer is not required to produce an operational transistor.

[0073] Then, in Figure 1 In step 125 and if Figure 7 As shown in FIG, the semiconductor layer 230 is patterned. This can be accomplished by applying and patterning a photoresist layer, etching to transfer the pattern to the semiconductor layer, and then removing the photoresist layer. As shown, the channel cap layer 240 has also been patterned.

[0074] Then, in Figure 1 In step 130, Figure 8 As shown in FIG, an interlayer dielectric (ILD) layer 250 is applied over the semiconductor layer 230. Suitable methods and materials for forming the dielectric layer have been previously described above with respect to step 105 and are also applicable to this processing step. As shown, the semiconductor layer 230 is encapsulated by the ILD layer 250.

[0075] Then, in Figure 1 In step 135 and Figure 9 As shown in FIG, etching is performed to form source / drain (S / D) regions 254 that contact the semiconductor layer 230. A photoresist layer is applied to the ILD layer and patterned, and each layer is etched using different etching parameters. As shown, the S / D region is a void volume extending through the ILD layer 250 and the channel cap layer 240.

[0076] Next, in Figure 1 In optional step 136, a lightly doped drain (LDD) region can be applied to the S / D region 254. Thus, the LDD region will be located between the semiconductor layer 230 and the final source / drain electrode. The LDD region reduces hot carrier effects that may occur in the saturation region of the transistor. Figure 8 or Figure 9 The lightly doped drain region is not shown.

[0077] Next, in Figure 1 In step 140 and as Figure 10 As shown in FIG, at least one interface layer 260 is applied to the S / D regions 254. As shown, the interface layer also covers the ILD layer 250. In some specific embodiments, each interface layer has a thickness 261 of about 0.5 nanometers to about 10 nanometers, although values outside this range may also be acceptable. Ideally, the interface layer is more conductive than the semiconductor layer to reduce the Schottky barrier height. The interface layer is a thin film and can be formed by ALD, PVD, CVD, or other suitable process (e.g., ex situ film deposition).

[0078] Then, in Figure 1 In the optional step 145 of Figure 10 As shown in FIG, a metal layer or metal oxide layer 262 is applied to the S / D regions 254. As shown, the metal layer or metal oxide layer also covers the ILD layer 250. In some specific embodiments, when a metal is used, the layer 262 has a thickness 263 of about 10 nanometers to about 100 nanometers, although values outside this range may also be acceptable. In some specific embodiments, when a metal oxide is used, the layer 262 has a thickness 263 of about 0.1 nanometers to about 20 nanometers, although values outside this range may also be acceptable. The metal layer or metal oxide layer is a thin film and can be formed by ALD, PVD, CVD or other suitable processes (e.g., ex-situ film deposition).

[0079] In an embodiment corresponding to the first method, the interfacial layer is formed from a semiconductor material having a bond dissociation energy (BDE) higher than that of indium oxide (In2O3). The BDE is the change in enthalpy that occurs when a bond between two elements in a compound breaks, measured in kJ / mol. The BDE of a particular bond may vary depending on the other elements present in the compound. For example, the BDE of the O-O bond in diatomic oxygen (O2) is 497.4 kJ / mol, but the BDE of the O-O bond in ozone (O3) is only approximately 102 kJ / mol.

[0080] The following table provides some BDEs for some bonds, sorted alphabetically on the left hand side by bonds and by BDE on the right hand side:

[0081] Bond BDE (kJ / mol) Bond BDE (kJ / mol) Cu-O 287.4 Zn-O 250 Ga-O 374 Cu-O 287.4 In-O 346 In-O 346 Ru-O 528 Ga-O 374 Sc-O 671.4 Sr-O 426.3 Sn-O 528 Ru-O 528

[0082] Bond BDE (kJ / mol) Bond BDE (kJ / mol) Sr-O 426.3 Sn-O 528 Ti-O 668 Ti-O 668 WO 720 Sc-O 671.4 Zn-O 250 WO 720

[0083] For the present disclosure, the BDE of a particular multi - oxide semiconductor material is measured as the BDE of each bond that can be formed between oxygen and other elements in the oxide semiconductor, weighted by their mole percentages in the dielectric layer. For example, the BDE of In1Ga1Zn1O can be the weighted average of the BDEs of InO, GaO, and ZnO, or (346 * 0.33)+(374 * 0.33)+(250 * 0.33)=320.1 kJ / mol. However, for In 0.5 Ga1Zn1O, the BDE is [(346 * 0.2)(374 * 0.4)(250 * 0.4)=318.8 kJ / mol.

[0084] Some examples of materials having a higher bond dissociation energy (BDE) than indium oxide (In2O3) include In x Sn t O, Ga y Zn z O, In x Ga y Zn z O, In x Sn t Zn z O, In x Sn t Ti w O or In x Sn t Ga y Zn z O, where 0 < t ≤ 1; 0 < w ≤ 1; 0 < x ≤ 1; 0 < y ≤ 1; and 0 < z ≤ 1.

[0085] In embodiments corresponding to the second method, the dielectric layer is formed of a metal - doped oxide semiconductor material. In some embodiments, the metal - doped oxide semiconductor material can include ZnO, In2O3, In x Sn t O, Ga y Zn z O, In x Ga y Zn z O, In x Sn t Zn z O, In x Sn t Ti w O or In x Sn t Ga y Zn zO, where 0 < t ≤ 1; 0 < w ≤ 1; 0 < x ≤ 1; 0 < y ≤ 1; and 0 < z ≤ 1. Some non-limiting examples of metal dopants that can be used with oxide semiconductor materials include TiO2, WO3, SnO2, RuO2, Sc q O, Sr r Cu s O, Sr r Ti w O, Mg, Ca, Ga, Hf, Al, Sn, V, Ti, Cd or Cu, where 0 < q ≤ 1; 0 < r ≤ 1; and 0 < s ≤ 1 and w is defined as above. The doping amount can be varied to obtain a desired balance between thermal reliability, carrier concentration, and the desired state (amorphous / crystalline). In some embodiments, doping can be performed such that the amount of metal atoms present is about 0.1 to about 20 at% of the interlayer. Doping can be carried out by ALD, CVD, PVD, or ion implantation. It is also worth noting that some metal-doped oxide semiconductor materials can also have a higher bond dissociation energy (BDE) than indium oxide (In2O3), or in other words, can also be consistent with the first method.

[0086] In embodiments corresponding to the third method, there is a metal layer or metal oxide layer 262, and it is formed between the source / drain electrodes and the interlayer. Suitable metals can include Mg, Ca, Ga, Hf, Al, Sn, V, Ti, Cd or Cu. Suitable metal oxides can include TiO2, WO3, SnO2, RuO2, Sc q O, Sr r Cu s O and Sr r Ti w O, where q, r, s, and w are defined as above. In these embodiments, the interlayer can be made of ZnO, In2O3, In x Sn t O, Ga y Zn z O, In x Ga y Zn z O, In x Sn t Zn z O, In x Sn t Ti w O or In x Sn t Ga y Zn z O, where t, w, x, y, and z are defined as above.

[0087] Next, in Figure 1 step 150 and as Figure 10 As shown in FIG, an adhesion layer 266 is applied to the S / D regions 254. As shown, the adhesion layer also covers the ILD layer 250. In some specific embodiments, the adhesion layer has a thickness 267 of about 1 nm to about 50 nm, although values outside this range may also be acceptable. Examples of materials suitable for the adhesion layer include metal nitrides, such as TaN, TiN, or WN; or alloys containing copper, aluminum, or titanium. The adhesion layer is a thin film and can be formed by ALD, PVD, CVD, or other suitable processes (e.g., ex-situ film deposition).

[0088] Next, in Figure 1 In step 155, Figure 10 As shown in , a conductive material 268 is deposited into the S / D region, which will be used to form the S / D electrodes. As shown, the conductive material also covers the ILD layer 250. The same methods and materials as described above for forming the gate electrode 210 are also applicable to the processing steps.

[0089] Then, in Figure 1 In step 160, Figure 11 As shown in , the device is planarized to separate and obtain two S / D electrodes 270 such that they are electrically connected only through the semiconductor layer 230. Planarization can be performed using, for example, a chemical mechanical planarization (CMP) process.

[0090] Typically, CMP is performed using a rotating platform with a polishing pad attached. The substrate is attached to the rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During the polishing process, both the polishing pad and carrier rotate, creating mechanical and chemical action on the wafer substrate surface, removing unwanted material and creating a highly flat surface. A post-CMP cleaning step is then performed using a rotating scrub brush and a cleaning solution to clean one or both sides of the wafer substrate.

[0091] Figure 11 An example of a final bottom gate transistor 201 is shown. Planarization removes various layers above the ILD layer 250. The semiconductor channel length 235 between the S / D electrodes 270 can be from about 1 nanometer to about 100 nanometers.

[0092] More generally, the gate dielectric layer 220 separates the gate electrode 210 from the source and drain electrodes 270. The semiconductor layer 230 bridges the S / D electrodes and contacts the gate dielectric layer 220. The semiconductor layer 230 can also be considered to separate the gate electrode 210 from the S / D electrodes 270. In other words, the S / D electrodes and the gate electrode are located on opposite sides of the semiconductor layer / gate dielectric layer.

[0093] Figure 12is a flow chart illustrating a second method 102 for fabricating a transistor, according to some embodiments of the present disclosure. Figure 13 and Figure 14 Specific steps in the second method are shown and these figures will be discussed together.These figures are described with reference to bottom-gate transistors.

[0094] Figure 12 Steps 105 to 135 of the method are Figure 1 Same as the first method described in Figures 2 to 9 Then the next Figure 12 Optional step 136, and as Figure 13 As shown in FIG, a lightly doped drain (LDD) region 280 is applied to the S / D region 254. The lightly doped drain region is thus located between the semiconductor layer 230 and the interface layer 260.

[0095] Then, in Figure 12 In step 138, a metal layer or metal oxide layer 262 is applied to the S / D region 254. Next, in step 140, at least one interface layer 260 is applied to the S / D region 254. Then, in step 150, an adhesion layer 266 is applied to the S / D region 254. Next, in step 155, a conductive material 268 is deposited into the S / D region to form the S / D electrode 270. These steps are performed using the same methods and materials as previously described. The resulting structure is shown in FIG. Figure 13 Likewise, layers 262, 260, and 266 cover the ILD layer 250. Figure 13 The structure and Figure 10 The main difference is that the positions of the interface layer 260 and the metal layer or metal oxide layer 262 are reversed. In addition, a lightly doped drain region 280 is shown.

[0096] Then, in Figure 12 In step 160, the device is planarized to obtain separated two S / D electrodes 270. This step is performed using the same methods and materials as previously described. Figure 14 The resulting structure is shown, which is another example of a bottom-gate transistor 202 .

[0097] Figure 15 is a flow chart illustrating a third method 104 for fabricating a transistor, according to some embodiments of the present disclosure. Figure 16 and Figure 17 Specific steps in the third method are shown and these figures will be discussed together.The figures are explained with reference to bottom gate transistors.

[0098] Figure 15 Steps 105 to 135 of the method are Figure 1 Same as the first method described in Figures 2 to 9 Then the next step is Figure 15 In optional step 136, a lightly doped drain (LDD) region 280 is applied to the S / D region 254. The lightly doped drain region is not shown here.

[0099] Next, in step 140 and with reference to Figure 16 , a first interface layer 260 is applied to the S / D region 254. Then, in step 145, a metal layer or metal oxide layer 262 is applied to the S / D region 254. Next, in step 148, a second interface layer 264 is applied to the S / D region 254. The second interface layer has a thickness 265. The thickness of the first interface layer and the second interface layer can independently be from about 0.25 nanometers to about 10 nanometers, but values outside this range may also be acceptable. It is contemplated that the two interface layers 260, 264 can be made of the same or different materials. These steps are performed using the same method as previously described.

[0100] Next, in Figure 15 In step 150, an adhesion layer 266 is applied to the S / D region 254. Then, in step 155, a conductive material 268 is deposited into the S / D region to form the S / D electrode 270. These steps are performed using the same methods and materials as previously described. The resulting structure is shown in FIG. Figure 16 Similarly, layers 262, 260, 264, and 266 cover the ILD layer 250. Figure 16 The structure and Figure 10 、 Figure 13 The main difference is that the metal layer or metal oxide layer 262 is located between the two interface layers, and there are three layers in total, while the non-metal layer or metal oxide layer has only two layers on a single side of the interface layer.

[0101] Then, in Figure 15 In step 160 , the device is planarized to obtain two separated S / D electrodes 270 . Figure 17 Another example of a final bottom-gate transistor 203 is shown.

[0102] Now refer to Figure 11 、 Figure 14 and Figure 17 structures comprising different interfacial layers 260, 264 and different metal layers or metal oxide layers 262 in different orders. In some embodiments, it is contemplated that the metal layer or metal oxide layer 262 may be used as a dopant for the oxide semiconductor material in the interfacial layers 260, 264 to obtain a metal-doped oxide semiconductor material. For example, the transistor may be annealed to promote diffusion of the metal layer or metal oxide layer 262 into the layers 260, 264, such as Figure 15The annealing can be performed at any time after the deposition of layers 260, 262, 264. The resulting transistor 204 is Figure 18 , where the interface layer 260 is a metal-doped oxide semiconductor material. The metal layer or metal oxide layer 262 can no longer be distinguished from the interface layer. Therefore, Figure 11 、 Figure 14 and Figure 17 The structure can also be regarded as an intermediate.

[0103] Figure 19 is a flow chart illustrating a fourth method 300 for fabricating a transistor according to some embodiments of the present disclosure. Figures 20 to 29 Specific steps of the fourth method are shown and these figures will be discussed together.The figures are explained with reference to top gate transistors.

[0104] Figure 20 The starting state of the substrate 205 before transistor fabrication is shown again.

[0105] Next, in Figure 19 In step 305, Figure 21 As shown in FIG, the substrate is etched to form S / D regions 254. The S / D regions are etched to a depth 255 sufficient to support layers that may be applied therein.

[0106] Then, in Figure 19 In step 310, Figure 22 As shown in , material is deposited into the S / D region to form an S / D electrode 270. The conductive material can be deposited using the methods and materials previously described. Alternatively, ion implantation can be used to form the S / D electrode in the portion of the wafer substrate located below the S / D region. In short, an ion implanter is used to implant atoms into the silicon lattice, changing the conductivity of the lattice at the implantation location. An ion implanter typically includes an ion source, a beam line, and a processing chamber. The ion source produces the desired ions (here, for example, Co, Ti, Ni, Pt, or Pb, depending on the desired N-type or P-type electrode). The beam line organizes the ions into a beam with high purity in terms of ion mass, energy, and species. The ion beam is then used to irradiate the wafer substrate in the processing chamber. The ion beam impacts the exposed area on the wafer substrate, and the ions can be implanted into the substrate as dopants at the desired depth.

[0107] Next, in Figure 19 In step 315 and continue to refer to Figure 22, an adhesive layer 266 is applied to the S / D region over the S / D electrodes 270. Next, in optional step 320, a first interface layer 260 is applied to the S / D region, and more specifically over the adhesive layer 266. Then, in step 325, a metal layer or metal oxide layer 262 is applied to the S / D region. Next, in optional step 330, a second interface layer 264 is applied to the S / D region. At least one interface layer is applied. Then, Figure 1 In optional step 335, lightly doped drain (LDD) regions may be applied to the S / D regions 254. These layers form thin films and fill the S / D regions 254. If desired, the device may be planarized to remove any material on the substrate, as shown in optional step 340.

[0108] Depending on which of these steps is performed, the resulting structure will have a metal or metal oxide layer 262 and one or two interface layers 260, 264, where the interface layers may be located on either side of the metal or metal oxide layer 262. Figure 22 In the embodiment of the present invention, the interface layer 264 is located on the metal layer or metal oxide layer 262, or in other words, the metal layer or metal oxide layer is located between the S / D electrodes and the interface layer. The lightly doped drain region is not shown here.

[0109] Next, in Figure 19 In step 345 and as Figure 23 As shown in FIG, a semiconductor layer 230 is formed over a substrate 205, specifically, over an S / D electrode 270. It should be noted that the S / D electrode should be completely covered by the semiconductor layer because exposure to oxygen may cause adhesion problems with the S / D electrode due to oxidation, especially when the S / D electrode is made of metal.

[0110] If necessary, Figure 19 In optional step 350, a channel cap layer may be formed over the semiconductor layer 230. The channel cap layer is not shown.

[0111] Next, in Figure 19 In step 355, Figure 24 As shown in FIG, the semiconductor layer 230 is patterned. The semiconductor layer 230 is patterned to contact the S / D electrodes 270. Next, Figure 19 In step 360, Figure 25 As shown in FIG, a gate dielectric layer 220 is formed in contact with the semiconductor layer 230. Then, Figure 19 In step 365, Figure 26 As shown in FIG, a gate electrode 210 is formed on the gate dielectric layer 220. Finally, Figure 19 In step 370, Figure 27As shown in FIG, an interlayer dielectric layer 250 is formed over the semiconductor layer 230. As shown, the ILD layer 250 is also etched to form a gap 252 that allows electrical contact with the gate electrode 210.

[0112] Figure 27 Also shown is one embodiment of a final top-gate transistor 206. It is worth noting that the semiconductor layer 230 need not completely cover the source / drain electrodes 270.

[0113] Figure 28 A second embodiment of the final top-gate transistor 207 is shown. Here, the interface layer 260 is below the metal layer or metal oxide layer 262, or in other words, the interface layer is located between the S / D electrodes and the metal layer or metal oxide layer.

[0114] Figure 29 A third embodiment of the final top-gate transistor 208 is shown. Here, a metal layer or metal oxide layer 262 is located between two interface layers 260,264.

[0115] Figure 30 is a flow chart illustrating a fifth method 302 for fabricating a transistor, according to some embodiments of the present disclosure. Figures 31 to 38 Specific steps of the fifth method are shown and these figures will be discussed together.The figures are explained with reference to top gate transistors.

[0116] Figure 30 The fifth method is Figure 19 The fourth method is different in that a dielectric layer is formed on the substrate before the transistor is made. The order of the previous steps can be carried out in different orders, such as Figure 30 The solid and dashed lines are shown in .

[0117] The first order follows the solid line. First, Figure 30 In step 306, a dielectric layer is formed over the substrate. This can be accomplished by thermal oxidation of the silicon substrate to form a silicon dioxide dielectric layer or by other suitable processes such as ALD, PVD, or CVD. Figure 30 In step 308, the dielectric layer is etched to form S / D regions 254. The resulting structure is shown in FIG. Figure 31 Next, at step 310, material is deposited into the S / D regions to form S / D electrodes 270. Conductive material may be deposited or ion implantation may be used to form the S / D electrodes in the portion of the wafer substrate located below the S / D regions, as previously described. If necessary, etching may be performed to remove excess material. The resulting structure is shown in FIG. Figure 32 middle.

[0118] The second sequence follows the dotted line. In this sequence, the S / D electrodes 270 are first formed in step 310. This can be done by ion implantation, or by metal deposition, annealing, and removal of excess material. The resulting structure is shown in FIG. Figure 33 Next, in Figure 30 In step 306, a dielectric layer 282 is formed over the substrate 205. The resulting structure is shown in FIG. Figure 34 Then, in step 308, the dielectric layer is etched to form the S / D regions 254. The resulting structure is shown in FIG. Figure 35 in (with Figure 32 same).

[0119] The remaining process steps 315 to 370 are Figure 19 Same as described in . Figures 36 to 38 Three different embodiments of top gate transistors 206, 207, 208 are shown. Figures 27 to 29 The main difference between the transistors is that the interface layers 260 , 264 and the metal layer or metal oxide layer 262 are located in the dielectric layer 282 instead of the substrate 205 .

[0120] It should be noted that in some applications, the gate electrode 210 is referred to as a write line, one S / D electrode 270 is referred to as a source line, and the other S / D electrode 270 is referred to as a bit line. These terms are interchangeable and should be considered as being used in the discussion of transistors herein. It should also be noted that although Figures 1 to 38 The formation of a single transistor on a wafer substrate is described, but during chip production, a large number of transistors are formed simultaneously on a wafer substrate. The present disclosure should be interpreted accordingly.

[0121] The resulting transistors can be used in a variety of different applications and systems. The transistors can be used in charge coupled devices (CCDs), complementary metal-oxide semiconductor (CMOS) image sensors, contact image sensors (CISs), and ambient light sensors (ALSs). Such sensors can be used in systems such as mobile phones, facial recognition systems, motion sensors in automotive applications, security applications, and energy efficiency. Random access memory uses transistors to read and write bits to memory cells (non-volatile or volatile). Transistors can be integrated with micro-electro-mechanical-system (MEMS) devices on a single chip. MEMS devices can include multiple elements formed from metal, polysilicon, dielectrics, and / or other materials. MEMS devices can include mechanical structures, electrical structures, or fluid structures.

[0122] The various interfacial / metal / metal oxide layers added between the S / D electrodes and the semiconductor layer offer several advantages. These layers improve thermal stability while maintaining high electrical conductivity. They improve the functional interconnection between the various components of the transistor. They reduce the Schottky barrier height. They reduce the S / D electrode (R csd ) and does not begin to decompose even after exposure to temperatures up to 400°C. This can make R csd They can increase the on-state current (I on ), thereby improving mobility. They also provide further protection against chemical or physical damage. Finally, the use of these layers reduces the number of oxygen vacancies and photogenerated holes that may occur in the semiconductor layer. This, in turn, reduces the potential variations in carrier concentration across the semiconductor layer. Carrier concentration is a key factor in maintaining high carrier mobility and high drive speed, which improves the reliability of the entire semiconductor device.

[0123] The improvements in thermal stability resulting from the use of various materials in the interface layer and the metal or metal oxide layer are described herein using a two-dimensional field effect transistor (FET). However, these disclosures are also applicable to three-dimensional transistors, such as fin FETs and gate-all-around transistors.

[0124] Thus, various embodiments of the present disclosure relate to a transistor including at least one source / drain electrode; a bonding layer contacting the at least one source / drain electrode; a semiconductor layer; and at least one interlayer located between the bonding layer and the semiconductor layer. The at least one interlayer comprises a material having a higher bond dissociation energy than indium oxide. In some embodiments, the at least one interlayer comprises a metal-doped oxide semiconductor material. In some embodiments, the oxide semiconductor material comprises ZnO, In2O3, In x Sn t O, Ga y Zn z O, In x Ga y Zn z O, In x Sn t Zn z O, In x Sn t Ti w O or In x Sn t Ga y Zn z O, where 0 < t ≤ 1; 0 < w ≤ 1; 0 < x ≤ 1; 0 < y ≤ 1; and 0 < z ≤ 1. In some embodiments, the oxide semiconductor material is doped with TiO2, WO3, SnO2, RuO2, Sc q O, Sr r Cu s O, Sr r Ti w O, Mg, Ca, Ga, Hf, Al, Sn, V, Ti, Cd or Cu, where 0 < q ≤ 1; 0 < r ≤ 1; 0 < s ≤ 1; and 0 < w ≤ 1. In some embodiments, the metal dopant of the metal-doped oxide semiconductor material comprises from about 0.1 to about 20 at% of the metal-doped oxide semiconductor material. In some embodiments, a metal layer or a metal oxide layer is located between the bonding layer and the semiconductor layer. In some embodiments, the metal oxide layer has a thickness of from about 0.1 nanometers to about 20 nanometers. In some embodiments, the transistor has two interlayers in total, and the metal layer or the metal oxide layer is located between the two interlayers. In some embodiments, the metal oxide layer comprises TiO2, WO3, SnO2, RuO2, Sc q O, Sr r Cu s O or Sr r Ti wO, where 0 < q ≤ 1; 0 < r ≤ 1; 0 < s ≤ 1; and 0 < w ≤ 1. In some embodiments, the metal layer has a thickness of from about 10 nanometers to about 100 nanometers. In some embodiments, the metal layer comprises Mg, Ca, Ga, Hf, Al, Sn, V, Ti, Cd, or Cu. In some embodiments, at least one interlayer comprises In x Sn t O, Ga y Zn z O, In x Ga y Zn z O, In x Sn t Zn z O, In x Sn t Ti w O or In x Sn t Ga y Zn z O, where 0 < t ≤ 1; 0 < w ≤ 1; 0 < x ≤ 1; 0 < y ≤ 1; and 0 < z ≤ 1. In some embodiments, the lightly doped drain region is between at least one interlayer and the semiconductor layer. In some embodiments, at least one interlayer has a thickness of from about 0.5 nanometers to about 10 nanometers.

[0125] Other embodiments of the present disclosure relate to a transistor comprising at least one source / drain electrode; a bonding layer contacting at least one source / drain electrode; a semiconductor layer; and at least one interlayer between the bonding layer and the semiconductor layer. At least one interlayer comprises a metal-doped oxide semiconductor material. In some embodiments, the metal-doped oxide semiconductor material has a higher bond dissociation energy than indium oxide. In some embodiments, a metal layer or a metal oxide layer is between the bonding layer and the semiconductor layer.

[0126] Another embodiment of the present disclosure relates to a transistor comprising at least one source / drain electrode; a bonding layer contacting at least one source / drain electrode; and a semiconductor layer. At least one interlayer and at least one metal layer or metal oxide layer are between the bonding layer and the semiconductor layer. In some embodiments, the transistor has a total of two interlayers, and at least one metal layer or metal oxide layer is between the two interlayers. In some embodiments, at least one interlayer directly contacts at least one metal layer or metal oxide layer.

[0127] Also disclosed herein is a method for manufacturing a transistor. A semiconductor layer is formed on a substrate. Etching is performed to form at least one S / D region in contact with the semiconductor layer. At least one interface layer is applied to the at least one S / D region. An adhesion layer is applied to the at least one S / D region. A conductive material is deposited into the at least one S / D region to form an S / D electrode. In some cases, at least one interface layer comprises a material having a higher bond dissociation energy than indium oxide. In other cases, at least one interface layer comprises a metal-doped oxide semiconductor material. In still other cases, a metal layer or a metal oxide layer is also present adjacent to the interface layer. In yet other embodiments, the substrate is annealed such that the metal layer or the metal oxide layer dopes the semiconductor layer.

[0128] The order of these steps may vary, depending, for example, on whether a bottom-gate or top-gate transistor is being fabricated.

[0129] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A transistor, characterized in that: include: at least one source / drain electrode; an adhesive layer contacting the at least one source / drain electrode; semiconductor layer; as well as at least one interface layer located between the adhesive layer and the semiconductor layer; The at least one interface layer is made of a material having a bond dissociation energy higher than that of indium oxide. 2 . The transistor according to claim 1 , wherein the at least one interface layer is a metal-doped oxide semiconductor material. 3 . The transistor according to claim 1 , further comprising a metal layer or a metal oxide layer located between the adhesive layer and the semiconductor layer. 4 . The transistor according to claim 1 , further comprising a lightly doped drain region between the at least one interface layer and the semiconductor layer. 5 . The transistor of claim 1 , wherein the at least one interface layer has a thickness of 0.5 nm to 10 nm.

6. A transistor, characterized in that: include: at least one source / drain electrode; an adhesive layer contacting the at least one source / drain electrode; semiconductor layer; as well as at least one interface layer located between the adhesive layer and the semiconductor layer; The at least one interface layer is a metal-doped oxide semiconductor material. 7 . The transistor according to claim 6 , further comprising a metal layer or a metal oxide layer located between the adhesive layer and the semiconductor layer.

8. A transistor, characterized in that: include: at least one source / drain electrode; an adhesive layer contacting the at least one source / drain electrode; semiconductor layer; at least one interface layer located between the adhesive layer and the semiconductor layer; as well as At least one metal layer or metal oxide layer is located between the adhesive layer and the semiconductor layer.

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