Nanostructured field effect transistor

Abstract

The nanostructure field effect transistor includes a source / drain region, a semiconductor nanostructure, an isolation region, a protection layer, a gate structure, and a spacer. The semiconductor nanostructure is adjacent to the source / drain region. The isolation region is adjacent to the semiconductor nanostructure. The protective layer is on the isolation region, and the protective layer is a carbon-containing dielectric layer. A gate structure is on the protective layer and around the semiconductor nanostructure. The spacer is between the gate structure and the source / drain region and electrically isolates the gate structure from the source / drain region.

Description

Technical Field

[0001] The present disclosure relates to a nanostructured field effect transistor. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. They are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate; and using lithography to pattern the various material layers to form circuit components and elements.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems that need to be solved arise. Utility Model Content

[0004] In some embodiments, a nanostructure field-effect transistor includes: source / drain regions, a semiconductor nanostructure, an isolation region, a protective layer, a gate structure, and a spacer. The semiconductor nanostructure is adjacent to the source / drain regions. The isolation region is adjacent to the semiconductor nanostructure. The protective layer is on the isolation region and is a carbon-containing dielectric layer. The gate structure is on the protective layer and surrounds the semiconductor nanostructure. The spacer is between the gate structure and the source / drain regions, electrically isolating the gate structure from the source / drain regions.

[0005] In some embodiments, a nanostructure field-effect transistor includes: source / drain regions, a semiconductor nanostructure, an isolation region, a gate structure, a protective layer, and a spacer. The semiconductor nanostructure is adjacent to the source / drain regions. The isolation region is adjacent to the semiconductor nanostructure. The gate structure surrounds the semiconductor nanostructure. The protective layer is located above the isolation region and below the gate structure, and the protective layer is a carbon-containing dielectric layer. The spacer is located between the gate structure and the source / drain regions, and the spacer physically contacts the semiconductor nanostructure.

[0006] In some embodiments, a nanostructure field-effect transistor includes: source / drain regions, a semiconductor nanostructure, an isolation region, a protective layer, a gate structure, and an internal spacer. The semiconductor nanostructure is adjacent to the source / drain regions. The isolation region is adjacent to the semiconductor nanostructure. The protective layer is on the isolation region and is a carbon-containing dielectric layer that is not located on the semiconductor nanostructure. The gate structure is on the protective layer and surrounds the semiconductor nanostructure. The internal spacer is between the gate structure and the source / drain regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of this disclosure are as follows: Figure 1The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a nanostructure field-effect transistor (nanostructure-FET) is shown in a three-dimensional view according to some embodiments;

[0009] Figures 2 to 20B is a diagram of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments;

[0010] Figures 21A to 21B is a diagram of a nanostructure FET according to some other embodiments;

[0011] Figures 22A to 23B is a diagram of an intermediate stage in the fabrication of a nanostructured FET according to some other embodiments.

[0012]

Explanation of symbols

[0013] 50:Substrate

[0014] 50N: n-type region

[0015] 50P: p-type region

[0016] 52: Multi-layer stacking

[0017] 54: dummy layer

[0018] 56: semiconductor layer

[0019] 62:Semiconductor fins

[0020] 64: Nanostructure

[0021] 66: Nanostructure

[0022] 68: Insulation material

[0023] 70: Isolation Zone

[0024] 72: dummy dielectric layer

[0025] 74: dummy gate layer

[0026] 76: Mask layer

[0027] 82: Virtual dielectric

[0028] 84: dummy gate

[0029] 86:Mask

[0030] 92: Gate spacer

[0031] 94: Fin spacer

[0032] 96: Source / drain recess

[0033] 98: Internal spacer

[0034] 102: epitaxial source / drain region

[0035] 112: Contact Etch Stop Layer (CESL)

[0036] 114: First interlayer dielectric (ILD)

[0037] 116: Interlayer dielectric (ILD) mask

[0038] 122: Etching process

[0039] 124: Treatment process

[0040] 126: Suppression layer

[0041] 128: Protective layer

[0042] 130: Opening

[0043] 132: Gate dielectric

[0044] 134: Gate electrode

[0045] 142: Etch stop layer (ESL)

[0046] 144: Second interlayer dielectric (ILD)

[0047] 146: Gate contact

[0048] 148: Source / drain contacts

[0049] 150:Metal semiconductor alloy area DETAILED DESCRIPTION

[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0051] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0052] According to various embodiments, during the gate replacement process, a protective layer is selectively deposited on the isolation region but not on the exposed semiconductor nanostructure. Specifically, after the dummy gate is removed to expose the isolation region and the semiconductor nanostructure, the protective layer is selectively deposited on the isolation region. A dangling amine group or an inhibitory layer is selectively formed on the top surface of the semiconductor nanostructure, such an inhibitory layer inhibits the deposition of the protective layer, so that the protective layer is selectively deposited on the isolation region but not on the semiconductor nanostructure. The protective layer protects the isolation region from etching loss during the process for removing the dummy nanostructure to expose the top and bottom surfaces of the semiconductor nanostructure. Because the protective layer is not formed on the semiconductor nanostructure, the top surface of the upper semiconductor nanostructure can be more easily exposed in subsequent processing before the gate structure is formed around the semiconductor nanostructure. Over-etching of the semiconductor nanostructure can therefore be avoided, thereby improving device reliability.

[0053] Figure 1 Examples of nanostructured FETs (eg, nanowire FETs, nanosheet FETs, multi-bridge channel (MBC) FETs, nanoribbon FETs, gate-all-around (GAA) FETs, or the like) according to some embodiments are shown. Figure 1 A three-dimensional view in which some features of the nanostructured FET are omitted for clarity of illustration.

[0054] The nanostructure FET includes a semiconductor nanostructure 66 (e.g., a nanosheet, nanowire, or the like) above a semiconductor fin 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the semiconductor nanostructure 66 is a semiconductor feature that serves as the channel region of the nanostructure FET. An isolation region 70, such as a shallow trench isolation (STI) region, is disposed between adjacent semiconductor fins 62. These fins 62 may protrude above and between adjacent isolation regions 70. The semiconductor nanostructure 66 is disposed above and between adjacent isolation regions 70. Although the isolation region 70 is described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the semiconductor fin 62 is depicted as a single, continuous material with the substrate 50, the bottom portion of the semiconductor fin 62 and / or the substrate 50 may comprise a single material or multiple materials.

[0055] A gate dielectric 132 is formed over the top surface of the semiconductor fin 62 and along the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 66. A gate electrode 134 is formed over the gate dielectric 132. Source / drain regions 102 are disposed on the semiconductor fin 62 on opposite sides of the gate dielectric 132 and the gate electrode 134. The source / drain regions 102 may be referred to individually or collectively as a source or a drain, depending on the context. The source / drain regions 102 may be shared between various semiconductor nanostructures 66. For example, adjacent source / drain regions 102 may be electrically connected, such as by merging the source / drain regions 102 through epitaxial growth or by coupling the source / drain regions 102 to the same contact. An interlayer dielectric (ILD) 114 is formed over the source / drain regions 102.

[0056] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 134. Cross section BB' is perpendicular to cross section AA' and is along the longitudinal axis of semiconductor fin 62 of the nanostructure FET and in the direction of current flow between source / drain regions 102 of the nanostructure FET. Cross section CC' is parallel to cross section AA' and extends through source / drain regions 102 of the nanostructure FET. Subsequent figures refer to these reference cross sections for clarity.

[0057] Figures 2 to 20B is a diagram of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0058] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 and Figure 6 To illustrate and Figure 1 A 3D view similar to the 3D view in .

[0059] Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A and Figure 20A The diagram is along Figure 1 A cross-sectional view of a similar cross section to the reference cross section AA'. Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B and Figure 20B The diagram is along Figure 1 Cross-sectional view of a similar cross section as in the reference cross section BB'. Figure 10C and Figure 10D The diagram is along Figure 1 A cross-sectional view of a cross-section similar to the reference cross-section C-C' in FIG. The nanostructured FET is shown in FIG. FIG. 20A to FIG. 20B middle.

[0060] exist Figure 2In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, indium aluminum arsenide, gallium indium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0061] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanostructure FET. The n-type region 50N may or may not be physically separated from the p-type region 50P (not shown), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P may be provided.

[0062] A multilayer stack 52 is formed over substrate 50. Multilayer stack 52 includes alternating dummy layers 54 and semiconductor layers 56. In the illustrated embodiment, and as described in more detail subsequently, dummy layers 54 are removed and semiconductor layers 56 are patterned to form channel regions for nanostructure FETs in n-type and p-type regions 50N and 50P.

[0063] Dummy layer 54 is formed from a dummy material, and semiconductor layer 56 is formed from one or more semiconductor materials. The dummy material of dummy layer 54 may be a dielectric material or a semiconductor material. The dummy material may be silicon oxide, silicon oxynitride, silicon oxycarbonitride, or the like. The semiconductor materials may each be selected from candidate semiconductor materials of substrate 50. In some embodiments, semiconductor layer 56 in n-type region 50N and p-type region 50P is formed from the same semiconductor material, which may be suitable for both n-type and p-type devices. In some embodiments, the dummy material of dummy layer 54 is silicon-germanium or silicon oxide, and the semiconductor material of semiconductor layer 56 is silicon. Therefore, the channel regions in both n-type region 50N and p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously. In another embodiment, semiconductor layer 56 in p-type region 50P is formed from a first semiconductor material, while semiconductor layer 56 in n-type region 50N is formed from a second semiconductor material. The first semiconductor material may be suitable for p-type devices, such as silicon germanium (eg, Si x Ge 1-x , where x can be in the range of 0 to 1), pure germanium, or the like. The second semiconductor material can be suitable for n-type devices, such as silicon, silicon carbide, or the like. The dummy material of dummy layer 54 has a high etch selectivity with respect to the semiconductor material of semiconductor layer 56. Therefore, the dummy material of dummy layer 54 can be removed at a faster rate than the semiconductor material of semiconductor layer 56 during subsequent processing.

[0064] The multilayer stack 52 is shown as including a specific number of dummy layers 54 and a specific number of semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of dummy layers 54 and semiconductor layers 56. Each of the layers of the multilayer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like.

[0065] exist Figure 3In the embodiment of the present invention, semiconductor fins 62 are formed in substrate 50, and nanostructures 64 and 66 (including dummy nanostructures 64 and semiconductor nanostructures 66) are formed in multilayer stack 52. In some embodiments, nanostructures 64 and 66 and semiconductor fins 62 can be formed in multilayer stack 52 and substrate 50 by etching trenches in multilayer stack 52 and substrate 50, respectively. The etching process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching process can be anisotropic. Forming nanostructures 64 and 66 by etching multilayer stack 52 can define dummy nanostructures 64 from dummy layer 54 and can define semiconductor nanostructures 66 from semiconductor layer 56.

[0066] The semiconductor fins 62 and nanostructures 64, 66 can be patterned by any suitable method. For example, the semiconductor fins 62 and nanostructures 64, 66 can be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. Generally speaking, double patterning or multiple patterning processes combine optical lithography and self-alignment processes, thereby allowing patterns to be produced that have, for example, a spacing that is smaller than that otherwise obtained using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the semiconductor fins 62 and nanostructures 64, 66.

[0067] Nanostructures 64, 66 are shown as having substantially equal widths in both n-type region 50N and p-type region 50P. In some embodiments, the widths of nanostructures 64, 66 in n-type region 50N may be different from the widths of nanostructures 64, 66 in p-type region 50P. Furthermore, while semiconductor fin 62 and each of nanostructures 64, 66 are shown as having a constant width throughout, in other embodiments, semiconductor fin 62 and / or nanostructures 64, 66 may have tapered sidewalls such that the width of each of semiconductor fin 62 and / or nanostructures 64, 66 continuously increases in a direction toward substrate 50. In such embodiments, each of nanostructures 64, 66 may have different widths and be trapezoidal in shape.

[0068] exist Figure 4Insulating material 68 is formed over substrate 50 and between semiconductor fin 62 and nanostructures 64 and 66. Insulating material 68 may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. Insulating material 68 is formed from a non-carbon dielectric material. In some embodiments, insulating material 68 includes silicon oxide formed by an FCVD process. Once insulating material 68 is formed, an annealing process may be performed. Although insulating material 68 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of substrate 50, semiconductor fin 62, and nanostructures 64 and 66. Thereafter, a filler material, such as one of the previously described insulating materials, may be formed over the liner.

[0069] Insulating material 68 may be deposited over semiconductor fins 62 and nanostructures 64 and 66 such that excess insulating material 68 covers nanostructures 64 and 66. A removal process is then applied to insulating material 68 to remove excess insulating material 68 over nanostructures 64 and 66. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes nanostructures 64 and 66 such that the top surfaces of nanostructures 64 and 66 and insulating material 68 are substantially coplanar (within process variations) after the planarization process is completed.

[0070] exist Figure 5 , insulating material 68 is recessed to form isolation region 70. Isolation region 70 is adjacent to semiconductor fin 62. Insulating material 68 is recessed so that upper portions of semiconductor fin 62 and / or nanostructures 64, 66 protrude from between adjacent isolation regions 70. Upper portions of semiconductor fin 62 and / or nanostructures 64, 66 are above isolation region 70. Additionally, the top surface of isolation region 70 may have a flat surface, as shown, a raised surface, a recessed surface (such as a dished shape), or a combination thereof. The top surface of isolation region 70 may be formed to be flat, raised, and / or recessed by appropriate etching. Isolation region 70 may be recessed using any acceptable etching process, such as an etching process that is selective for the material of insulating material 68 (e.g., selectively etches the material of insulating material 68 at a faster rate than the material of semiconductor fin 62 and nanostructures 64, 66). For example, an oxide removal process using, for example, dilute hydrofluoric (dHF) acid may be used. In some embodiments, the etch is anisotropic.

[0071] The process previously described is only one example of how the semiconductor fins 62 and nanostructures 64, 66 may be formed. In some embodiments, the semiconductor fins 62 and / or nanostructures 64, 66 may be formed using a masking and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the semiconductor fins 62 and / or nanostructures 64, 66. The epitaxial structure may include alternating semiconductor materials, such as dummy material and semiconductor material, as previously described. In some embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material may be in situ doped during growth, which may mitigate prior and / or subsequent implantation, although both in situ and implantation doping may be used together.

[0072] In addition, appropriate wells (not shown separately) may be formed in the semiconductor fins 62 and / or nanostructures 64, 66. In embodiments having different well types, different implantation steps for the n-type region 50N and the p-type region 50P may be achieved using photoresist or other masks (not shown separately). For example, a photoresist may be formed in the n-type region 50N and the p-type region 50P over the semiconductor fins 62, nanostructures 64, 66, and isolation regions 70. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity may be implanted in the region up to a range of 10 13 atoms / cm 3 to 10 14 atoms / cm 3 After implantation, the photoresist is removed, such as by any acceptable ashing process.

[0073] After or before implanting the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the semiconductor fins 62, nanostructures 64, 66, and isolation regions 70 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be implanted in the region up to a range of 10 13 atoms / cm 3 to 10 14 atoms / cm3 After implantation, the photoresist may be removed, such as by any acceptable ashing process.

[0074] After implantation of n-type region 50N and p-type region 50P, an annealing process may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments where the epitaxial structure is grown epitaxially, the epitaxially grown material may be doped in situ during growth, which may mitigate implantation, although both in situ and implanted doping may be used together.

[0075] exist Figure 6 In the embodiment of the present invention, a dummy dielectric layer 72 is formed over the semiconductor fins 62 and / or nanostructures 64 and 66. The dummy dielectric layer 72 may be formed of silicon oxide, silicon nitride, combinations thereof, or the like, which may be deposited or thermally grown according to accepted techniques. A dummy gate layer 74 is formed over the dummy dielectric layer 72. The dummy gate layer 74 may be deposited over the dummy dielectric layer 72 and then planarized, such as by a chemical mechanical polish (CMP) process. The dummy gate layer 74 may be formed of a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The material of the dummy gate layer 74 may be deposited by CVD, physical vapor deposition (PVD), sputtering, or other techniques for depositing the selected material. Dummy gate layer 74 may be formed from other materials that have high etch selectivity to insulating materials (e.g., isolation region 70 and / or dummy dielectric layer 72). A mask layer 76 may be formed over dummy gate layer 74. Mask layer 76 may be made of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across n-type region 50N and p-type region 50P. In the illustrated embodiment, dummy dielectric layer 72 covers isolation region 70, extending between dummy gate layer 74 and isolation region 70. In another embodiment, dummy dielectric layer 72 only covers semiconductor fins 62 and / or nanostructures 64 and 66.

[0076] 7A to 20B Various additional steps in fabricating an embodiment device are illustrated. 7A to 20B The features in either n-type region 50N or p-type region 50P are shown. For example, the structure shown can be applied to both n-type region 50N and p-type region 50P. The differences in the structures of n-type region 50N and p-type region 50P, if any, will be explained in describing each figure.

[0077] exist 7A to 7B , mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 can then be transferred to dummy gate layer 74 and to dummy dielectric layer 72 to form dummy gates 84 and dummy dielectric 82, respectively. Dummy gates 84 cover the respective channel regions of nanostructures 64 and 66. The pattern of mask 86 can be used to physically separate each of dummy gates 84 from adjacent dummy gates 84. Dummy gates 84 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of respective semiconductor fins 62. Mask 86 can be removed after patterning, such as by any acceptable etching technique, as desired.

[0078] exist Figures 8A to 8B In FIG. 1 , gate spacers 92 are formed over nanostructures 64, 66 and isolation regions 70, on exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacers 92 can be formed by conformally forming one or more dielectric materials and then etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride carbide, or the like, which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other insulating materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, the like, or a combination thereof, may be performed to pattern the dielectric material. The etching may be anisotropic. When etched, the dielectric material has portions remaining on the sidewalls of dummy gate 84 (thus, forming gate spacers 92). As described in more detail below, the dielectric material, when etched, may also have portions remaining on the sidewalls of the semiconductor fins 62 and / or nanostructures 64, 66 (thus forming fin spacers 94, see FIG. 10C to FIG. 10D After etching, the fin spacers 94 and / or gate spacers 92 may have straight sidewalls (as shown), or may have curved sidewalls (not separately shown).

[0079] Additionally, implantation for lightly doped source / drain (LDD) regions (not separately shown) may be performed. LDD implantation may be performed before forming gate spacers 92. In embodiments with different device types, similar to the well implantation described previously, a mask, such as a photoresist, may be formed over n-type region 50N, while exposing p-type region 50P, and an appropriate type (e.g., p-type) impurity may be implanted into semiconductor fins 62 and nanostructures 64 and 66 exposed in p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over p-type region 50P, while exposing n-type region 50N, and an appropriate type (e.g., n-type) impurity may be implanted into semiconductor fins 62 and nanostructures 64 and 66 exposed in n-type region 50N. The mask may then be removed. The n-type impurity may include any of the n-type impurities previously discussed, and the p-type impurity may include any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a 15 atoms / cm 3 to 10 19 atoms / cm 3 Annealing can be used to repair implant damage and activate implanted impurities.

[0080] It should be noted that the previous disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used, additional spacers may be formed and removed, and / or the like. Furthermore, n-type devices and p-type devices may be formed using different structures and steps.

[0081] Source / drain recesses 96 are patterned in the semiconductor fin 62, nanostructures 64, 66, and substrate 50. Epitaxial source / drain regions will subsequently be formed in the source / drain recesses 96. The source / drain recesses 96 may extend through the nanostructures 64, 66 and into the substrate 50. In some embodiments, the semiconductor fin 62 may be etched such that the bottom surface of the source / drain recesses 96 is disposed below the top surface of the isolation region 70. The source / drain recesses 96 may be formed by etching the semiconductor fin 62, nanostructures 64, 66, and substrate 50 using an anisotropic etching process, such as RIE, NBE, or the like. The gate spacers 92 and the dummy gate 84 mask portions of the semiconductor fin 62, nanostructures 64, 66, and substrate 50 during the etching process used to form the source / drain recesses 96. A single etching process or multiple etching processes may be used to etch each layer of nanostructures 64, 66 and / or semiconductor fins 62. A timed etching process may be used to stop etching of source / drain recesses 96 after they reach a desired depth.

[0082] exist Figures 9A to 9B In the embodiment of the present invention, internal spacers 98 are formed on the sidewalls of the remaining portions of dummy nanostructure 64, such as those sidewalls exposed by source / drain recess 96. As will be described in greater detail later, source / drain regions will be formed in source / drain recess 96, and dummy nanostructure 64 will subsequently be replaced with corresponding gate structures. Internal spacers 98 serve as isolation features between the subsequently formed source / drain regions and the subsequently formed gate structures. In addition, internal spacers 98 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as the etching process used to subsequently remove dummy nanostructure 64.

[0083] As an example for forming internal spacers 98, source / drain recesses 96 may be laterally expanded. Specifically, portions of the sidewalls of dummy nanostructures 64 exposed by source / drain recesses 96 may be recessed to form sidewall recesses. Although the sidewalls of dummy nanostructures 64 are shown as straight, the sidewalls may be concave or convex. The sidewalls may be recessed using any acceptable etching process, such as an etching process that is selective for the material of dummy nanostructures 64 (e.g., selectively etches the material of dummy nanostructures 64 at a faster rate than the material of semiconductor nanostructures 66). The etching process may be isotropic. For example, when semiconductor nanostructures 66 are formed of silicon and dummy nanostructures 64 are formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In some embodiments, the same etching process may be performed sequentially to both form the source / drain recesses 96 and recess the sidewalls of the dummy nanostructures 64. An insulating material may then be conformally formed in the source / drain recesses 96 (including the sidewall recesses) and subsequently etched. The insulating material may be silicon nitride or silicon oxynitride, although any suitable material may be utilized, such as a low-dielectric constant (low-k) material having a k value of less than approximately 3.5. The insulating material may be formed by a deposition process such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch such as RIE, NBE, or the like. When etched, the insulating material has a portion remaining in the sidewall recesses (thus forming the inner spacers 98). Although the outer sidewalls of the inner spacers 98 are shown flush with the sidewalls of the semiconductor nanostructures 66, the outer sidewalls of the inner spacers 98 may extend beyond the sidewalls of the semiconductor nanostructures 66 or be recessed from these sidewalls. In other words, the inner spacer 98 may partially fill, completely fill, or overfill the sidewall recess. Additionally, although the sidewalls of the inner spacer 98 are illustrated as being straight, the sidewalls of the inner spacer 98 may be concave or convex.

[0084] exist FIG. 10A to FIG. 10B In the embodiment of the present invention, epitaxial source / drain regions 102 are formed in the source / drain recesses 96. In some embodiments, the epitaxial source / drain regions 102 exert stress on the respective channel regions of the semiconductor nanostructures 66, thereby improving performance. The epitaxial source / drain regions 102 are formed in the source / drain recesses 96 such that each dummy gate 84 is disposed between respective adjacent pairs of epitaxial source / drain regions 102. In some embodiments, gate spacers 92 are used to separate the epitaxial source / drain regions 102 from the dummy gates 84, and inner spacers 98 are used to separate the epitaxial source / drain regions 102 from the dummy nanostructures 64 by an appropriate lateral distance so that the epitaxial source / drain regions 102 do not short-circuit with the subsequently formed gate of the resulting nanostructure FET.

[0085] Epitaxial source / drain regions 102 in n-type region 50N can be formed by masking p-type region 50P. Epitaxial source / drain regions 102 are then epitaxially grown in source / drain recesses 96 in n-type region 50N. Epitaxial source / drain regions 102 in n-type region 50N may comprise any acceptable material suitable for n-type nanostructure FETs. For example, if semiconductor nanostructure 66 is formed of silicon, epitaxial source / drain regions 102 in n-type region 50N may comprise a material that imparts tensile strain on semiconductor nanostructure 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. Epitaxial source / drain regions 102 in n-type region 50N may be referred to as "n-type source / drain regions." Epitaxial source / drain regions 102 may have surfaces elevated from the respective upper surfaces of nanostructures 64, 66 and may have facets.

[0086] Epitaxial source / drain regions 102 in p-type region 50P can be formed by masking n-type region 50N. Epitaxial source / drain regions 102 are then epitaxially grown in source / drain recesses 96 in p-type region 50P. Epitaxial source / drain regions 102 in p-type region 50P may comprise any acceptable material suitable for a p-type nanostructure FET. For example, if semiconductor nanostructure 66 is formed of silicon, epitaxial source / drain regions 102 in p-type region 50P may comprise a material that imposes compressive strain on dummy nanostructure 64, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. Epitaxial source / drain regions 102 in p-type region 50P may be referred to as "p-type source / drain regions." Epitaxial source / drain regions 102 may also have surfaces elevated from the respective surfaces of nanostructures 64, 66 and may be faceted.

[0087] Similar to the process previously discussed for forming lightly doped source / drain regions, the epitaxial source / drain regions 102, nanostructures 64, 66, and / or semiconductor fins 62 may be implanted with dopants to form the source / drain regions, followed by annealing. 19 atoms / cm 3 with 10 21 atoms / cm 3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 102 may be in-situ doped during growth.

[0088] As a result of the epitaxial process used to form epitaxial source / drain regions 102, the upper surface of epitaxial source / drain regions 102 has facets that extend laterally outward beyond the sidewalls of nanostructures 64, 66. In some embodiments, these facets allow adjacent epitaxial source / drain regions 102 of the same nanostructure FET to merge, e.g., Figure 10C In other embodiments, adjacent epitaxial source / drain regions 102 remain separated after the epitaxial process is completed, as shown by Figure 10D In the illustrated embodiment, fin spacers 94 are formed on the top surface of isolation region 70, thereby blocking epitaxial growth. In some other embodiments, fin spacers 94 may cover portions of the sidewalls of nanostructures 64, 66 and / or semiconductor fins 62, further blocking epitaxial growth. In another embodiment, the spacers used to form gate spacers 92 are adjusted to not form fin spacers 94, thereby allowing epitaxial source / drain regions 102 to extend to the surface of isolation region 70.

[0089] The epitaxial source / drain region 102 may include one or more semiconductor layers. For example, the epitaxial source / drain region 102 may include a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. Any number of semiconductor layers may be used for the epitaxial source / drain region 102. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor layer may have a dopant concentration that is less than the dopant concentration of the second semiconductor layer and greater than the dopant concentration of the third semiconductor layer. In embodiments where the epitaxial source / drain region 102 includes three semiconductor layers, the first semiconductor layer may be grown on the sidewalls of the semiconductor nanostructures 66, the second semiconductor layer may be grown on the first semiconductor layer, and the third semiconductor layer may be grown on the second semiconductor layer.

[0090] exist Figures 11A to 11BIn the embodiment of the present invention, a first ILD 114 is deposited over the epitaxial source / drain regions 102, the gate spacers 92, and the mask 86 (if present) or the dummy gate 84. The first ILD 114 can be formed of a dielectric material deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used.

[0091] In some embodiments, a contact etch stop layer (CESL) 112 is formed between the first ILD 114 and the epitaxial source / drain regions 102, the gate spacers 92, and the mask 86 (if present) or the dummy gate 84. The CESL 112 may be formed of a dielectric material having a high etch selectivity to the first ILD 114, such as silicon nitride, silicon oxynitride, or the like. The first ILD 114 may be formed by any suitable deposition process, such as CVD, ALD, or the like.

[0092] exist FIG. 12A to FIG. 12B In the embodiment of the present invention, a removal process is performed to make the top surface of the first ILD 114 flush with the top surface of the gate spacer 92 and the mask 86 (if present) or the dummy gate 84. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process may also remove portions of the mask 86 and gate spacer 92 along the sidewalls of the mask 86 on the dummy gate 84. After the planarization process, the top surfaces of the first ILD 114, the gate spacer 92, and the mask 86 (if present) or the dummy gate 84 are substantially coplanar (within process variations). As a result, the top surface of the mask 86 (if present) or the dummy gate 84 is exposed through the first ILD 114.

[0093] exist 13A to 13BIn the embodiment of the present invention, an ILD mask 116 is formed over the remaining portion of the first ILD 114. The ILD mask 116 covers the first ILD 114 to protect it during the subsequent gate replacement process. As an example of forming the ILD mask 116, the first ILD 114 may be recessed such that a recess is formed between opposing gate spacers 92 in the gate spacers 92. The recessing may be performed by any acceptable etching process, such as a wet or dry etch. An insulating material may then be conformally formed in the recess. The insulating material may be silicon nitride or silicon oxynitride, although any suitable material may be utilized, such as a low-dielectric constant (low-k) material having a k value of less than approximately 3.5. The insulating material may be formed by a deposition process such as ALD, CVD, or the like. Excess insulating material is then removed, which is above the top surface of the gate spacers 92 and the mask 86 (if present) or the dummy gate 84. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be used. Portions of the insulating material remain in the recesses after the removal process (thus forming the ILD mask 116).

[0094] exist FIG. 14A to FIG. 14B In one or more etching steps, mask 86 (if present) and dummy gate 84 are removed, resulting in recess 122 formed between gate spacers 92. Portions of dummy dielectric 82 in recess 122 are also removed. In some embodiments, dummy gate 84 and dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of dummy gate 84 at a faster rate than the material of gate spacers 92 and ILD mask 116 (if present) or first ILD 114. Etching process 122 exposes and / or overlies portions of semiconductor nanostructure 66 that function as channel regions in a subsequently completed nanostructured FET. Portions of semiconductor nanostructure 66 that function as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 102. During removal, dummy dielectric 82 may serve as an etch stop while dummy gate 84 is etched. The dummy dielectric 82 may then be removed after removing the dummy gate 84 .

[0095] Additionally, pendant hydroxyl groups (OH) are formed on the top surface of the upper semiconductor nanostructure 66 and on the top surface of the isolation region 70. The hydroxyl groups may bond to silicon atoms of the semiconductor nanostructure 66 and the isolation region 70. The hydroxyl groups may be formed due to intrinsic oxidation and / or exposure to moisture during the formation of the recess 122, or may be formed by a surface hydroxylation process after the recess 122 is formed. The surface hydroxylation process may be a plasma treatment performed with precursors that leave hydroxyl groups on the treated surface, such as a combination of oxygen (O2) and hydrogen (H2). The surface hydroxylation process may be anisotropic, such that the top surface of the upper semiconductor nanostructure 66 and the isolation region 70 are hydroxylated. As a result, the sidewalls of the gate spacer 92, nanostructures 64, 66, and semiconductor fin 62 may not be hydroxylated. The ILD mask 116 may protect the first ILD 114 from hydroxylation.

[0096] exist FIG. 15A to FIG. 15B In the process, treatment process 124 is performed to selectively replace some of the dangling hydroxyl groups with dangling amine groups (NH2). Specifically, at least some of the hydroxyl groups dangling from the top surface of the upper semiconductor nanostructure 66 are replaced with dangling amine groups. As described in greater detail later, a protective layer will be formed on the isolation region 70 by selectively depositing a protective material on a desired surface. The precursor of the protective material reacts with hydroxyl groups but not with amine groups, thereby effectively inhibiting the deposition of the protective material on surfaces where the dangling hydroxyl groups have been replaced with dangling amine groups. Thus, replacing at least some of the dangling hydroxyl groups with dangling amine groups (e.g., at the top surface of the upper semiconductor nanostructure 66) effectively increases the deposition selectivity between the top surface of the upper semiconductor nanostructure 66 and the top surface of the isolation region 70 relative to the selective deposition process used to form the protective layer. As a result, the orientation of the subsequently deposited protective layer can be advantageously controlled by replacing the desired hydroxyl groups with amine groups.

[0097] Treatment process 124 detaches hydroxyl groups from silicon atoms in semiconductor nanostructure 66 and attaches amine groups to those silicon atoms, thereby replacing the hydroxyl groups with the amine groups. Treatment process 124 has a first replacement ratio on the top surface of upper semiconductor nanostructure 66, while treatment process 124 has a second replacement ratio on the top surface of isolation region 70. In this context, "replacement ratio" refers to the percentage of hydroxyl groups replaced with amine groups by treatment process 124. It is more difficult for treatment process 124 to reach the lower portion of recess 122 than the upper portion of recess 122. Therefore, the first replacement ratio on the top surface of upper semiconductor nanostructure 66 is greater than the second replacement ratio on the top surface of isolation region 70. Treatment process 124 is controlled so that the difference between the replacement ratios of semiconductor nanostructure 66 and isolation region 70 is large.

[0098] After treatment process 124, the top surface of the upper semiconductor nanostructure 66 has fewer dangling hydroxyl groups and more dangling amine groups than the top surface of the isolation region 70. In this embodiment, the hydroxyl groups dangling from the top surface of the upper semiconductor nanostructure 66 are not completely replaced by amine groups, and none of the hydroxyl groups dangling from the top surface of the isolation region 70 are replaced by amine groups. Therefore, the top surface of the isolation region 70 is substantially free of amine groups after treatment process 124. In another embodiment (subsequently described for Figures 21A to 21B In the embodiment described above, hydroxyl groups hanging from the top surfaces of the upper semiconductor nanostructure 66 and the isolation region 70 are replaced by amine groups, but more hydroxyl groups hanging from the top surface of the upper semiconductor nanostructure 66 are replaced by amine groups than hydroxyl groups hanging from the top surface of the isolation region 70. Therefore, the amine groups still hang from the top surface of the isolation region 70 after the treatment process 124.

[0099] In some embodiments, treatment process 124 is a nitrogen soak process, in which semiconductor nanostructures 66 are soaked in a nitrogen-containing gas without generating a plasma. The nitrogen soak process can be performed in a chamber into which a nitrogen-containing gas is dispensed. The nitrogen-containing gas can include a nitrogen precursor and a carrier gas. The nitrogen precursor can be ammonia (NH3), nitrogen (N2), a combination thereof, or the like. The carrier gas can be an inert gas such as Ar, He, Xe, Ne, Kr, Rn, the like, or a combination thereof. The nitrogen soak is performed at an elevated temperature, such as by heating the chamber during the nitrogen soak process. In some embodiments, the nitrogen soak is performed at a temperature ranging from 400°C to 800°C and for a duration of 4 to 8 hours. As a result, hydroxyl groups are detached from silicon atoms of semiconductor nanostructures 66, react with the nitrogen precursor to form amine groups, and the amine groups attach to those silicon atoms. Performing the nitrogen soak in the presence of a nitrogen-containing gas and at an elevated temperature can help achieve the aforementioned large difference between the replacement ratios of semiconductor nanostructures 66 and isolation regions 70.

[0100] In some embodiments, the treatment process 124 is a nitrogen plasma treatment, wherein the semiconductor nanostructures 66 are bombarded with nitrogen-containing ions. The nitrogen-containing ions may be nitrenium ions (NH2 + ), nitrogen ion (nitrogen ion, N2 +), combinations thereof, or the like. The nitrogen plasma treatment may be performed in a chamber to which a source gas is dispensed. The source gas may include a nitrogen precursor and a carrier gas. The nitrogen precursor may be ammonia (NH3), nitrogen (N2), combinations thereof, or the like. The carrier gas may be an inert gas such as Ar, He, Xe, Ne, Kr, Rn, the like, or a combination thereof. Plasma is generated in the chamber from the source gas. The plasma may be generated by a plasma generator such as an inductively coupled plasma system, a capacitively coupled plasma system, a microwave plasma generating gas, or the like. The plasma generator generates radio frequency power that generates plasma from the source gas by exciting the source gas to a plasma state. The plasma generating power may be pulsed between a low power (e.g., substantially zero watts) and a high power. In some embodiments, the nitrogen plasma treatment is performed using a plasma generating power having a high power in the range of 200 watts to 800 watts. In some embodiments, the nitrogen plasma treatment is performed at a temperature ranging from 200° C. to 450° C. for a duration of 30 minutes to 2 hours. The generated plasma includes nitrogen-containing ions, and the semiconductor nanostructures 66 are bombarded by the nitrogen-containing ions. Consequently, hydroxyl groups are detached from the silicon atoms of the semiconductor nanostructures 66, which react with the nitrogen-containing ions to form amine groups, which are attached to those silicon atoms. Performing the nitrogen plasma treatment with a nitrogen precursor and at a desired plasma generation power or temperature can help achieve the aforementioned large difference between the replacement ratios of the semiconductor nanostructures 66 and the isolation regions 70.

[0101] exist 16A to 16B In the embodiment of the present invention, a protective layer 128 is formed on the top surface of the isolation region 70. The protective layer 128 is formed by selectively depositing a protective material on the top surface of the isolation region 70. The protective material may be a carbon-containing dielectric material, such as silicon oxycarbonitride, silicon carbonitride, or the like, which may be deposited by a selective deposition process, such as a selective ALD process, a selective CVD process, or the like. The protective material may be doped with impurities such as hydrogen. The protective material of the protective layer 128 is different from the insulating material of the isolation region 70. For example, the protective material of the protective layer 128 may have a greater carbon concentration than the insulating material of the isolation region 70.

[0102] As will be described in more detail later, the dummy nanostructure 64 will be replaced by a corresponding gate structure. The protective layer 128 will protect the isolation region 70 during the removal of the dummy nanostructure 64. Specifically, the protective material of the protective layer 128 has a high etch selectivity relative to the dummy material of the dummy nanostructure 64. Therefore, the etching loss of the isolation region 70 during the subsequent gate replacement process can be reduced. In some embodiments, the protective layer 128 is formed to to The thickness of the protective layer 128 may be within a range of 0.5 to 1.0. This thickness of the protective layer 128 may help provide protection to the isolation region 70 during the removal of the dummy nanostructures 64. In some embodiments, the composition of the protective material includes from 30% to 50% silicon, from 10% to 20% carbon, and from 0% to 10% nitrogen, wherein the carbon to silicon ratio is within a range of 0.3 to 0.5 (such as within a range of 0.3 to 0.4). This composition of the protective material may allow the protective material to have a low etch rate during the removal of the dummy nanostructures 64. In some embodiments, the etch rate of the protective material in dilute hydrofluoric acid (dHF) is less than 0.5%. The etch rate of the protective material can be adjusted to a desired amount by adjusting the composition of the protective material.

[0103] In some embodiments, protective layer 128 is formed by a selective ALD process performed by cyclically dispensing different source precursors into recess 122. The source precursors include a silicon-carbon precursor and one or more other precursors that react with the silicon-carbon precursor to form the protective material of protective layer 128. The silicon-carbon precursor is a precursor that includes both silicon and carbon, such as bis(tertiary-butyl-amino)silane (BTBAS), bis(diethylamino)silane (BDEAS), or the like. Other precursors may include nitrogen and / or oxygen, such as oxygen, amines, or the like. ALD cycles are performed by sequentially dispensing each of the source precursors, with each ALD cycle resulting in the deposition of an atomic layer (sometimes referred to as a monolayer) of the protective material of protective layer 128. Multiple ALD cycles are repeated until protective layer 128 is formed to the desired thickness (described previously). The selective ALD process may be plasma enhanced, wherein the plasma is generated after at least some of the source precursors are dispensed. The plasma may be generated by argon, helium, oxygen, a combination thereof, or the like, which is excited into a plasma state using a plasma generator. During the ALD cycle of the selective ALD process, the top surface of the isolation region 70 is immersed in the silicon carbon precursor. The process conditions of the selective ALD process (e.g., temperature, pressure, and plasma generation) are selected so that the hydrogen atoms in the hydroxyl groups are disconnected. As a result, the silicon atoms in the silicon carbon precursor adsorb on the oxygen atoms remaining from the hydroxyl groups and attach to the oxygen atoms. The silicon carbon precursor preferably attaches to the hydroxyl groups and preferably does not attach to the amine groups. Thus, the amine groups act as inhibitors, thereby inhibiting the physical and / or chemical adsorption of the silicon carbon precursor. Effectively, the treatment process 124 (previously described for FIG. 15A to FIG. 15BThe selective ALD process described herein increases the deposition selectivity between the top surface of upper semiconductor nanostructure 66 and the top surface of isolation region 70 relative to the selective ALD process. Because the hydroxyl groups are pendant from the top surface of isolation region 70 and the amine groups are pendant from the top surface of upper semiconductor nanostructure 66, the silicon-carbon precursor is attached to isolation region 70 but is inhibited from attaching to semiconductor nanostructure 66. Consequently, adsorption of the silicon-carbon precursor is selective to isolation region 70, and the protective material of protective layer 128 is selectively deposited on the top surface of isolation region 70. The top surface of upper semiconductor nanostructure 66 can be substantially free of protective layer 128. Furthermore, the top surface of upper semiconductor nanostructure 66 can be substantially free of carbon after deposition of protective layer 128. Forming pendant amine groups on semiconductor nanostructure 66 is a low-cost way to avoid forming protective layer 128 on semiconductor nanostructure 66.

[0104] exist 17A to 17B , the remaining portions of dummy nanostructures 64 are removed to form openings 130 between semiconductor nanostructures 66. The remaining portions of dummy nanostructures 64 can be removed by any acceptable etching process that selectively etches the material of dummy nanostructures 64 at a faster rate than the material of semiconductor nanostructures 66 and protective layer 128. The etching process can be isotropic. For example, when dummy nanostructures 64 are formed of silicon germanium, semiconductor nanostructures 66 are formed of silicon, and protective layer 128 is formed of silicon oxycarbonitride, the etching process can be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. Similarly, when dummy nanostructures 64 are formed of silicon oxide, semiconductor nanostructures 66 are formed of silicon, and protective layer 128 is formed of silicon oxycarbonitride, the etching process can be a wet etch using dilute hydrofluoric acid (dHF) or the like. Protection layer 128 protects isolation region 70 during etching of dummy nanostructure 64, thereby reducing etching loss of isolation region 70. In some embodiments, isolation region 70 and dummy nanostructure 64 are formed of the same material, and forming protection layer 128 allows dummy nanostructure 64 to be removed without removing isolation region 70.

[0105] exist 18A to 18B In the embodiment of the present invention, the dangling amine groups are removed from the surface of the semiconductor nanostructure 66, for example. The dangling amine groups can be removed by any acceptable etching process (such as dry etching and / or wet etching) that selectively etches the dangling amine groups at a faster rate than the material of the semiconductor nanostructure 66 and the protective layer 128. In some embodiments, the dangling amine groups are removed by the same etching process as the etching process used to remove the remaining portion of the dummy nanostructure 64. In some embodiments, the dangling amine groups are removed by a separation etching process that is performed after the etching process used to remove the remaining portion of the dummy nanostructure 64.

[0106] The dangling amine groups are easier to etch than the protective material of the protective layer 128. By preventing the formation of the protective layer 128 on the semiconductor nanostructure 66, the semiconductor nanostructure 66 can be more easily exposed after the deposition of the protective layer 128. Over-etching of the semiconductor nanostructure 66 can thus be avoided, thereby improving device reliability.

[0107] exist Figures 19A to 19B In the embodiment of the present invention, a gate dielectric 132 and a gate electrode 134 are formed to replace the gate. Each respective pair of gate dielectric 132 and gate electrode 134 may be collectively referred to as a "gate structure." Each gate structure encapsulates the channel region of semiconductor nanostructure 66, such that the gate structure extends along the sidewalls, bottom surface, and top surface of semiconductor nanostructure 66. Some of the gate structures also extend along the sidewalls and / or top surface of semiconductor fin 62.

[0108] Gate dielectric 132 includes one or more gate dielectric layers disposed on: the sidewalls and / or top surfaces of semiconductor fin 62; the top, sidewalls, and bottom surfaces of the channel region of semiconductor nanostructure 66; the sidewalls of inner spacer 98; and the sidewalls of gate spacer 92. Gate dielectric 132 may be formed from an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multilayers thereof, or the like. Additionally or alternatively, gate dielectric 132 may be formed from a high-k dielectric material (e.g., a dielectric material having a k value greater than approximately 7.0), such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material of gate dielectric 132 may be formed by molecular-beam deposition (MBD), ALD, PECVD, or the like. Although a single layer of gate dielectric 132 is shown, gate dielectric 132 may include any number of interfacial layers and any number of main layers. For example, gate dielectric 132 may include an interfacial layer and an overlying high-k dielectric layer.

[0109] The gate electrode 134 includes one or more gate electrode layers disposed over the gate dielectric 132. The gate electrode 134 can be formed from a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayers thereof, or the like. Although a single-layer gate electrode 134 is shown, the gate electrode 134 can include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and any filler materials.

[0110] As an example for forming a gate structure, one or more gate dielectric layers may be deposited in the recess 122 and the opening 130. The gate dielectric layer may also be deposited on the gate spacers 92 and the ILD mask 116 (if present), or on the top surface of the first ILD 114. Subsequently, one or more gate electrode layers may be deposited on the gate dielectric layer and in the remaining portions of the recess 122 and the opening 130. A removal process may then be performed to remove excess portions of the gate dielectric layer and the gate electrode layer above the gate spacers 92 and the ILD mask 116 (if present), or on the top surface of the first ILD 114. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. After the removal process, portions of the gate dielectric layer remain in the recess 122 and the opening 130 (thereby forming the gate dielectric 132). After the removal process, the gate electrode layer has portions remaining in the recess 122 and the opening 130 (thus forming the gate electrode 134). When a planarization process is utilized, the top surfaces of the gate spacers 92, the ILD mask 116 (if present) or the first ILD 114, the gate dielectric 132, and the gate electrode 134 are substantially coplanar (within process variations).

[0111] exist FIG. 20A to FIG. 20B In the embodiment of the present invention, the second ILD 144 is deposited over the gate spacer 92, the ILD mask 116 (if present), or the first ILD 114, the gate dielectric 132, and the gate electrode 134. In some embodiments, the second ILD 144 is a flow-type film formed by a flow-type CVD method. In some embodiments, the second ILD 144 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which can be formed by any suitable deposition method, such as CVD, PECVD, or the like.

[0112] In some embodiments, an etch stop layer (ESL) 142 is formed between the second ILD 144 and the gate spacers 92, the ILD mask 116 (if present), or the first ILD 114, the gate dielectric 132, and the gate electrode 134. The ESL 142 may be formed of a dielectric material having a high etch selectivity to the dielectric material of the second ILD 144, such as silicon nitride, silicon oxynitride, or the like. The second ILD 144 may be formed by any suitable deposition process, such as CVD, ALD, or the like.

[0113] A gate contact 146 and source / drain contacts 148 are formed through the second ILD 144 and the first ILD 114 to electrically couple to the gate electrode 134 and the epitaxial source / drain regions 102, respectively. As an example for forming gate contact 146 and source / drain contacts 148, an opening for gate contact 146 is formed through the second ILD 144 and the ESL 142, and an opening for source / drain contacts 148 is formed through the second ILD 144, the ESL 142, the ILD mask 116 (if present), the first ILD 114, and the CESL 112. The openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately) such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, a copper alloy, indium, gold, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the top surface of the second ILD 144. The remaining liner and conductive material form a gate contact 146 and a source / drain contact 148 in the opening. The gate contact 146 and the source / drain contact 148 may be formed in separate processes or may be formed in the same process. Although shown as being formed with the same cross-section, it should be understood that each of the gate contact 146 and the source / drain contact 148 may be formed with a different cross-section to avoid shorting the contacts.

[0114] Optionally, a metal-semiconductor alloy region 150 is formed at the interface between the epitaxial source / drain regions 102 and the source / drain contacts 148. The metal-semiconductor alloy region 150 can be a silicide region formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium region formed from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy region 150 can be formed before the material of the source / drain contacts 148 by depositing a metal in the openings for the source / drain contacts 148 and then performing a thermal annealing process. The metal can be any metal, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, that is capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain regions 102 to form a low-resistance metal-semiconductor alloy. The metal may be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process such as a wet clean may be performed to remove any residual metal from the openings of the source / drain contacts 148, such as from the surface of the metal semiconductor alloy region 150. The material of the source / drain contacts 148 may then be formed on the metal semiconductor alloy region 150.

[0115] In the previously described embodiment, the semiconductor layer 56 (see Figure 2) is patterned to form channel regions in both the n-type region 50N and the p-type region 50P. In another embodiment (not shown separately), a different set of semiconductor layers is patterned to form channel regions in the n-type region 50N and the p-type region 50P. For example, the multilayer stack 52 (previously Figure 2 The first and second nanostructures are formed by alternating first and second semiconductor layers of a first semiconductor material and a second semiconductor material, respectively. Figure 3 A similar process as described is formed with a multilayer stack 52. The first semiconductor material of the first nanostructure may be suitable for a p-type device, while the second semiconductor material of the second nanostructure may be suitable for an n-type device. The etching of the first and second semiconductor materials relative to each other may have a high etch selectivity such that the first nanostructure may be removed without significantly removing the second nanostructure in the n-type region 50N, and the second nanostructure may be removed without significantly removing the first nanostructure in the p-type region 50P. Internal spacers 98 in the n-type region 50N are formed on the sidewalls of the first nanostructure, while the internal spacers 98 in the p-type region 50P are formed by a process similar to that previously described for the first nanostructure. Figures 9A to 9B The gate structure (including gate dielectric 132 and gate electrode 134) in the p-type region 50P is formed around the first nanostructure, while the gate structure in the n-type region 50N is formed by a process similar to that previously described for the second nanostructure. Figures 14A to 19B The process described revolves around the second nanostructure formation. Various masking steps can be used to mask and expose appropriate areas when forming the inner spacers 98 and gate structures.

[0116] Figures 21A to 21B FIG is a diagram of a nanostructured FET according to some other embodiments. FIG. 20A to FIG. 20B , except that there are some amine groups hanging from the top surface of the isolation region 70. Therefore, the protection layer 128 is formed over and covers those amine groups, which remain hanging and do not react with the protection material of the protection layer 128.

[0117] Other functional groups may be utilized. More generally, any first functional groups may be formed so as to be suspended from the top surface of the upper semiconductor nanostructure 66 and the top surface of the isolation region 70. The treatment process 124 may then be performed to selectively replace some of the first functional groups with second functional groups. The protective layer 128 may then be formed by a selective deposition process that preferably attaches to the first functional groups and preferably does not attach to the second functional groups. Thus, replacing at least some of the first functional groups with the second functional groups effectively increases the deposition selectivity between the top surface of the upper semiconductor nanostructure 66 and the top surface of the isolation region 70 with respect to the selective deposition process.

[0118] Figures 22A to 23B is a diagram of an intermediate stage in the fabrication of a nanostructured FET according to some other embodiments. Figure 22A and Figure 23A The diagram is along Figure 1 A cross-sectional view of a similar cross section to the reference cross section AA'. Figure 22B and Figure 23B The diagram is along Figure 1 Cross-sectional view of a similar cross section as in the reference cross section BB'.

[0119] exist FIG. 22A to FIG. 22B , similar steps as those previously described are performed to form FIG. 14A to FIG. 14B In this embodiment, instead of performing treatment process 124, an inhibiting layer 126 is deposited on the top surface of upper semiconductor nanostructure 66. Inhibiting layer 126 covers (e.g., passivates) the hydroxyl groups on the top surface of upper semiconductor nanostructure 66. Inhibiting layer 126 can be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like, which can be deposited by a selective deposition process such as a selective ALD process, a selective CVD process, or the like. Inhibiting layer 126 may not be deposited on isolation region 70.

[0120] exist FIG. 23A to FIG. 23B In the embodiment, a protective layer 128 is formed on the top surface of the isolation region 70. The protective layer 128 is formed by 16A to 16B In the manner described, a protective material is selectively deposited on the top surface of isolation region 70 to form the protective layer 128. The top surface of inhibition layer 126 may be substantially free of hydroxyl groups, and therefore the selective deposition process used to form the protective material is preferably not inhibition layer 126. Effectively, forming inhibition layer 126 increases the deposition selectivity between the top surface of upper semiconductor nanostructure 66 and the top surface of isolation region 70 relative to the selective deposition process. Protection layer 128 may not be deposited on inhibition layer 126.

[0121] Subsequently, similar steps as those previously described are performed to complete the fabrication of the nanostructure FET. The inhibiting layer 126 may be removed before the gate structure is formed around the semiconductor nanostructure 66. The inhibiting layer 126 may be removed by any acceptable etching process (such as dry etching and / or wet etching) that selectively etches the material of the inhibiting layer 126 at a faster rate than the material of the semiconductor nanostructure 66 and the protective layer 128. In some embodiments, the inhibiting layer 126 is formed by the same process as that used to remove the dummy nanostructure 64 (previously described for the semiconductor nanostructure 66). 17A to 17B In some embodiments, the inhibition layer 126 is removed by a separate etching process that is performed after the etching process used to remove the remaining portion of the dummy nanostructure 64.

[0122] Embodiments can achieve multiple advantages. Forming dangling amine groups or an inhibiting layer 126 on the top surface of the upper semiconductor nanostructure 66 increases selectivity for selectively depositing the protective layer 128. Specifically, the dangling amine groups or the inhibiting layer 126 inhibit deposition of the protective layer 128 on the top surface of the upper semiconductor nanostructure 66. As a result, the top surface of the upper semiconductor nanostructure 66 can be more easily exposed in subsequent processing before a gate structure is formed around the semiconductor nanostructure 66. Over-etching of the semiconductor nanostructure 66 can thus be avoided, thereby improving device reliability.

[0123] In one embodiment, a method for fabricating a nanostructure field-effect transistor includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing the deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative to a selective deposition process; depositing a protective layer on the top surface of the isolation region by performing a selective deposition process; removing the dummy nanostructure by selectively etching the dummy material of the dummy nanostructure at a faster rate than the protective material of the protective layer; and forming a gate structure surrounding the semiconductor nanostructure. In some embodiments of the method, a plurality of hydroxyl groups are suspended from the top surface of the semiconductor nanostructure and from the top surface of the isolation region, and increasing the deposition selectivity between the top surface of the semiconductor nanostructure and the top surface of the isolation region includes replacing the hydroxyl groups suspended from the top surface of the semiconductor nanostructure with a plurality of amine groups. In some embodiments of the method, replacing the hydroxyl groups includes immersing the semiconductor nanostructure in a nitrogen-containing gas without generating a plasma. In some embodiments of the method, replacing the hydroxyl groups includes bombarding the semiconductor nanostructure with a plurality of nitrogen-containing ions. In some embodiments of the method, increasing the deposition selectivity between the top surface of the semiconductor nanostructure and the top surface of the isolation region includes depositing an inhibition layer on the top surface of the semiconductor nanostructure. In some embodiments of the method, a plurality of hydroxyl groups are suspended from a top surface of the isolation region, and depositing the protective layer comprises immersing the isolation region in a silicon-carbon precursor that adsorbs onto oxygen atoms of the hydroxyl groups. In some embodiments of the method, the dummy nanostructure is formed of silicon germanium, the semiconductor nanostructure is formed of silicon, the protective layer is formed of silicon oxycarbonitride, and removing the dummy nanostructure comprises etching the dummy nanostructure with tetramethylammonium hydroxide or ammonium hydroxide. In some embodiments of the method, the dummy nanostructure is formed of silicon oxide, the semiconductor nanostructure is formed of silicon, the protective layer is formed of silicon oxycarbonitride, and removing the dummy nanostructure comprises etching the dummy nanostructure with dilute hydrofluoric acid.

[0124] In one embodiment, a method for fabricating a nanostructure field-effect transistor includes: exposing a semiconductor nanostructure and an isolation region by removing a dummy gate, wherein a plurality of hydroxyl groups are suspended from a top surface of the semiconductor nanostructure and from a top surface of the isolation region; performing a treatment process to selectively replace some of the hydroxyl groups with a plurality of amine groups suspended from the top surface of the semiconductor nanostructure; depositing a protective layer on the top surface of the isolation region using a silicon-carbon precursor that reacts with the hydroxyl groups but not with the amine groups, such that the top surface of the semiconductor nanostructure is substantially free of carbon after the protective layer is deposited; and removing the amine groups suspended from the top surface of the semiconductor nanostructure. In some embodiments of the method, the treatment process includes immersing the semiconductor nanostructure in ammonia or nitrogen gas without generating a plasma. In some embodiments of the method, the treatment process includes bombarding the semiconductor nanostructure with nitrogen cations or nitrogen ions. In some embodiments of the method, the top surface of the isolation region is substantially free of amine groups after the treatment process. In some embodiments of the method, a plurality of amine groups are suspended from the top surface of the isolation region after the treatment process. In some embodiments of the method, the silicon-carbon precursor is bis(tert-butylamino)silane or bis(diethylamino)silane.

[0125] In one embodiment, a nanostructure field-effect transistor includes: source / drain regions; a semiconductor nanostructure adjacent to the source / drain regions; an isolation region adjacent to the semiconductor nanostructure, the isolation region comprising a first dielectric material; a protective layer on the isolation region, the protective layer comprising a second dielectric material, the second dielectric material comprising more carbon than the first dielectric material; a gate structure on the protective layer and surrounding the semiconductor nanostructure; and spacers between the gate structure and the source / drain regions, the spacers electrically isolating the gate structure from the source / drain regions, the spacers physically contacting the semiconductor nanostructure. In some embodiments of the nanostructure field-effect transistor, the second dielectric material is silicon oxycarbonitride or silicon carbonitride. In some embodiments of the nanostructure field-effect transistor, the second dielectric material is doped with hydrogen. In some embodiments of the nanostructure field-effect transistor, the protective layer is on a top surface of the isolation region, and the top surface of the isolation region is substantially free of amine groups. In some embodiments of the nanostructure field-effect transistor, the protective layer is on the top surface of the isolation region, and a plurality of amine groups are suspended from the top surface of the isolation region. In some embodiments of the nanostructured field effect transistor, the second dielectric material has a carbon to silicon ratio in a range of 0.3 to 0.5.

[0126] In some embodiments, a nanostructure field-effect transistor includes: source / drain regions, a semiconductor nanostructure, an isolation region, a protective layer, a gate structure, and a spacer. The semiconductor nanostructure is adjacent to the source / drain regions. The isolation region is adjacent to the semiconductor nanostructure. The protective layer is on the isolation region and is a carbon-containing dielectric layer. The gate structure is on the protective layer and surrounds the semiconductor nanostructure. The spacer is between the gate structure and the source / drain regions, electrically isolating the gate structure from the source / drain regions.

[0127] In some embodiments, the protection layer is on the top surface of the isolation region.

[0128] In some embodiments, the thickness of the protective layer is Inside.

[0129] In some embodiments, the carbon-containing dielectric layer is a silicon oxycarbonitride layer or a silicon carbonitride layer.

[0130] In some embodiments, the top surface of the semiconductor nanostructure is substantially free of a protective layer.

[0131] In some embodiments, a nanostructure field-effect transistor includes: source / drain regions, a semiconductor nanostructure, an isolation region, a gate structure, a protective layer, and a spacer. The semiconductor nanostructure is adjacent to the source / drain regions. The isolation region is adjacent to the semiconductor nanostructure. The gate structure surrounds the semiconductor nanostructure. The protective layer is located above the isolation region and below the gate structure, and the protective layer is a carbon-containing dielectric layer. The spacer is located between the gate structure and the source / drain regions, and the spacer physically contacts the semiconductor nanostructure.

[0132] In some embodiments, the protection layer is on the top surface of the isolation region.

[0133] In some embodiments, the thickness of the protective layer is Inside.

[0134] In some embodiments, a nanostructure field-effect transistor includes: source / drain regions, a semiconductor nanostructure, an isolation region, a protective layer, a gate structure, and an internal spacer. The semiconductor nanostructure is adjacent to the source / drain regions. The isolation region is adjacent to the semiconductor nanostructure. The protective layer is on the isolation region and is a carbon-containing dielectric layer that is not located on the semiconductor nanostructure. The gate structure is on the protective layer and surrounds the semiconductor nanostructure. The internal spacer is between the gate structure and the source / drain regions.

[0135] In some embodiments, the carbon-containing dielectric layer is a silicon oxycarbonitride layer or a silicon carbonitride layer.

[0136] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and replacements may be made herein for such equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A nanostructured field-effect transistor, characterized in that: include: a source / drain region; a semiconductor nanostructure adjacent to the source / drain region; an isolation region adjacent to the semiconductor nanostructure; a protective layer on the isolation region, wherein the protective layer is a carbon-containing dielectric layer; a gate structure on the protection layer and around the semiconductor nanostructure; and A spacer is provided between the gate structure and the source / drain region, wherein the spacer electrically isolates the gate structure from the source / drain region.

2. The nanostructured field-effect transistor according to claim 1, wherein: The protection layer is on a top surface of the isolation region.

3. The nanostructured field effect transistor according to claim 1, wherein: The thickness of the protective layer is Inside.

4. The nanostructured field effect transistor according to claim 1, wherein: The carbon-containing dielectric layer is a silicon carbonitride oxide layer or a silicon carbonitride layer.

5. The nanostructured field effect transistor according to any one of claims 1 to 4, characterized in that The protective layer is substantially absent on a top surface of the semiconductor nanostructure.

6. A nanostructured field-effect transistor, characterized in that: include: a source / drain region; a semiconductor nanostructure adjacent to the source / drain region; an isolation region adjacent to the semiconductor nanostructure; a gate structure surrounding the semiconductor nanostructure; a protective layer on the isolation region and below the gate structure, wherein the protective layer is a carbon-containing dielectric layer; and A spacer is provided between the gate structure and the source / drain region, wherein the spacer physically contacts the semiconductor nanostructure.

7. The nanostructured field effect transistor according to claim 6, wherein: The protection layer is on a top surface of the isolation region.

8. The nanostructured field-effect transistor according to claim 6 or claim 7, wherein: The thickness of the protective layer is Inside.

9. A nanostructured field effect transistor, characterized in that: include: a source / drain region; a semiconductor nanostructure adjacent to the source / drain region; an isolation region adjacent to the semiconductor nanostructure; a protective layer on the isolation region, wherein the protective layer is a carbon-containing dielectric layer and is not located on the semiconductor nanostructure; a gate structure on the protection layer and around the semiconductor nanostructure; and An inner spacer between the gate structure and the source / drain region.

10. The nanostructured field effect transistor according to claim 9, wherein: The carbon-containing dielectric layer is a silicon carbonitride oxide layer or a silicon carbonitride layer.

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