Time correction signal waveform processing circuit

Abstract

The utility model relates to the technical field of hardware timing equipment of a transformer substation, in particular to a timing signal waveform processing circuit, which is provided with a signal correction module, increases the slope of a rising edge to a certain extent, extracts the slope of the rising edge in a signal after the corrected signal is amplified by a differential operational amplifier circuit, and outputs the waveform of the timing signal. And the rising edge is extracted as a base point of time positioning according to the slope of the rising edge and the signal amplitude, so that the time is determined to be the time when each bit approaches the sending end, and the time calibration is more accurate. The rising edge extraction module provided by the utility model can prevent false triggering, and can adjust the triggering opportunity according to the amplitude of the level signal, for example, when the amplitude is relatively low, the corresponding rising edge slope during triggering is also reduced, the timing opportunity is more sensitively captured, and the reliability is high.

Description

Technical Field

[0001] The utility model relates to the technical field of hardware timing equipment for transformer substations, in particular to a timing signal waveform processing circuit. Background Art

[0002] Only when all automated equipment in the power system (such as fault recorders, relay protection devices, and RTU microcomputer monitoring systems) uses a unified time base can the cause and process of an accident be accurately analyzed based on the fault recorder data and the sequence and exact timing of the operation of each switch and circuit breaker. Unified and accurate time is a key measure to ensure the safe operation of the power system and improve its performance.

[0003] One time signal method for substations is IRIG-B code time synchronization. The basic code elements of the B code are "0" code element, "1" code element, and "p" code element. Each code element occupies 10ms. The high-level pulse width of the "0" code element is 2ms, the high-level pulse width of the "1" code element is 5ms, and the high-level pulse width of the "p" code element is 8ms. In related technologies, these level signals are transmitted through RS485 communication cables.

[0004] At the start of time calibration, if the device being calibrated detects two consecutive p codes, the second identifier is the reference marker Pr, whose leading edge marks the starting point of the second synchronization pulse. The first rising edge after the reference marker Pr corresponds to the moment when the second synchronization pulse has been delayed by 10ms. Therefore, capturing the rising edge of the signal is crucial for accurate time calibration. However, due to the high level of electrical interference generated by substation electrical equipment, this further affects the waveform of the RS485 transmission signal (the timing signal is transmitted via RS485). This discrepancy in the timing of the rising edge recognition results in suboptimal synchronization among substation equipment.

[0005] Based on this, it is necessary to develop a timing signal waveform processing circuit. Utility Model Content

[0006] The embodiment of the utility model provides a timing signal waveform processing circuit for solving the problem of inaccurate timing caused by the difference in the recognition timing of the rising edge of the IRIG-B code timing in the prior art.

[0007] In a first aspect, an embodiment of the present invention provides a timing signal waveform processing circuit, comprising:

[0008] Two waveform correctors, a differential operational amplifier circuit, a rising edge slope extraction module, and a rising edge extraction module;

[0009] The output ends of the two waveform correctors are electrically connected to the two input ends of the differential operational amplifier circuit respectively; the input end of the rising edge slope extraction module is electrically connected to the output end of the differential operational amplifier circuit; the input end of the rising edge extraction module is electrically connected to the output end of the differential operational amplifier circuit and the output end of the rising edge slope extraction module;

[0010] When a differential signal is input into the input ends of the two waveform correctors, the rising edge slope of the differential signal increases. The differential signal with increased slope is converted into a level signal by the differential operational amplifier circuit and then sent to the rising edge slope extraction module to obtain a slope signal. The rising edge extraction module generates a rectangular wave signal based on the level signal and the slope signal.

[0011] In some possible implementations, the two waveform correctors respectively include: a first resistor, a second resistor, a third resistor, a first capacitor, and a first operational amplifier;

[0012] The inverting input terminal of the first operational amplifier is electrically connected to the second terminal of the first resistor and the first terminal of the third resistor;

[0013] The positive input terminal of the first operational amplifier is electrically connected to the second end of the second resistor and the first end of the first capacitor; the output terminal of the first operational amplifier is electrically connected to the second end of the third resistor;

[0014] A first end of the first resistor and a second end of the first capacitor are grounded.

[0015] In some possible implementations, the differential operational amplifier circuit includes: a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a second operational amplifier;

[0016] The second end of the fourth resistor and the second end of the fifth resistor are electrically connected to the inverting input terminal of the second operational amplifier and the positive input terminal of the second operational amplifier respectively;

[0017] Two ends of the seventh resistor are connected to the ground and the positive input terminal of the second operational amplifier respectively;

[0018] Two ends of the sixth resistor are electrically connected to the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier respectively;

[0019] The first end of the fourth resistor and the first end of the fifth resistor are electrically connected to the two waveform corrector output ends respectively.

[0020] In some possible implementations, the rising edge slope extraction module includes: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a second capacitor, and a third operational amplifier;

[0021] The inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the second capacitor and the first terminal of the eleventh resistor; the output terminal of the third operational amplifier is electrically connected to the second terminal of the eleventh resistor;

[0022] The second end of the eighth resistor is electrically connected to the first end of the second capacitor;

[0023] The positive input terminal of the third operational amplifier is electrically connected to the second end of the ninth resistor and the first end of the tenth resistor;

[0024] The first end of the ninth resistor and the second end of the tenth resistor are connected to the positive electrode of the power supply and the ground respectively;

[0025] The first end of the eighth resistor is electrically connected to the output end of the differential operational amplifier circuit.

[0026] In some possible implementations, the rising edge extraction module includes: a level signal amplitude sampling circuit and a fourth operational amplifier;

[0027] The output terminal of the level signal amplitude sampling circuit is electrically connected to the positive input terminal of the fourth operational amplifier;

[0028] The inverting input terminal of the fourth operational amplifier is electrically connected to the output terminal of the rising edge slope extraction module.

[0029] In some possible implementations, the level signal amplitude sampling circuit includes: a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a third capacitor, a fourth capacitor, a first transistor, and a second transistor;

[0030] The base and collector of the first transistor are electrically connected to the output terminal of the differential operational amplifier circuit and the positive electrode of the power supply, respectively; the emitter of the first transistor is electrically connected to the collector of the second transistor and the first end of the twelfth resistor;

[0031] Two ends of the third capacitor are electrically connected to the second end of the twelfth resistor and the first end of the fourth capacitor respectively, and the second end of the fourth capacitor is grounded;

[0032] The first end of the fourth capacitor is electrically connected to the positive input terminal of the fourth operational amplifier;

[0033] Two ends of the thirteenth resistor are electrically connected to the emitter of the second transistor and the ground respectively;

[0034] Two ends of the fourteenth resistor are electrically connected to the base of the second transistor and the output end of the differential operational amplifier circuit respectively.

[0035] In some possible implementations, the timing signal waveform processing circuit further includes: a digital signal extraction module;

[0036] The two input terminals of the digital signal extraction module are electrically connected to the output terminal of the rising edge extraction module and the output terminal of the differential operational amplifier circuit respectively;

[0037] When the two input terminals of the digital signal extraction module input the level signal and the rectangular wave signal respectively, the digital signal extraction module outputs a high level signal or a low level signal according to the level signal and the rectangular wave signal.

[0038] In some possible implementations, the digital signal extraction module includes: a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a fifth capacitor, a diode, and a third transistor;

[0039] The base of the third transistor and the emitter of the third transistor are electrically connected to the second end of the fifteenth resistor and the first end of the sixteenth resistor respectively, the first end of the fifteenth resistor is electrically connected to the output end of the rising edge extraction module, and the second end of the sixteenth resistor is grounded;

[0040] The first end of the fifth capacitor and the cathode of the diode are electrically connected to the collector of the third transistor, and the second end of the fifth capacitor is grounded;

[0041] Two ends of the seventeenth resistor are electrically connected to the output end of the differential operational amplifier circuit and the anode of the diode respectively.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The embodiment of the present utility model discloses a timing signal waveform processing circuit, which is provided with a signal correction module, which improves the slope of the rising edge to a certain extent. After the corrected signal is amplified by a differential operational amplifier circuit, the slope of the rising edge in the signal is extracted, and the rising edge is extracted as the base point of time positioning based on the slope of the rising edge and the signal amplitude. Therefore, the timing is determined to be the timing of each bit approaching the sending end, and the timing is more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0045] Figure 1 This is a functional block diagram of a timing signal waveform processing circuit provided by an embodiment of the present utility model;

[0046] Figure 2 This is a schematic diagram of the waveform corrector provided by the embodiment of the utility model;

[0047] Figure 3 This is a schematic diagram of a differential operational amplifier circuit provided by an embodiment of the present utility model;

[0048] Figure 4 This is a schematic diagram of a rising edge slope extraction module provided by an embodiment of the present utility model;

[0049] Figure 5 This is a schematic diagram of a rising edge extraction module provided by an embodiment of the present utility model;

[0050] Figure 6 This is a schematic diagram of a digital signal extraction module provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0051] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, and methods are omitted to avoid obscuring the description of the present invention with unnecessary detail.

[0052] In order to make the purpose, technical solutions and advantages of the present invention clearer, the following will be described through specific implementation methods in conjunction with the accompanying drawings.

[0053] The following is a detailed description of an embodiment of the present invention. This example is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process. However, the protection scope of the present invention is not limited to the following embodiment.

[0054] Figure 1 This is the overall structural diagram of the timing signal waveform processing circuit provided by the embodiment of the present utility model.

[0055] like Figure 1As shown, it shows the overall structure of the timing signal waveform processing circuit provided by the embodiment of the utility model, which is described in detail as follows:

[0056] A timing signal waveform processing circuit includes: two waveform correctors, a differential operational amplifier circuit, a rising edge slope extraction module, and a rising edge extraction module;

[0057] The output ends of the two waveform correctors are electrically connected to the two input ends of the differential operational amplifier circuit respectively; the input end of the rising edge slope extraction module is electrically connected to the output end of the differential operational amplifier circuit; the input end of the rising edge extraction module is electrically connected to the output end of the differential operational amplifier circuit and the output end of the rising edge slope extraction module;

[0058] When a differential signal is input into the input ends of the two waveform correctors, the rising edge slope of the differential signal increases. The differential signal with increased slope is converted into a level signal by the differential operational amplifier circuit and then sent to the rising edge slope extraction module to obtain a slope signal. The rising edge extraction module generates a rectangular wave signal based on the level signal and the slope signal.

[0059] For example, Figure 1 As shown, the embodiment of the present invention first performs waveform correction on the two differential signal input terminals of RS485. The correction principle is to filter out some high-frequency signals to reduce the noise of the signal. The rising edge slope of the signal after filtering out the noise will increase to a certain extent. The corrected signal is sent to the differential operational amplifier circuit and converted into a level signal. This level signal then passes through the rising edge slope extraction module to extract the slope of the rising edge of the level signal. This slope is then converted into a trigger signal through the rising edge extraction module. Since this trigger signal is extracted based on the rising edge of the timing signal, the response timeliness and timing accuracy are greatly improved. In some application scenarios, it is used to connect to the interrupt terminal of the processor to trigger the interrupt handler of the processor.

[0060] The embodiment of the present invention is provided with a signal correction module, which improves the slope of the rising edge to a certain extent. After the corrected signal is amplified by the differential operational amplifier circuit, the slope of the rising edge in the signal is extracted, and the rising edge is extracted as the base point for time positioning based on the slope of the rising edge and the signal amplitude. Therefore, the timing is determined to be the same as the timing of each bit approaching the transmitting end, and the time calibration is more accurate.

[0061] In some embodiments, the two waveform correctors respectively include: a first resistor, a second resistor, a third resistor, a first capacitor, and a first operational amplifier;

[0062] The inverting input terminal of the first operational amplifier is electrically connected to the second terminal of the first resistor and the first terminal of the third resistor;

[0063] The positive input terminal of the first operational amplifier is electrically connected to the second end of the second resistor and the first end of the first capacitor; the output terminal of the first operational amplifier is electrically connected to the second end of the third resistor;

[0064] A first end of the first resistor and a second end of the first capacitor are grounded.

[0065] For example, Figure 2 As shown, two waveform correctors are used to input signals from terminals A and B, respectively. They include a first resistor R101, a second resistor R102, a third resistor R103, a first capacitor C101, and a first operational amplifier U1. High-frequency components in the signal are bypassed to ground via the first capacitor C101, while low-frequency components pass through, resulting in waveform correction.

[0066] In some embodiments, the differential operational amplifier circuit includes: a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a second operational amplifier;

[0067] The second end of the fourth resistor and the second end of the fifth resistor are electrically connected to the inverting input terminal of the second operational amplifier and the positive input terminal of the second operational amplifier respectively;

[0068] Two ends of the seventh resistor are connected to the ground and the positive input terminal of the second operational amplifier respectively;

[0069] Two ends of the sixth resistor are electrically connected to the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier respectively;

[0070] The first end of the fourth resistor and the first end of the fifth resistor are electrically connected to the two waveform corrector output ends respectively.

[0071] For example, Figure 3 As shown, the differential operational amplifier circuit is used to convert the corrected A-end signal and B-end signal into level signals. The circuit includes: a fourth resistor R201, a fifth resistor R202, a sixth resistor R203, a seventh resistor R204 and a second operational amplifier U2. The circuit outputs a TTL level signal.

[0072] In some embodiments, the rising edge slope extraction module includes: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a second capacitor, and a third operational amplifier;

[0073] The inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the second capacitor and the first terminal of the eleventh resistor; the output terminal of the third operational amplifier is electrically connected to the second terminal of the eleventh resistor;

[0074] The second end of the eighth resistor is electrically connected to the first end of the second capacitor;

[0075] The positive input terminal of the third operational amplifier is electrically connected to the second end of the ninth resistor and the first end of the tenth resistor;

[0076] The first end of the ninth resistor and the second end of the tenth resistor are connected to the positive electrode of the power supply and the ground respectively;

[0077] The first end of the eighth resistor is electrically connected to the output end of the differential operational amplifier circuit.

[0078] For example, Figure 4 As shown, the rising edge slope extraction module is used to extract the rising edge slope of the signal, including: an eighth resistor R301, a ninth resistor R302, a tenth resistor R303, an eleventh resistor R304, a second capacitor C301, and a third operational amplifier U3. The level signal obtained above generates a current flowing through the eighth resistor R301 to the second capacitor C301. According to the principle of virtual short circuit and virtual open circuit of an ideal operational amplifier, this current is the same as that flowing to the eleventh resistor R304. The power supply of the inverting input terminal of the third operational amplifier U3 is the voltage divided by the ninth resistor R302 and the tenth resistor R303. Therefore, the third operational amplifier U3 outputs a value of the extracted level voltage slope.

[0079] This circuit extracts the voltage slope. Since the slope is extracted from the rising edge of the signal, the extraction speed is significantly faster than the way of judging the level change, which improves the response speed to the signal.

[0080] In some embodiments, the rising edge extraction module includes: a level signal amplitude sampling circuit and a fourth operational amplifier;

[0081] The output terminal of the level signal amplitude sampling circuit is electrically connected to the positive input terminal of the fourth operational amplifier;

[0082] The inverting input terminal of the fourth operational amplifier is electrically connected to the output terminal of the rising edge slope extraction module.

[0083] In some embodiments, the level signal amplitude sampling circuit includes: a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a third capacitor, a fourth capacitor, a first transistor, and a second transistor;

[0084] The base and collector of the first transistor are electrically connected to the output terminal of the differential operational amplifier circuit and the positive electrode of the power supply, respectively; the emitter of the first transistor is electrically connected to the collector of the second transistor and the first end of the twelfth resistor;

[0085] Two ends of the third capacitor are electrically connected to the second end of the twelfth resistor and the first end of the fourth capacitor respectively, and the second end of the fourth capacitor is grounded;

[0086] The first end of the fourth capacitor is electrically connected to the positive input terminal of the fourth operational amplifier;

[0087] Two ends of the thirteenth resistor are electrically connected to the emitter of the second transistor and the ground respectively;

[0088] Two ends of the fourteenth resistor are electrically connected to the base of the second transistor and the output end of the differential operational amplifier circuit respectively.

[0089] For example, Figure 5 As shown, the rising edge extraction module is used to determine the rising edge signal based on the voltage of the level and the slope of the rising edge, including: a level signal amplitude sampling circuit and a fourth operational amplifier U4, wherein the level signal amplitude sampling circuit includes: a twelfth resistor R401, a thirteenth resistor R402, a fourteenth resistor R403, a third capacitor C401, a fourth capacitor C402, a first transistor Q1, and a second transistor Q2. When the level signal arrives, the first transistor Q1 and the second transistor Q2 are both turned on, so that the voltage of the level stored in the third capacitor C401 and the fourth capacitor C402 is proportional to the voltage of the previous pulse amplitude. In addition, the fourth capacitor C402 divides the voltage according to the capacitance of the third capacitor C401 and the fourth capacitor C402, so that the voltage of the fourth capacitor C402 is proportional to the voltage of the previous pulse amplitude. This voltage is compared with the output of the third operational amplifier U3. When the output of the third operational amplifier U3 is higher than this voltage, the fourth operational amplifier U4 does not output; otherwise, it outputs the power supply voltage.

[0090] Because the output of the third operational amplifier U3 is negatively correlated with the rising edge slope of the level signal (the greater the slope, the lower the output voltage of the third operational amplifier U3), when the rising edge of the level signal arrives, the fourth operational amplifier U4 outputs a power supply voltage. This voltage is used to indicate the start of time calibration and is generally connected to the interrupt trigger terminal of the processor to inform the processor of the timing and enter the time calibration preparation procedure.

[0091] The rising edge extraction module can prevent false triggering and adjust the trigger timing according to the amplitude of the TTL level signal. For example, when the amplitude is low, the corresponding rising edge slope during triggering will also become smaller, allowing the timing opportunity to be captured more sensitively.

[0092] In some embodiments, the timing signal waveform processing circuit further includes: a digital signal extraction module;

[0093] The two input terminals of the digital signal extraction module are electrically connected to the output terminal of the rising edge extraction module and the output terminal of the differential operational amplifier circuit respectively;

[0094] When the two input terminals of the digital signal extraction module input the level signal and the rectangular wave signal respectively, the digital signal extraction module outputs a high level signal or a low level signal according to the level signal and the rectangular wave signal.

[0095] In some embodiments, the digital signal extraction module includes: a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a fifth capacitor, a diode, and a third transistor;

[0096] The base of the third transistor and the emitter of the third transistor are electrically connected to the second end of the fifteenth resistor and the first end of the sixteenth resistor respectively, the first end of the fifteenth resistor is electrically connected to the output end of the rising edge extraction module, and the second end of the sixteenth resistor is grounded;

[0097] The first end of the fifth capacitor and the cathode of the diode are electrically connected to the collector of the third transistor, and the second end of the fifth capacitor is grounded;

[0098] Two ends of the seventeenth resistor are electrically connected to the output end of the differential operational amplifier circuit and the anode of the diode respectively.

[0099] For example, in addition, some scenarios are also provided with a module for identifying code elements based on the high-level width: a digital signal extraction module, which includes: a fifteenth resistor R501, a sixteenth resistor R502, a seventeenth resistor R503, a fifth capacitor C501, a diode D1 and a third transistor Q3. When the TTL level is high, the diode D1, through the seventeenth resistor R503 and the fifth capacitor C501, latches the voltage charged by the TTL level to the fifth capacitor C501 during the high-level period. When the rising edge arrives, the charge of the fifth capacitor C501 is released through the fifteenth resistor R501, the collector and emitter of the third transistor Q3 and the sixteenth resistor R502. After the rising edge ends, the third transistor Q3 is cut off again to recharge the fifth capacitor C501. The charged voltage is the voltage charged to the fifth capacitor C501 during the high-level period. In other words, the voltage of the fifth capacitor C501 is proportional to the length of the TTL level in the high-level period, thereby achieving the purpose of converting the pulse width into a digital signal.

[0100] It should be understood that the size of the serial numbers of each step in the above embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present utility model.

[0101] The following is an embodiment of the device of the present invention. For details not described in detail, please refer to the corresponding method embodiment described above.

Claims

1. A timing signal waveform processing circuit, characterized in that: include: Two waveform correctors, a differential operational amplifier circuit, a rising edge slope extraction module, and a rising edge extraction module; The output ends of the two waveform correctors are electrically connected to the two input ends of the differential operational amplifier circuit respectively; the input end of the rising edge slope extraction module is electrically connected to the output end of the differential operational amplifier circuit; the input end of the rising edge extraction module is electrically connected to the output end of the differential operational amplifier circuit and the output end of the rising edge slope extraction module; When a differential signal is input into the input ends of the two waveform correctors, the rising edge slope of the differential signal increases. The differential signal with increased slope is converted into a level signal by the differential operational amplifier circuit and then sent to the rising edge slope extraction module to obtain a slope signal. The rising edge extraction module generates a rectangular wave signal based on the level signal and the slope signal.

2. The timing signal waveform processing circuit according to claim 1, wherein: The two waveform correctors respectively include: a first resistor, a second resistor, a third resistor, a first capacitor and a first operational amplifier; The inverting input terminal of the first operational amplifier is electrically connected to the second end of the first resistor and the first end of the third resistor; The positive input terminal of the first operational amplifier is electrically connected to the second end of the second resistor and the first end of the first capacitor; the output terminal of the first operational amplifier is electrically connected to the second end of the third resistor; A first end of the first resistor and a second end of the first capacitor are grounded.

3. The timing signal waveform processing circuit according to claim 1, wherein: The differential operational amplifier circuit includes: a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a second operational amplifier; The second end of the fourth resistor and the second end of the fifth resistor are electrically connected to the inverting input terminal of the second operational amplifier and the positive input terminal of the second operational amplifier respectively; Two ends of the seventh resistor are connected to the ground and the positive input terminal of the second operational amplifier respectively; Two ends of the sixth resistor are electrically connected to the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier respectively; The first end of the fourth resistor and the first end of the fifth resistor are electrically connected to the two waveform corrector output ends respectively.

4. The timing signal waveform processing circuit according to claim 1, wherein: The rising edge slope extraction module includes: an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a second capacitor and a third operational amplifier; The inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the second capacitor and the first terminal of the eleventh resistor; the output terminal of the third operational amplifier is electrically connected to the second terminal of the eleventh resistor; The second end of the eighth resistor is electrically connected to the first end of the second capacitor; The positive input terminal of the third operational amplifier is electrically connected to the second end of the ninth resistor and the first end of the tenth resistor; The first end of the ninth resistor and the second end of the tenth resistor are connected to the positive electrode of the power supply and the ground respectively; The first end of the eighth resistor is electrically connected to the output end of the differential operational amplifier circuit.

5. The timing signal waveform processing circuit according to claim 1, wherein: The rising edge extraction module includes: a level signal amplitude sampling circuit and a fourth operational amplifier; The output terminal of the level signal amplitude sampling circuit is electrically connected to the positive input terminal of the fourth operational amplifier; The inverting input terminal of the fourth operational amplifier is electrically connected to the output terminal of the rising edge slope extraction module.

6. The timing signal waveform processing circuit according to claim 5, characterized in that: The level signal amplitude sampling circuit includes: a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a third capacitor, a fourth capacitor, a first transistor and a second transistor; The base and collector of the first transistor are electrically connected to the output terminal of the differential operational amplifier circuit and the positive electrode of the power supply, respectively; the emitter of the first transistor is electrically connected to the collector of the second transistor and the first end of the twelfth resistor; Two ends of the third capacitor are electrically connected to the second end of the twelfth resistor and the first end of the fourth capacitor respectively, and the second end of the fourth capacitor is grounded; The first end of the fourth capacitor is electrically connected to the positive input terminal of the fourth operational amplifier; Two ends of the thirteenth resistor are electrically connected to the emitter of the second transistor and the ground respectively; Two ends of the fourteenth resistor are electrically connected to the base of the second transistor and the output end of the differential operational amplifier circuit respectively.

7. The timing signal waveform processing circuit according to any one of claims 1 to 5, characterized in that: The timing signal waveform processing circuit further includes: a digital signal extraction module; The two input terminals of the digital signal extraction module are electrically connected to the output terminal of the rising edge extraction module and the output terminal of the differential operational amplifier circuit respectively; When the two input terminals of the digital signal extraction module input the level signal and the rectangular wave signal respectively, the digital signal extraction module outputs a high level signal or a low level signal according to the level signal and the rectangular wave signal.

8. The timing signal waveform processing circuit according to claim 7, wherein: The digital signal extraction module includes: a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a fifth capacitor, a diode, and a third transistor; The base of the third transistor and the emitter of the third transistor are electrically connected to the second end of the fifteenth resistor and the first end of the sixteenth resistor respectively, the first end of the fifteenth resistor is electrically connected to the output end of the rising edge extraction module, and the second end of the sixteenth resistor is grounded; The first end of the fifth capacitor and the cathode of the diode are electrically connected to the collector of the third transistor, and the second end of the fifth capacitor is grounded; Two ends of the seventeenth resistor are electrically connected to the output end of the differential operational amplifier circuit and the anode of the diode respectively.

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