MOSFET test circuit
By integrating inductive branches, auxiliary test device branches and short circuit branches on the same circuit board, the control switch realizes multi-performance testing, solving the problem of increasing time and cost per test board replacement in MOSFET test, improving testing efficiency and reducing management complexity.
Patent Information
- Application Number
- CN202421504975.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-08-29
- Estimated Expiration
- 2034-06-27
AI Technical Summary
When performing performance testing of MOSFETs in the prior art, each test board replacement will increase a lot of time and cost, and it is difficult to manage and store the test board.
Design a MOSFET test circuit that integrates inductive branch, auxiliary test device branch, short-circuit branch and drive signal module. By controlling the disconnection and connection of the switch, multiple performance tests are implemented on the same circuit board, including double pulse, avalanche and short-circuit tests.
Reduces testing time and cost, improves testing efficiency, simplifies the management of test equipment, and reduces the complexity of multiple performance testing.
Smart Images
Figure CN223284330U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of MOSFET testing, in particular to a MOSFET testing circuit. Background Art
[0002] In the field of semiconductor device testing technology, especially the testing of MOSFET (metal oxide semiconductor field effect transistor), it is a very important link, because MOSFET is an important electronic switching device, and its performance directly affects the performance of electronic equipment. In practical applications, MOSFET needs to be subjected to various performance tests, such as double pulse switching capability test, avalanche test and short circuit test, to ensure that it meets the design requirements.
[0003] Currently, when performing performance tests on MOSFET tubes, it is usually necessary to replace different test boards to perform different performance tests. For example, if a dual-pulse switching capability test is to be performed, the device under test needs to be connected to a dedicated dual-pulse test circuit; if an avalanche test is to be performed, the device under test needs to be connected to a dedicated avalanche test circuit; if a short-circuit test is to be performed, the device under test needs to be connected to a dedicated short-circuit test circuit. Although comprehensive testing of MOSFETs can be achieved by replacing different test boards, each replacement of the test board will increase a lot of time and cost, and the test efficiency is low. Utility Model Content
[0004] In view of the deficiencies in the prior art, the present invention provides a MOSFET test circuit, which solves the problem in the prior art that each replacement of a test board increases a lot of time and cost.
[0005] According to an embodiment of the present invention, a MOSFET test circuit includes:
[0006] An inductor branch, an auxiliary test device branch, a short-circuit branch and a drive signal module are provided. A first switch K1 and a second switch K2 are provided on the inductor branch and the auxiliary test device branch respectively. One end of the inductor branch is connected to the power supply VCC, and the other end of the inductor branch is connected to the drain of the device under test Q2. The inductor branch is connected in parallel with the auxiliary test device branch and the short-circuit branch respectively. The drive signal module is connected to the gate of the device under test Q2, and the source of the device under test Q2 is grounded.
[0007] Preferably, a capacitor C is provided between the source of the device under test Q2 and the power supply VCC.
[0008] Preferably, the inductor branch includes: an inductor L, one end of the inductor L is connected to one end of the second switch K2, the other end of the inductor L is connected to the power supply VCC, and the other end of the second switch K2 is connected to the drain of the device under test Q2.
[0009] Preferably, the auxiliary test device branch includes: an auxiliary test device Q1, the drain of the auxiliary test device Q1 is connected to the power supply VCC, the source of the auxiliary test device Q1 is connected to one end of the first switch K1, the other end of the first switch K1 is connected to the drain of the device under test Q2, and the gate and source of the auxiliary test device Q1 are short-circuited.
[0010] Preferably, the short-circuit branch includes: a third switch K3 , one end of the third switch K3 is connected to the drain of the device under test Q2 , and the other end of the third switch K3 is connected to the power supply VCC.
[0011] Preferably, the drain and gate of the device under test Q2 are both connected to differential probes.
[0012] Preferably, the source of the device under test Q2 is connected to a current probe.
[0013] Preferably, the method further includes: the device under test Q2 is arranged on a test fixture, the first interface and the second interface of the test fixture are connected to the drive signal module and the inductor branch respectively, and the third interface of the test fixture is grounded.
[0014] Preferably, the first interface, the second interface and the third interface of the test fixture are all connected to the gate, the drain and the source of the device under test Q2 through ejector pins.
[0015] Preferably, the inductor branch, the auxiliary test device branch, the short-circuit branch, the capacitor C and the drive signal module are integrated on the same circuit board.
[0016] Compared with the prior art, the present invention has the following beneficial effects: by respectively controlling the disconnection and connection of the first switch, the second switch and the third switch, and integrating the multi-performance switching test circuit and the capacitor on the same circuit board, the multi-performance switching test circuit can be switched to different test circuits, thereby solving the problem of increased time cost and test equipment cost each time the test board is replaced for different performance tests; at the same time, it solves the problem that each test board is independent and a large number of test boards need to be stored and managed, which increases the difficulty and cost of management; and multiple performance tests of MOSFET are realized on one test platform, and the test circuit provided by the present invention can at least perform double pulse test, short circuit test and avalanche test on MOSFET, which can reduce test time and cost and improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 This is a circuit diagram of an embodiment of the present utility model. DETAILED DESCRIPTION
[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the utility model for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The technical solutions in the present invention are further explained below in conjunction with the drawings and embodiments.
[0019] like Figure 1 As shown, the embodiment of the present utility model provides a MOSFET test circuit, comprising:
[0020] An inductor branch, an auxiliary test device branch, a short-circuit branch and a drive signal module are provided. A first switch K1 and a second switch K2 are provided on the inductor branch and the auxiliary test device branch respectively. One end of the inductor branch is connected to the power supply VCC, and the other end of the inductor branch is connected to the drain of the device under test Q2. The inductor branch is connected in parallel with the auxiliary test device branch and the short-circuit branch respectively. The drive signal module is connected to the gate of the device under test Q2, and the source of the device under test Q2 is grounded.
[0021] When the first switch K1 and the second switch K2 are closed and the third switch K3 is disconnected, a double pulse test of the MOSFET is implemented; when the second switch K2 is closed and the first switch K1 and the third switch K3 are disconnected, an avalanche test of the MOSFET is implemented; when the third switch K3 is closed and the first switch K1 and the second switch K2 are disconnected, a short circuit test of the MOSFET is implemented. Therefore, the present invention realizes the testing of various performances of the MOSFET by cooperating with fewer components. Compared with the prior art of independently testing the performance of the MOSFET, the test circuit provided by the present invention greatly reduces the testing cost.
[0022] As an optional technical solution, a capacitor C is provided between the source of the device under test Q2 and the power supply VCC. Capacitor C acts as a filter, absorbing the spike voltage generated during the test and eliminating the spike voltage caused by the stray inductance of the busbar, thus avoiding damage to the device and making the output waveform more stable, thereby ensuring the accuracy and reliability of the test results.
[0023] As an optional technical solution, the inductor branch includes an inductor L, one end of which is connected to one end of the second switch K2, the other end of which is connected to the power supply VCC, and the other end of the second switch K2 is connected to the drain of the device under test Q2. During the MOSFET testing process of the present invention, the power supply VCC in the circuit charges the inductor and performs performance testing in conjunction with components such as a differential probe. At the same time, the inductor L also acts as a load to regulate the output current, thereby observing the switching state of the device under test at different currents.
[0024] As an optional technical solution, the auxiliary test device branch includes an auxiliary test device Q1, the drain of which is connected to the power supply VCC, the source of which is connected to one end of a first switch K1, the other end of which is connected to the drain of the device under test Q2, and the gate and source of the auxiliary test device Q1 are short-circuited. When the test device is turned off, the inductor current cannot change suddenly. In this case, the current in the inductor L continues to be released after the test device is turned off. At this time, the GS (gate and source) of the auxiliary test device are short-circuited, forming a discharge loop between the parasitic diode of the MOSFET and the inductor, consuming the energy released by the inductor and preventing the released energy from breaking down the device under test.
[0025] As an optional technical solution, the short-circuit branch includes a third switch K3 , one end of the third switch K3 is connected to the drain of the device under test Q2 , and the other end of the third switch K3 is connected to the power supply VCC.
[0026] As an optional technical solution, the drain and gate of the device under test Q2 are connected to differential probes, which respectively capture the VDS and VGS conditions of the device under test Q2; the source of the device under test Q2 is connected to a current probe for capturing and detecting the current conditions.
[0027] In the test circuit of the present invention, the device under test Q2 is arranged on a test fixture, a first interface and a second interface of the test fixture are connected to the drive signal module and the inductor branch respectively, and a third interface of the test fixture is grounded.
[0028] The first interface, second interface and third interface of the test fixture are all connected to the gate, drain and source of the device under test Q2 through ejector pins; the inductor branch, auxiliary test device branch, short-circuit branch, capacitor C and drive signal module are integrated on the same circuit board; the device under test Q2 is installed on the test fixture, so that the test fixture is respectively connected to the drain, source and gate of the device under test Q2 through ejector pins, which facilitates the quick replacement of the device under test Q2 for testing.
[0029] The test circuit described in the utility model;
[0030] Specifically, during the actual test process of the present invention, when the first switch K1 and the second switch K2 are closed and the third switch K3 is opened, the driving signal module generates a double pulse waveform, and controls the on and off of the device under test Q2 through high and low levels. At this time, the device under test Q2 is a double pulse test circuit. By setting a differential probe to capture the VDS and VGS of the device under test Q2 respectively, and the current probe to capture the source outflow current Is of the device under test Q2, which is the parameter for testing the switching time of the device under test Q2, the double pulse test is completed.
[0031] When the second switch K2 is closed and the first switch K1 and the third switch K3 are opened, the drive signal module generates a single pulse waveform, and the high and low levels are used to control the on and off of the device. When the single pulse is high, the Q2 device is turned on and charges the inductor L. When the single pulse is low, the device under test Q2 is turned off, and the energy stored in the inductor L is discharged at this time. The high level time of the pulse is controlled to control the magnitude of the current and the avalanche energy impacting the device under test Q2. The differential probe captures the VDS and VGS of the device under test Q2 respectively, and the current probe captures the source outflow current Is of the device under test Q2 to perform an avalanche test on the device under test Q2.
[0032] When the third switch K3 is closed and the first switch K1 and the second switch K2 are opened, the drive signal module generates a single pulse waveform, and controls the on and off of the device under test Q2 through high and low levels. When the single pulse is high, the device under test Q2 is turned on, and when the single pulse is low, the device under test Q2 is turned off. The high level time is controlled to control the short-circuit time of the device under test Q2, testing the short-circuit capability of the device under test Q2. The differential probe captures the VDS and VGS of the device under test Q2 respectively, and the current probe captures the source outflow current Is of the device to perform a short-circuit test on the device under test Q2.
[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model and are not limiting. Although the utility model is described in detail with reference to the preferred embodiments, ordinary technicians in this field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.
Claims
1. A MOSFET test circuit, characterized in that: include: An inductor branch, an auxiliary test device branch, a short-circuit branch and a drive signal module are provided. A first switch K1 and a second switch K2 are provided on the inductor branch and the auxiliary test device branch respectively. One end of the inductor branch is connected to the power supply VCC, and the other end of the inductor branch is connected to the drain of the device under test Q2. The inductor branch is connected in parallel with the auxiliary test device branch and the short-circuit branch respectively. The drive signal module is connected to the gate of the device under test Q2, and the source of the device under test Q2 is grounded.
2. A MOSFET test circuit as claimed in claim 1, characterized in that: A capacitor C is provided between the source of the device under test Q2 and the power supply VCC.
3. A MOSFET test circuit as claimed in claim 1, characterized in that: The inductor branch includes an inductor L, one end of the inductor L is connected to one end of the second switch K2, the other end of the inductor L is connected to the power supply VCC, and the other end of the second switch K2 is connected to the drain of the device under test Q2.
4. A MOSFET test circuit as claimed in claim 1, characterized in that: The auxiliary test device branch includes: an auxiliary test device Q1, the drain of the auxiliary test device Q1 is connected to the power supply VCC, the source of the auxiliary test device Q1 is connected to one end of the first switch K1, the other end of the first switch K1 is connected to the drain of the device under test Q2, and the gate and source of the auxiliary test device Q1 are short-circuited.
5. A MOSFET test circuit as claimed in claim 1, characterized in that: The short-circuit branch includes a third switch K3 , one end of the third switch K3 is connected to the drain of the device under test Q2 , and the other end of the third switch K3 is connected to the power supply VCC.
6. A MOSFET test circuit as claimed in claim 1, characterized in that: The drain and gate of the device under test Q2 are both connected to differential probes.
7. A MOSFET test circuit as claimed in claim 1, characterized in that: The source of the device under test Q2 is connected to a current probe.
8. A MOSFET test circuit according to any one of claims 1 to 7, characterized in that: Also includes: The device under test Q2 is arranged on a test fixture, a first interface and a second interface of the test fixture are connected to the driving signal module and the inductor branch respectively, and a third interface of the test fixture is grounded.
9. A MOSFET test circuit as claimed in claim 8, characterized in that: The first interface, the second interface and the third interface of the test fixture are all connected to the gate, the drain and the source of the device under test Q2 through ejector pins.
10. A MOSFET test circuit according to any one of claims 1 to 7, characterized in that: The inductor branch, the auxiliary test device branch, the short-circuit branch, the capacitor C and the drive signal module are integrated on the same circuit board.