Memory device

Abstract

A memory device includes a substrate having a front side and a back side opposite to the front side. An interconnect structure is on or over the substrate and has a first metal layer and a second metal layer and a via electrically connecting the first metal layer and the second metal layer. A word line driver circuit is used for outputting a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit for receiving a word line signal and an enable transistor electrically connected to an output of the inverter circuit by a metal wire including the first metal layer, the second metal layer, and the via.

Description

Technical Field

[0001] The present disclosure relates to a device, and more particularly to a memory device. Background Art

[0002] A common type of integrated circuit memory is a static random access memory (SRAM) device. A typical SRAM memory device has an array of memory cells. In some instances, each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (typically ground) so that one of the two storage nodes can be occupied by the information to be stored, with complementary information stored at the other storage node. Each bit in the SRAM cell is stored in four of the transistors, which form two cross-coupled inverters. The other two transistors are connected to the memory cell word line to control access to the memory cell during read and write operations by selectively connecting the cell to its bit line. In a read operation, for example, the memory cell bit line is precharged to a predetermined threshold voltage. When the word line is enabled, a sense amplifier connected to the bit line senses and outputs the stored information. Utility Model Content

[0003] According to one aspect of the present disclosure, a memory device includes: a substrate having a front side and a back side opposite the front side; an interconnect structure located on or above the substrate, the interconnect structure including a first metal layer and a second metal layer and a via electrically interconnecting the first metal layer and the second metal layer; and a word line driver circuit for outputting a word line enable signal to a word line of a memory array, the word line driver circuit including an inverter circuit for receiving a word line signal and an enable transistor, the enable transistor being electrically connected to an output of the inverter circuit by a metal connection including the first metal layer, the second metal layer, and the via.

[0004] According to another aspect of the present disclosure, a memory device includes: a memory array comprising a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines connected to the plurality of memory cells in a plurality of respective rows of the memory array; and a word line driver circuit for outputting a plurality of word line enable signals to the plurality of respective word lines, the word line driver circuit comprising: a substrate; an interconnect structure located on or above the substrate; and a plurality of inverter circuits and a plurality of enable transistors electrically connected to respective word lines of the plurality of word lines by a plurality of metal wires of the interconnect structure, wherein each of the plurality of metal wires has a uniform length.

[0005] According to another aspect of the present disclosure, a memory device includes: a substrate having a front side and a back side opposite the front side; a word line driver circuit for outputting a word line enable signal to a word line of a memory array in or on the substrate, the word line driver circuit including an inverter circuit and an enable transistor; a metal connection electrically connecting the inverter circuit, the enable transistor, and the word line, wherein the metal connection includes: an inter-layer via extending through the substrate; a front side interconnect structure disposed on or above the front side of the substrate; and a back side interconnect structure disposed on or above the back side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The disclosed aspect is in the accompanying Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram illustrating an example of a memory device according to some embodiments;

[0008] Figure 2 is a circuit diagram illustrating an example of an SRAM memory cell according to some embodiments;

[0009] Figure 3 FIGURE 1 is a diagram illustrating some embodiments of the present invention. Figure 1 Circuit diagrams of other aspects of the memory device;

[0010] Figure 4 is a circuit diagram illustrating an example of a word line driver circuit according to some embodiments;

[0011] Figure 5 is a top view illustrating an example of a FinFET structure according to some embodiments;

[0012] Figure 6 is a block diagram illustrating aspects of a word line driver circuit according to some embodiments;

[0013] Figure 7 is a block diagram illustrating an example of a semiconductor device according to some embodiments;

[0014] Figure 8 is a block diagram illustrating another example of a semiconductor device according to an embodiment;

[0015] Figure 9 is a block diagram illustrating another example of a word line driver circuit according to some embodiments;

[0016] Figure 10is a block diagram illustrating another example of a word line driver circuit according to some embodiments;

[0017] Figure 11 is a flow chart illustrating an example of a method according to some embodiments.

[0018]

Explanation of symbols

[0019] 100:Memory device

[0020] 104: word line driver

[0021] 110: memory cell array

[0022] 112: Input / Output (IO) block

[0023] 120: Control block

[0024] 200: memory unit

[0025] 202: Word Line

[0026] 203: complementary bit line BL

[0027] 204:Bit line bar / BLB

[0028] 206a: Access transistor / "pass gate" transistor / NMOS transistor

[0029] 206b: Access transistor / NMOS transistor

[0030] 206c to 206d: access transistors

[0031] 208a-208b: PMOS transistors

[0032] 210a: output node

[0033] 210b: output node

[0034] 220: Inverter

[0035] 221:PMOS transistor

[0036] 222:NMOS transistor

[0037] 224: Enable PMOS transistor

[0038] 230: After adding resistance

[0039] 232:Metal wiring / conductive wiring

[0040] 232a: Part 1

[0041] 232b: Part 2

[0042] 232c: Part 3

[0043] 234: Active Device

[0044] 250:FinFET

[0045] 252: Fins

[0046] 254: Gate finger

[0047] 260:Substrate

[0048] 261:Front-side interconnection structure

[0049] 262: Backside interconnection structure

[0050] 264:Interlayer via

[0051] 270: First substrate or layer

[0052] 272: Second substrate or layer

[0053] 300: Method

[0054] 310: Operation

[0055] 312: Operation

[0056] 314: Operation

[0057] 316: Operation

[0058] ADDR: address signal

[0059] RAS: row select signal

[0060] VDD: Upper reference voltage terminal

[0061] VSS: Lower reference voltage terminal

[0062] WL0~WLN: word lines

[0063] WLB: word line bar signal

[0064] WL: word line enable signal DETAILED DESCRIPTION

[0065] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0066] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0067] Various disclosed embodiments relate to a wordline driver circuit for an SRAM memory that provides memory read assist. The wordline driver circuit includes wordline suppression to improve memory cell static noise margin (SNM), while also providing power reduction and improved performance, even under temperature variations. The driver circuit includes added resistance formed by external metal interconnects connecting components of the wordline driver circuit to the wordlines. In some examples, the metal interconnects are formed in multiple metal layers and / or interconnect structures to provide metal interconnects of increased length. The longer metal interconnects increase resistance, suppressing wordline voltage while also improving performance at both high and low temperatures.

[0068] Figure 1 FIG. 1 is a block diagram illustrating an example of a memory device 100 according to an aspect of the present disclosure. Figure 1In the illustrated embodiment of the present invention, the memory device 100 includes a memory cell array 110 comprising an array of memory cells. In the examples disclosed herein, the memory cells are SRAM cells, although other implementations, such as dynamic random access memory (DRAM) cells are possible. The memory array 110 is connected between an upper reference voltage terminal VDD and a lower reference voltage terminal VSS (typically ground). The memory device 100 further includes an input / output (IO) block 112 for reading data from and writing data to the memory array 110. The word line driver 104 outputs a row select signal to select a row of memory cells based on a received address signal ADDR to read or write data. The control block 120 is connected to the word line driver 104 and the IO block 112. In Figure 1 In the illustrated embodiment of FIG, although each element is depicted as a separate block for illustration purposes, in some other embodiments, Figure 1 Some or all of the elements shown may be integrated together.

[0069] In some embodiments, each memory cell uses six transistors connected between an upper reference potential, VDD, and a lower reference potential, VSS, so that one of the two storage nodes can be occupied by the information to be stored, with complementary information stored at the other storage node. Each bit in the SRAM cell is stored in four of the transistors, which form two cross-coupled inverters. The other two transistors are connected to the memory cell word line to control access to the memory cell during read and write operations by selectively connecting the cell to its bit line. During a read operation, when the appropriate word line is enabled by the word line driver 104, the sense amplifier of the IO block 112 connected to the bit line senses and outputs the stored information.

[0070] Figure 2 The diagram is shown in Figure 1 2. Memory cell 200 is an example of a memory cell array 110 in FIG. Memory cell 200 is connected to word line 202 and complementary bit lines BL 203 and BLB 204. Memory cell 200 includes PMOS transistors 208a-208b and NMOS transistors 206a-206d. Transistors 208a-206c are coupled to each other and positioned between supply voltage VDD and ground to form an inverter. Similarly, transistors 208b and 206d are coupled between VDD and ground to form a second inverter.

[0071] The two inverters are cross-coupled to each other. Access or "pass gate" transistor 206a connects the output of the first inverter to bit line BL 203 in response to word line enable signal WL output by word line driver 104. Similarly, access transistor 206b connects the output of the second inverter to bit line bar 204. Word line 202 is responsive to the word line enable signal WL shown in FIG. Figure 1 The word line driver 104 in FIG. 1 is attached to the gate control terminals of access transistors 206a and 206b during read / write operations to selectively couple the outputs of the inverters to bit lines 203, 204. During a read operation, the inverters drive complementary voltage levels at bit lines 203, 204.

[0072] The cross-coupled inverters of memory cell 200 provide two stable voltage states indicating logic values ​​0 and 1. Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) are typically used as transistors in memory cell 200. In some embodiments, more than six or less than six transistors may be used to implement memory cell 200.

[0073] Figure 3 Other aspects of the memory device 100 are shown. In some embodiments, the memory cell array 110 includes a plurality of memory cells 200 arranged in a column-row configuration, in which each column has a bit line 203 and a bit line bar 204, and each row has a word line 202. More specifically, the bit lines 203 and 204 of each column are respectively coupled to the plurality of memory cells 200 disposed in the column, and each memory cell 200 in the column is arranged in a different row and coupled to a respective (different) word line 202. That is, each memory cell 200 in the memory cell array 110 is coupled to the bit line 203 of the column of the memory cell array 110, the bit line bar 204 of the column of the memory cell array 110, and the word line 202 of the row of the memory cell array 110. In some embodiments, the bit lines 203 and the bit line bars 204 are arranged in parallel in the vertical direction, and the word lines 202 are arranged in parallel in the horizontal direction (ie, perpendicular to the bit lines 203 and 204). Figure 3 In the example of , there are n columns and m rows of memory cells 200 in array 110 .

[0074] In some embodiments, during a read cycle, both bit lines 203 and 204 are precharged to a high (logic 1) voltage, typically at or near VDD. In response to an enable signal output by control block 120, a word line signal WL is output by word line driver 104 to select the desired word line 202 of memory cell 200. Asserting word line 202 activates access transistors 206a and 206b of memory cell 200, which are coupled to the selected word line 202. This causes the voltage signal on one of bit lines 203 and 204 to drop slightly. Bit lines 203 and 204 will then have a small voltage difference between them. The sense amplifier of IO block 112 senses which of bit lines 203 and 204 has the higher voltage and, therefore, determines whether memory cell 200 is storing a 1 or a 0. During a write cycle, the value to be written to memory cell 200 is received by the IO block. The desired word line 202 is asserted in response to a select signal output by the word line driver 104 based on an enable signal from the control block 120 .

[0075] Static noise margin (SNM) is a measure of how well an SRAM cell, such as SRAM memory cell 200, can maintain its binary state when the SRAM memory cell is disturbed or disrupted. In other words, SNM is the maximum amount of static voltage noise that the SRAM cell can withstand without changing state. A change in state can corrupt the data stored in the SRAM cell.

[0076] One example of an SRAM failure is the switching of the state of an SRAM cell during a read operation. The read operation of an SRAM cell is due to the voltage distribution along the wordline driver and through the gate transistor, which causes the internal node storing the zero data value to rise. When the rise exceeds a threshold, it is due to regenerative positive feedback, resulting in a bit flip and thus loss of the stored data.

[0077] Consider drawing Figure 2 FIG. 2 is a read zero (0) operation of the SRAM cell 200 in which a zero data value is read from the output node 210 a to the BL 203. Correspondingly, a complementary high or one (1) data value is stored at the output node 210 b. Due to the activation of both the lower NMOS transistor 206 c and the pass-gate transistor 206 a, a resistive voltage drop occurs at the output node 210 a of the SRAM cell 200.

[0078] If the magnitude of the voltage drop at node 210a is high enough to turn on NMOS transistor 206b, the data 1 stored at node 210b will be lost. Because of the back-to-back connection of the inverters of SRAM cell 200, a regeneration action occurs and output node 210a may be pulled high, thereby causing the destruction of the data stored in SRAM cell 200. If the word line voltage is reduced, the voltage at node 210a is also reduced during a read operation.

[0079] If the wordline voltage is reduced, the voltage at the SRAM output node is also reduced during a read operation. Some conventional approaches reduce the wordline voltage by using a wordline suppressor circuit. This wordline suppressor circuit attenuates the pass-gate transistors 206a / 206b, reducing the voltage drop across the pass-gate transistors 206a / 206b and the voltage drop between the pass-gate transistors 206a / 206b and their associated driver transistors 206c / 206d, thereby increasing the SNM. Therefore, when the relative level of the wordline is reduced compared to the bitline supply voltage VDD, the read operation of the memory cell is improved. This results in an increased SNM of the SRAM and, therefore, provides a more stable read operation.

[0080] In some embodiments, the reduction of the word line voltage (ie, word line inhibition) is achieved through a charge sharing arrangement. Figure 4 An example of a word line driver 104 according to the present disclosure is shown. The illustrated word line driver 104 includes a PMOS transistor 221 and an NMOS transistor 222 connected between a supply voltage terminal VDD and ground as an inverter 220. More specifically, a first source / drain terminal of the PMOS transistor 221 is connected to the VDD terminal, and a first source / drain terminal of the NMOS transistor 222 is connected to ground. The output node of the inverter 220 is formed at the junction of the second source / drain terminals of the PMOS transistor 221 and the NMOS transistor 222.

[0081] The enable PMOS transistor 224 is connected between the output of the inverter 220 formed by the transistors 221 and 222 and the ground. More specifically, the first source / drain terminal of the enable transistor 224 is connected to the output of the inverter 220, and the second source / drain terminal of the enable transistor 224 is connected to the ground. Figure 1 ), the word line bar signal WLB is received at the gate terminals of transistors 221 , 222 (ie, the input of inverter 220 ), and the row select signal RAS is received by enabling transistor 224 .

[0082] Some disclosed embodiments utilize a charge-sharing configuration for wordline inhibition facilitated by PMOS transistor 221 and enable PMOS transistor 224. While some conventional wordline inhibition circuits reduce the wordline voltage to improve SNM and thereby operate at a lower cell supply voltage, SRAM cell operation speed may be affected. Additionally, increased power consumption may occur due to "crowbar" current between the wordline driver and the wordline inhibition activator.

[0083] Conventional circuits attempt to address this issue by increasing the size of the enable or pull-down transistor 224. For example, in some embodiments, transistor 224 (and the other transistors shown) are fin field-effect transistors (FinFETs), which are three-dimensional structures on the surface of a semiconductor substrate. Fins extend upward from the main body of the substrate and can be formed by depositing fin material on the substrate, etching non-fin areas of the substrate, or a combination thereof. The channel of the FinFET is formed in this vertical fin, and conductive gate strips or "fingers" are provided above the fin (e.g., wrapping the fin). Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from both sides.

[0084] Increasing the size of the enable transistor 224 (ie, increasing the number of gate fingers) can result in a reduction in the word line voltage level. However, this can increase power consumption and also affect the operating speed of the SRAM. Figure 5 An example of portions of a FinFET 250 that can be used to implement transistor 224 is shown. In the illustrated example, FinFET 250 has three fins 252 extending horizontally (i.e., in the y-direction) and multiple gate fingers 254 extending vertically (i.e., in the x-direction). In some known word line suppression configurations, enable transistor 224 is implemented with an increased size FinFET having, for example, 14 to 20 or more fingers.

[0085] The disclosed embodiments provide word line suppression and temperature immunity while saving power and maintaining SRAM speed. Figure 4 The word line driver 104 in FIG. 1 further includes an added resistor 230 formed by increasing the length of a metal connection 232 connecting the output of the inverter 220, the enable transistor 224, and the word line 202. The added resistor 230 allows for achieving desired word line suppression while using a smaller FinFET 250 for the enable transistor 224. For example, in some examples, the enable transistor has fewer than ten fingers 254, with some examples having seven fingers 254.

[0086] In some embodiments, added resistance 230 is a metal resistance created by increasing the length of the metal wire connecting inverter 220 and enable transistor 224. Depending on temperature (discussed further below), added resistance 230 is 200-400 ohms in some examples. Figure 6 A plan view of portions of an example of an example wordline driver 104 is conceptually illustrated, illustrating a plurality of wordlines 202 , including wordlines WL0 through WLN. Figure 6 Further illustrated is a PMOS transistor 221 and an enable transistor 224 of inverter 220. As will be discussed further below, a conductive metal connection 232 connecting PMOS transistor 221 and enable transistor 224 has an increased length to provide added resistance 230. In some examples, conductive metal connection 232 includes various metal layers along with conductive vias. Each of the enable PMOS transistors 224 is positioned adjacent to a corresponding PMOS transistor 221. In some examples, a fin 252 forming the enable PMOS transistor 224 is directly adjacent to a fin 252 forming the corresponding PMOS transistor 221.

[0087] In some examples, device 100 includes an interconnect structure formed over a substrate. Figure 7 To conceptually illustrate a block diagram of an example memory device 100, memory device 100 includes a substrate 260 having active devices 234, such as transistors 221, 222, and 224, formed in or on substrate 260. An interconnect structure 261 is formed over substrate 260 and devices 234. Interconnect structure 261 may include various metal layers, such as those forming device interconnects, power delivery networks, IO pins, and the like. Interconnect structure 261 may include conductive wiring and conductive vias interconnecting multiple conductive wiring layers, including metal deposition, conductive vias, M0 to Mn connections, and the like, each of which may be formed over one or more stacked dielectric layers. The conductive wiring may include copper, aluminum, tungsten, tantalum, titanium, nickel, cobalt, metal silicides, metal nitrides, polysilicon, combinations thereof, and / or other materials that may include one or more layers or liners. Conductive vias may extend through respective ones of the dielectric layers to provide vertical interconnection between the layers of conductive wiring, and through the substrate to electrically connect the front-side interconnect structure and the back-side interconnect structure.

[0088] The interconnect structure 261 provides metal wiring 232, which interconnects the metal wiring 232. Figure 4 In the example shown in FIG. 2 , transistors 221, 222, and 224 are shown in addition to other transistors. Figure 4In the example of FIG, the distance between word line 202 and inverter 220 (i.e., PMOS transistor 221) and corresponding enable transistor 224 varies depending on the relative positioning of word line 202 and PMOS transistors 221 and 224 in memory array 110. To increase the length of metal line 232 to form added resistance 230 and provide a metal interconnect line of uniform length and, in turn, a uniform added resistance 230, metal line 232 may include multiple segments or portions formed from different metal layers and vias of interconnect structure 261. For example, metal line 232 may include a first portion 232a in a first metal layer of interconnect structure 261, a second portion 232b in a second metal layer of interconnect structure 261, and a third portion 232c including one or more vias 236 interconnecting the various metal layers of interconnect structure 261 and device 234. By extending the length of the metal connector 232 by including the first portion 232a, the second portion 232b, and the third portion 232c in different metal layers and vias, the resistance is increased, which reduces the wordline signal voltage. The lower wordline voltage in turn improves the SRAM cell SNM.

[0089] Furthermore, in order to provide consistent added resistance 230 between the various metal wires 232, the metal wires 232 are constructed using the interconnect structure 261 to have similar lengths and therefore consistent resistance 230. Figure 6 As shown in FIG, positioning the enable transistor 224 close to the corresponding PMOS transistor 221 further provides a balanced RC network formed by the metal connection 232.

[0090] Figure 8 1. The memory device 100 includes a word line driver circuit 104. The memory device 100 includes a substrate 260 having a front side and a back side opposite the front side. Figure 8 , interconnect structure 261 is a front-side interconnect structure located on or above the front side of substrate 260, and back-side interconnect structure 262 is located on or above the back side of substrate 260. Interlayer vias 264 extend through substrate 260 and electrically connect front-side interconnect structure 261 and back-side interconnect structure 262.

[0091] As discussed above, the word line driver 104 includes an inverter 220 formed by a PMOS transistor 221 and an NMOS transistor 222. The PMOS transistor 224 is enabled and connected to the output of the inverter 220 by a conductive connection, such as a metal connection 232, which includes a first portion 232a in the front-side interconnect structure 261. Figure 9In the embodiment, second portion 232b is in backside interconnect structure 262, and third portion 232c is one or more vias 264 interconnecting front-side interconnect structure 261 and back-side interconnect structure 262. By extending the length of metal connector 232 by including first portion 232a in front-side interconnect structure 261, second portion 232b in back-side interconnect structure 262, and third portion 232c in via 264, resistance 230 is increased, which reduces wordline signal voltage. Lower wordline voltage improves SRAM cell SNM.

[0092] Other embodiments use three-dimensional integrated circuits (3DICs), in which multiple semiconductor dies are interconnected and packaged together to form an integrated circuit device. In some of these integrated circuit devices, the semiconductor dies are arranged edge-to-edge, while others are stacked vertically. Such devices achieve 3D integration at the packaging level, for example, by stacking separately manufactured wafers. Monolithic 3D approaches use two or more device tiers manufactured sequentially, with devices formed in each tier and connected using through-silicon vias (TSVs).

[0093] Figure 10 The diagram shows an example of a word line driver circuit 104 formed in a 3DIC device. In some embodiments, multiple semiconductor dies are stacked, with wire bonding, flip chip bonding, and / or through-silicon-vias (TSVs) used to stack the dies together and connect the dies to the packaging substrate. Other embodiments use a monolithic 3DIC structure with multiple levels. More specifically, a monolithic 3D IC requires two or more layers of devices such as transistors that are sequentially manufactured and interconnected above a substrate. For example, starting with a first semiconductor substrate, the first layer of transistors is manufactured using conventional techniques. A donor substrate is then bonded to the first substrate, and a portion of the donor substrate is peeled off to leave a semiconductor film above the first layer of transistors. The second layer of transistors is then manufactured in the semiconductor film, and interlayer interconnects are formed between the transistor layers. Thus, a monolithic 3DIC may include one or more interlayer interconnects that extend between a first (e.g., lower) transistor or device layer and a second (e.g., upper) transistor or device layer in the monolithic 3DIC to provide vertical connections between the levels of the monolithic 3DIC circuit. Sometimes TSVs are used to implement inter-layer interconnects.

[0094] The illustrated example includes a first substrate or layer 270 having some active devices (e.g., transistors) of the word line driver circuit 104 and a second substrate or layer 272 having the remaining transistors of the word line driver circuit 104. Figure 10In the example of FIG. 2 , the PMOS transistor 221 of the inverter 220 is provided in the first level 270, while the NMOS transistor 222 and the enable transistor PMOS transistor 224 of the inverter 220 are provided in the second level 272. The conductive line 232 is again provided by a plurality of interconnect structures, such as a front-side interconnect structure 261, a back-side interconnect structure 262, and a via 264 to extend the length of the metal interconnect and thereby increase resistance.

[0095] As mentioned above, the conductive line 230 connecting the inverter 220 and the enable transistor 224 has an increased length to increase resistance, which in turn increases the SNL of the SRAM cell 200. The resistance of the metal line changes depending on the temperature. For example, in some embodiments, the resistance of the conductive line 230 decreases by 10% at a low temperature (e.g., -40°C) compared to a higher temperature (e.g., 125°C).

[0096] Typically, devices using larger enable transistors may experience SNM failure issues at high temperatures, while memory speed may be reduced at low temperatures. However, the added resistance provided by the increased length of conductive link 232 varies with temperature, as mentioned above. Therefore, at low temperatures, the added resistance 230 decreases, which increases the wordline voltage to improve memory speed.

[0097] Thus, using increased metal resistance 230 and smaller transistors 224 (eg, smaller gate fingers) due to increased length of metal line 232 provides the desired suppression of word line voltage levels. Furthermore, the added resistance 230 improves speed and performance at low temperatures in response to temperature changes.

[0098] Figure 11 FIG is a flow chart illustrating an example of a method 300 according to an aspect of the present disclosure. Figure 11 With the previous drawings discussed above, Figure 11 Method 300 includes providing a substrate 260 at operation 310. Substrate 260 has a front side and a back side opposite the front side. At operation 312, active devices 234 (e.g., transistors 221 and 222) of word line driver circuit 104 are formed in or on substrate 260. Word line driver circuit 104 is configured to output a word line enable signal to word line 202 of memory array 110. As described above, word line driver circuit 104 includes inverter circuit 220 having transistors 221 and 222, and enable transistor 224. At operation 314, enable transistor 224 is formed in or on the substrate.

[0099] At operation 316, an interconnect structure 261 is formed on or over substrate 260. Interconnect structure 261 has a plurality of metal layers 232a, 232b and vias 232c that electrically connect the metal layers. In some examples, the interconnect structure includes a front-side interconnect structure 261 formed on or over the front side of substrate 260 and a back-side interconnect structure 262 formed on or over the back side of substrate 260.

[0100] In some examples, operation 316 includes extending an interlayer via 264 through substrate 260, electrically connecting front-side interconnect structure 261 and back-side interconnect structure 262. Inverter circuit 220, enable transistor 224, and wordline 202 are electrically connected by metal wiring 232. As mentioned above, in some embodiments, metal wiring 232 is formed with at least a first portion 232a comprising a first metal layer, a second portion 232b comprising a second metal layer, and a via 232c. In other embodiments, metal wiring 232 includes front-side interconnect structure 261, back-side interconnect structure 262, and interlayer via 264. By forming metal wiring 232 in multiple metal layers and / or interconnect structures (i.e., front-side and back-side interconnect structures), including by adding metal resistor 230, this improves memory cell SNM to suppress wordline voltage, while also improving performance at both high and low temperatures.

[0101] Therefore, the present disclosure provides a memory circuit comprising a substrate having a front side and a back side opposite to the front side. An interconnect structure is located on or above the substrate and has a first metal layer and a second metal layer and a through hole electrically connecting the first metal layer and the second metal layer. A word line driver circuit is used to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit for receiving a word line signal and an enable transistor, the enable transistor being electrically connected to an output of the inverter circuit by a metal connection, the metal connection including the first metal layer, the second metal layer and the through hole. In some embodiments, the inverter circuit includes a first P-type metal oxide semiconductor transistor and a first N-type metal oxide semiconductor transistor, and wherein the output of the inverter circuit is formed at a junction surface between the first P-type metal oxide semiconductor transistor and the first N-type metal oxide semiconductor transistor. In some embodiments, the enable transistor includes a second P-type metal oxide semiconductor transistor. In some embodiments, the enable transistor is a fin field effect transistor. In some embodiments, the FinFET includes less than 10 gate fingers. In some embodiments, the FinFET includes 7 gate fingers. In some embodiments, the metal wiring has a resistance greater than 200 ohms. In some embodiments, the metal wiring has a resistance of 200 ohms to 400 ohms. In some embodiments, the interconnect structure includes a front-side interconnect structure located on or above the front side of the substrate, a back-side interconnect structure located on or above the back side of the substrate, and an interlayer via extending through the substrate and electrically connecting the front-side interconnect structure and the back-side interconnect structure, and wherein the metal wiring includes the front-side interconnect structure, the back-side interconnect structure, and the interlayer via. In some embodiments, the memory device further includes a first layer and a second layer, wherein at least one of the first P-type metal oxide semiconductor transistor, the first N-type metal oxide semiconductor transistor and / or the second P-type metal oxide semiconductor transistor is in the first layer, and wherein at least one of the first P-type metal oxide semiconductor transistor, the first N-type metal oxide semiconductor transistor and / or the second P-type metal oxide semiconductor transistor is in the second layer.

[0102] According to other disclosed embodiments, a memory device includes a memory array having a plurality of memory cells arranged in a plurality of rows and columns. A plurality of word lines are connected to the plurality of memory cells in respective rows of the memory array. A word line driver circuit is used to output a plurality of word line enable signals to the plurality of respective word lines and includes a substrate, an interconnect structure located on or above the substrate, a plurality of inverter circuits, and a plurality of enable transistors electrically connected to the respective word lines of the plurality of word lines by a plurality of metal wires of the interconnect structure. Each of the plurality of metal wires has a uniform length. In some embodiments, the plurality of memory cells are a plurality of SRAM cells. In some embodiments, the interconnect structure includes a first metal layer and a second metal layer and a through-hole electrically connecting the first metal layer and the second metal layer, and wherein the plurality of metal wires include the first metal layer, the second metal layer, and the through-hole. In some embodiments, the interconnect structure includes a front-side interconnect structure located on or above a front side of the substrate, a back-side interconnect structure located on or above a back side of the substrate opposite to the front side, and an interlayer via extending through the substrate and electrically connecting the front-side interconnect structure and the back-side interconnect structure, and wherein the plurality of metal wirings include the front-side interconnect structure, the back-side interconnect structure, and the interlayer via. In some embodiments, the memory device further includes a first level and a second level, wherein: the multiple inverter circuits each include a first P-type metal oxide semiconductor transistor and a first N-type metal oxide semiconductor transistor; the multiple enable transistors each include a second P-type metal oxide semiconductor transistor; an output of the inverter circuit is formed at a junction interface between the first P-type metal oxide semiconductor transistor and the first N-type metal oxide semiconductor transistor; and wherein at least one of the first P-type metal oxide semiconductor transistor, the first N-type metal oxide semiconductor transistor and / or the second P-type metal oxide semiconductor transistor is in the first level, and wherein at least one of the first P-type metal oxide semiconductor transistor, the first N-type metal oxide semiconductor transistor and / or the second P-type metal oxide semiconductor transistor is in the second level.

[0103] According to further disclosed embodiments, a method for forming a memory circuit includes providing a substrate having a front side and a back side opposite the front side. An active device of a word line driver circuit for outputting a word line enable signal to a word line of a memory array is formed in or on the substrate. The word line driver circuit includes an inverter circuit and an enable transistor. An interlayer via is formed extending through the substrate. A front-side interconnect structure is formed on or above the front side of the substrate, and a back-side interconnect structure is formed on the back side of the substrate. The inverter circuit, the enable transistor, and the word line are electrically connected by a metal wiring, the metal wiring including the front-side interconnect structure, the back-side interconnect structure, and the interlayer via. In some embodiments, the step of forming the front-side interconnect structure includes the steps of forming a first metal layer and a second metal layer and a via electrically connecting the first metal layer and the second metal layer, wherein the metal wiring includes the first metal layer and the second metal layer and the via. In some embodiments, the plurality of active devices of the inverter circuit include a first P-type metal oxide semiconductor transistor and a first N-type metal oxide semiconductor transistor, and wherein the enable transistor includes a P-type metal oxide semiconductor transistor. In some embodiments, the enable transistor is a FinFET having less than 10 fingers. In some embodiments, the step of providing the substrate further includes the step of providing a substrate having a first layer and a second layer, wherein at least one of the first P-type metal oxide semiconductor transistor, the first N-type metal oxide semiconductor transistor, and / or the second P-type metal oxide semiconductor transistor is in the first layer, and wherein at least one of the first P-type metal oxide semiconductor transistor, the first N-type metal oxide semiconductor transistor, and / or the second P-type metal oxide semiconductor transistor is in the second layer.

[0104] In one embodiment, a memory device includes: a substrate having a front side and a back side opposite the front side; a word line driver circuit for outputting a word line enable signal to a word line of a memory array in or on the substrate, the word line driver circuit including an inverter circuit and an enable transistor; a metal connection electrically connecting the inverter circuit, the enable transistor, and the word line, wherein the metal connection includes: an inter-layer via extending through the substrate; a front side interconnect structure disposed on or above the front side of the substrate; and a back side interconnect structure disposed on or above the back side of the substrate.

[0105] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and replacements may be made herein for such equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that: Include: a substrate having a front side and a back side opposite to the front side; an interconnect structure located on or above the substrate, the interconnect structure comprising a first metal layer, a second metal layer, and a through hole electrically interconnecting the first metal layer and the second metal layer; and A word line driver circuit is provided for outputting a word line enable signal to a word line of a memory array. The word line driver circuit includes an inverter circuit for receiving a word line signal and an enable transistor. The enable transistor is electrically connected to an output of the inverter circuit by a metal connection. The metal connection includes the first metal layer, the second metal layer, and the through-hole.

2. The memory device according to claim 1, wherein The inverter circuit includes a first P-type metal oxide semiconductor transistor and a first N-type metal oxide semiconductor transistor, wherein the output of the inverter circuit is formed at a junction interface between the first P-type metal oxide semiconductor transistor and the first N-type metal oxide semiconductor transistor.

3. The memory device according to claim 2, wherein: The enabling transistor includes a second P-type metal oxide semiconductor transistor.

4. The memory device according to claim 3, wherein: The enabling transistor is a FinFET.

5. The memory device according to claim 3, wherein: The interconnect structure includes a front-side interconnect structure located on or above the front side of the substrate, a back-side interconnect structure located on or above the back side of the substrate, and an interlayer via extending through the substrate and electrically connecting the front-side interconnect structure and the back-side interconnect structure, wherein the metal wiring includes the front-side interconnect structure, the back-side interconnect structure, and the interlayer via.

6. The memory device according to claim 5, wherein: Further comprising a first level and a second level, wherein at least one of the first P-type metal oxide semiconductor transistor, the first N-type metal oxide semiconductor transistor and / or the second P-type metal oxide semiconductor transistor is in the first level, and wherein at least one of the first P-type metal oxide semiconductor transistor, the first N-type metal oxide semiconductor transistor and / or the second P-type metal oxide semiconductor transistor is in the second level.

7. A memory device, characterized in that: Include: a memory array comprising a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines connected to the plurality of memory cells in respective rows of the memory array; A word line driver circuit is configured to output a plurality of word line enable signals to a plurality of respective word lines, the word line driver circuit comprising: a substrate; an interconnect structure located on or over the substrate; and A plurality of inverter circuits and a plurality of enable transistors electrically connected to respective word lines of the plurality of word lines by a plurality of metal wires of the interconnect structure, wherein each of the plurality of metal wires has a uniform length.

8. The memory device according to claim 7, wherein: The plurality of memory cells are a plurality of SRAM cells.

9. The memory device according to claim 7, wherein: The interconnect structure includes a first metal layer, a second metal layer, and a through hole electrically connecting the first metal layer and the second metal layer, and the plurality of metal wirings include the first metal layer, the second metal layer, and the through hole.

10. A memory device, characterized in that: Include: a substrate having a front side and a back side opposite to the front side; a word line driver circuit for outputting a word line enable signal to a word line of a memory array in or on the substrate, the word line driver circuit comprising an inverter circuit and an enable transistor; a metal connection electrically connecting the inverter circuit, the enable transistor, and the word line, wherein the metal connection comprises: an inter-layer via extending through the substrate; a front-side interconnect structure disposed on or above the front side of the substrate; and A backside interconnect structure is disposed on or above the backside of the substrate.

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