Packaging structure for reducing cutting burrs

Abstract

The utility model discloses a packaging structure for reducing cutting burrs, the structure comprises a chip, a substrate and a plastic packaging material, the substrate is configured to comprise a first metal layer and a second metal layer, the second metal layer is configured to be connected with a chip pin, and the first metal layer is configured to be used for forming an exposed bonding pad; the plastic package material is configured to be used for carrying out plastic package on the chip and the substrate and is configured on one side opposite to the exposed bonding pad side of the substrate, the first metal layer is configured to be processed through a chemical plating process, and the chemical plating process is configured to be used for forming chemical nickel-plated palladium gold on the first metal layer.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a structure for reducing cutting burrs in Land Grid Array (LGA) packaging. Background Art

[0002] Semiconductor chip packaging can be divided into substrate-type packaging and frame-type packaging according to the different carriers. Substrate-type packaging mainly includes LGA (Land Grid Array), BGA (Ball Grid Array), PGA (Pin Grid Array), etc. Frame-type packaging mainly includes SOP (Small Outline Package), QFN (Quad Flat No-leads Package), QFP (Quad Flat Package), etc.

[0003] The functions of substrate-type packaged products are more complex, and the packaging process is relatively difficult. Among them, LGA packaging is mainly suitable for high-performance and high-frequency application scenarios, BGA packaging is mainly suitable for high-density and high-heat application scenarios, and PGA packaging is mainly suitable for high-speed transmission and low-power application scenarios. With the development of 5G communications, research on LGA packaging that requires high performance and high frequency has also been further developed.

[0004] The LGA chip packaging process includes the following steps: wafer thinning, wafer dicing, die bonding, bonding, plastic encapsulation, printing, finished product cutting, testing, and packaging. For LGA packaged chips, the wafer and substrate are the main raw materials. The substrate, also known as the printed circuit board (PCB), is primarily composed of a laminate of copper foil and resin. The outermost metal (copper) layers (upper and lower) of the substrate require surface treatment to ensure that the upper metal layer can connect to the chip and the lower metal layer can be mounted on other PCBs.

[0005] The wafer needs to be ground and thinned to a certain thickness, and then cut into single pieces using a laser or resin knife before it can be used for subsequent packaging.

[0006] The die bonding process involves attaching the cut chip to the substrate. Depending on the process, the die bonding process can be categorized as either wire bonding or flip-chip bonding. Wire bonding involves attaching the cut chip to the substrate and then bonding the chip to the substrate. Flip-chip bonding involves first forming bumps on the chip and then flipping the chip onto the substrate, connecting the bumps to the substrate. Both processes can be applied to LGA packaged products.

[0007] The plastic encapsulation step is a process step in which the chip and substrate are sealed together with resin materials to protect the chip and prevent water vapor from corroding the chip.

[0008] The finished product cutting step involves dicing the encapsulated chips into individual pieces. Each chip is a separate LGA packaged chip. Depending on the package size, the cutting method can be divided into tape cutting and jig cutting. Tape cutting involves attaching the entire encapsulated substrate to a sticky circular film and then cutting with a resin knife. Jig cutting involves directly cutting the entire substrate with a resin knife. Generally, tape cutting is used for chips sized 3mm*3mm or less; jig cutting is used for chips sized larger than 3mm*3mm.

[0009] There are two methods for surface treatment of exposed metal on a substrate: electroplating and chemical plating, each with its own advantages and disadvantages. Electroplating is characterized by a simple production process and a fast electroplating reaction speed; chemical plating is characterized by good uniformity of coating thickness, strong coating adhesion, low cost, and the absence of harmful substances, making it more environmentally friendly. Electroplating primarily involves nickel-gold plating, while chemical plating primarily involves nickel-palladium-gold plating. Nickel-gold plating involves first electroplating a layer of nickel and then a layer of gold on the exposed copper foil of the substrate. The nickel plating primarily prevents diffusion between the gold and copper. The electroplating process requires electroplating leads to plate the metal layer. Chemical nickel-palladium-gold plating involves depositing nickel and palladium separately on the exposed copper foil of the substrate through an oxidation-reduction reaction in a chemical solution, and then depositing gold through a gold immersion process. The role of palladium is to prevent corrosion of the nickel layer by the solution during the gold deposition process.

[0010] In LGA packaging, cutting burrs are often found on the edges of pads after the finished product cutting step. These burrs not only affect the appearance of the product, but also affect the product's mounting quality and reliability. The utility model provides an LGA packaging structure to reduce the cutting burrs that occur during the finished product cutting step, thereby improving the reliability of the finished chip. Utility Model Content

[0011] According to one aspect of the present disclosure, a packaging structure for reducing cutting burrs is provided, comprising a chip, a substrate and a molding material, wherein the substrate is configured to include a first metal layer and a second metal layer, the second metal layer is configured to be connected to the chip pins, and the first metal layer is configured to form an exposed pad; the molding material is configured to be used to mold the chip and the substrate, and is configured on a side opposite to the exposed pad side of the substrate, wherein the first metal layer is configured to be processed by a chemical plating process, wherein the chemical plating process is configured to form chemical nickel palladium gold plating on the first metal layer.

[0012] According to one aspect of the present disclosure, a packaging structure for reducing cutting burrs is provided, wherein the substrate further includes N metal layers between the first metal layer and the second metal layer, where N is a natural number.

[0013] According to one aspect of the present disclosure, a package structure for reducing cutting burrs is provided, wherein the substrate further includes a connecting through-hole configured to connect metal layers within the substrate.

[0014] According to one aspect of the present disclosure, a packaging structure for reducing cutting burrs is provided, wherein the second metal layer is configured to be processed by an electroless plating process, wherein the electroless plating process is configured to form electroless nickel palladium gold on the second metal layer.

[0015] According to one aspect of the present disclosure, a packaging structure for reducing cutting burrs is provided, wherein the second metal layer is configured to be processed by an electroplating process, wherein the electroplating process is configured to form electroplated nickel-gold on the second metal layer by electroplating leads.

[0016] According to an aspect of the present disclosure, a package structure for reducing cutting burrs is provided, wherein the second metal layer is configured to be processed by attaching an OSP film.

[0017] According to one aspect of the present disclosure, a packaging structure for reducing cutting burrs is provided, wherein the molding material is a resin material.

[0018] According to one aspect of the present disclosure, a packaging structure for reducing cutting burrs is provided, comprising a chip, a substrate and a molding material, wherein the substrate is configured to include a first metal layer and a second metal layer, the second metal layer is configured to be connected to the chip pin, the first metal layer is configured to form an exposed pad, and the first metal layer and the second metal layer are connected through connecting through-holes; the molding material is configured to mold the chip and the substrate, and is configured on a side opposite to the exposed pad side of the substrate, wherein the second metal layer is configured to set a plating lead in the second metal layer, and the first metal layer is configured to be electroplated through the plating lead and the connecting through-hole set in the second metal layer.

[0019] According to one aspect of the present disclosure, a packaging structure for reducing cutting burrs is provided, wherein the second metal layer is further configured to be processed by an electroless plating process, wherein the electroless plating process is configured to form electroless nickel palladium gold on the second metal layer.

[0020] According to one aspect of the present disclosure, a package structure for reducing cutting burrs is provided, wherein the second metal layer is further configured to be processed by attaching an OSP film. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other aspects, features and advantages of exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 This is a schematic diagram showing the appearance of the product on the LGA package pad side.

[0023] Figure 2 It is a schematic diagram showing the positional relationship between the internal structure of the substrate (internal circuit connections) and the chip;

[0024] Figure 3 It shows that along Figure 1 A cross-sectional view of the packaged chip along line AA;

[0025] Figure 4 is a schematic diagram showing a finished packaged chip after cutting generated by using a structure for reducing cutting burrs according to an embodiment of the present invention;

[0026] Figure 5 is a schematic diagram showing the positional relationship between the internal structure (internal circuit connection) of the substrate and the chip according to an embodiment of the present invention;

[0027] Figure 6 It shows that along Figure 4 A cross-sectional view of the packaged chip along line BB;

[0028] Figure 7 is a schematic diagram showing a finished packaged chip after cutting generated by using a structure for reducing cutting burrs according to another embodiment of the present invention;

[0029] Figure 8 is a schematic diagram showing the positional relationship between the internal structure (internal circuit connection) of a substrate and a chip according to another embodiment of the present invention;

[0030] Figure 9 It shows that along Figure 7 A cross-sectional view of the packaged chip along line CC in FIG; and

[0031] Figure 10 The invention shows a manufacturing process for reducing cutting burrs in packaged chips according to an embodiment of the invention. DETAILED DESCRIPTION

[0032] Before proceeding with the following detailed description, it may be helpful to set forth definitions of certain words and phrases used throughout this disclosure. The terms "include" and "comprising" and their derivatives mean including, but not limited to, including. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item from the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0033] Definitions for other specific words and phrases are provided throughout this disclosure. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0034] The various embodiments of the principles of the present disclosure in this patent application document are described below in conjunction with the accompanying drawings for illustration only and should not be interpreted as limiting the scope of the present disclosure in any way. It will be understood by those skilled in the art that the principles of the present disclosure can be implemented in any appropriately arranged system or device. In some cases, the actions described in the present disclosure can be performed in a different order and can still achieve the desired result. In addition, the process depicted in the accompanying drawings does not necessarily require the specific order shown or the sequential order to achieve the desired result. In a specific embodiment, multitasking and parallel processing may be advantageous.

[0035] The text and drawings are provided as examples only to aid understanding of the present disclosure. They should not be interpreted as limiting the scope of the claims appended hereto in any way. Throughout the drawings, the same reference numerals generally indicate the same elements. Although certain embodiments and examples have been provided, it will be clear to those skilled in the art based on the contents of this disclosure that the illustrated embodiments and examples may be modified without departing from the scope of this disclosure.

[0036] Figure 1 This is a schematic diagram showing the appearance of the product on the LGA package pad side. Figure 1 The packaged chip 100 has an LGA package cutting finished product outer contour 102 and a chip exposed pad 103; in addition, there are cutting burrs 101 connected to the chip exposed pad 103, and the cutting burrs 101 are generated in the finished product cutting step, and there are obvious cutting burrs 101 on one side of the cutting path of all chip exposed pads 103.

[0037] Figure 2 This is a schematic diagram showing the positional relationship between the internal structure of the substrate (internal circuit connections) and the chip.

[0038] refer to Figure 2The packaged chip 200 comprises: electroplated leads 208, a cut-out outer contour 202, exposed pads 203, connecting vias 204, a second layer of copper 205, bumps 206, and a chip 207. Electroplated leads 208 and exposed pads 203 are configured as the first layer of copper; bumps 206 are configured as bumps connecting the second layer of copper to the chip; and chip 207 is the chip inside the package.

[0039] Because the first layer of copper is surface-treated through electroplating, the plating leads 208 connect to all exposed pads 203, forming a circuit path for the electroplating operation. After the substrate is cut along a certain width of cutting lanes, the remaining portion becomes the main body of the LGA package chip. The cutting width must completely include the width of the plating leads 208. At the same time, a portion of the plating leads extending toward the pads must also be cut. The remaining plating leads that are not completely cut away will form cutting burrs.

[0040] Figure 3 It shows that along Figure 1 Cross-sectional view of the packaged chip along line AA.

[0041] refer to Figure 3 The packaged chip 300 includes: cutting burrs 301, molding material 309, exposed pads 303, connecting through holes 304, a second layer of copper 305, bumps 306 and a chip 307.

[0042] One side of the electroplated lead is connected to the exposed pad 303 and is therefore located inside the substrate, while the other side is exposed outside the substrate. During the cutting step, the copper layer is subjected to unstable force, which causes the blade to curl and generate cutting burrs 301.

[0043] The cutting burrs on the edge of the pad are caused by curling of the outermost electroplated lead during the cutting process. During the cutting step, the cutting tool used is configured as a resin material, and the electroplated lead is configured as a copper material. Since copper has low hardness and good toughness, if the upper and lower layers of copper are not fixed during cutting, curling will easily occur and produce cutting burrs. Since resin tools have been greatly improved in curling compared to metal tools, and the cutting parameters have been fully studied, the existence of the existing burr phenomenon shows that it is difficult to solve the existing cutting burr problem by improving the cutting process.

[0044] Figure 4 The figure is a schematic diagram showing a finished packaged chip after cutting generated by using a structure for reducing cutting burrs according to an embodiment of the present invention.

[0045] refer to Figure 4The packaged chip 400 has an LGA package cutting finished product outer contour 402 and an exposed pad 403 ; and there are no cutting burrs in the packaged chip 400 .

[0046] Figure 5 Schematic diagram showing the positional relationship between the internal structure (internal circuit connection) of the substrate and the chip according to an embodiment of the present invention.

[0047] refer to Figure 5 The packaged chip 500 has: a cut finished outer contour 502 , an exposed pad 503 , a connecting through hole 504 , a second layer of copper 505 , a bump 506 and a chip 507 .

[0048] Exposed pad 503 is configured as a first layer of copper, connected to second layer of copper 505 via connecting via 504; bump 506 is configured as a bump connecting the second layer of copper to the chip; chip 207 is the chip inside the package. The first layer of copper is configured to be surface-treated by chemical plating, wherein the plating thickness is configured as follows: Ni layer: 0.3-0.5μm; Pd layer: minimum 0.1μm; Au layer: minimum 0.1μm.

[0049] Figure 6 It shows that along Figure 4 Cross-sectional view of the packaged chip along line BB.

[0050] refer to Figure 6 The packaged chip 600 includes: a plastic encapsulation material 609 , an exposed pad 603 , a connecting through hole 604 , a second layer of copper 605 , a bump 606 and a chip 607 .

[0051] According to an embodiment of the present invention, chemical plating is used to perform surface treatment on the first layer of copper, thereby eliminating the need to introduce electroplating leads for the electroplating process, and thus preventing cutting burrs caused by the electroplating leads during the cutting step.

[0052] Although it is possible to consider applying a 0.1-0.3µm thick organic solderability film (OSP) to the first copper layer for surface treatment to avoid cutting burrs caused by electroplated leads, OSP film is not suitable for subsequent mounting of the package to the PCB board, so the first copper layer is not treated with OSP film.

[0053] According to an embodiment of the present invention, the second layer of copper may be configured to be surface-treated by one of chemical plating, electroplating, or OSP film treatment, and the treatment thereof may be separate from the treatment of the first layer of copper.

[0054] According to an embodiment of the present invention, the second layer of copper is preferably electrolessly plated or treated with an OSP film.

[0055] In addition, according to the embodiments of the present invention, copper metal traces are only formed in the internal space of the substrate, and there is no need to lead the copper traces to the outside of the packaged chip. The first layer of copper and the second layer of copper are interconnected through connecting through holes inside the substrate, and the second layer of copper is interconnected with the chip through bumps to achieve circuit interconnection. Therefore, the function of the chip is not affected.

[0056] Figure 7 The figure is a schematic diagram showing a finished packaged chip after cutting generated by using a structure for reducing cutting burrs according to another embodiment of the present invention.

[0057] refer to Figure 7 ,and Figure 4 Similar to the figure, the packaged chip 700 has an LGA package cutting finished product outer contour 702 and a chip exposed pad 703 ; and there is no cutting burr in the packaged chip 700 .

[0058] Figure 8 Schematic diagram showing the positional relationship between the internal structure (internal circuit connection) of a substrate and a chip according to another embodiment of the present invention.

[0059] refer to Figure 8 The packaged chip 800 has: a cut finished outer contour 802 , exposed pads 803 , connecting through-holes 804 , a second layer of copper 805 , bumps 806 , a chip 807 and electroplated leads 808 .

[0060] The exposed pad 803 is configured as a first layer of copper, connected to the second layer of copper 805 via a connecting via 804; the plated lead 808 is configured within the second layer of copper; the bump 506 is configured as a bump connecting the second layer of copper to the chip; and the chip 207 is the chip inside the package. The first layer of copper is configured to be electroplated through the plated leads 808 and the connecting via 804. The plating thickness is configured as follows: 2-8 μm for the Ni layer; and a minimum of 0.1 μm for the Au layer. The second layer of copper can be surface-treated by chemical plating, electroplating, or an OSP film. When the second layer of copper is electroplated, the plating thickness is configured as follows: 2-8 μm for the Ni layer; and a minimum of 0.1 μm for the Au layer. When the second layer of copper is treated by chemical plating, the plating thickness is configured as follows: 0.3-0.5 μm for the Ni layer; a minimum of 0.1 μm for the Pd layer; and a minimum of 0.1 μm for the Au layer.

[0061] According to an embodiment of the present invention, the second layer of copper is preferably electroplated or processed through an OSP film.

[0062] Figure 9 It shows that along Figure 7Cross-sectional view of the packaged chip along line CC.

[0063] refer to Figure 9 The packaged chip 900 includes: a plastic encapsulation material 909 , an exposed pad 903 , a connecting through hole 904 , a second layer of copper 905 , a bump 906 and a chip 907 .

[0064] According to an embodiment of the present invention, the first layer of copper (exposed pad 903) is configured to be electroplated by configuring a plating lead in the second layer of copper 905 to perform surface treatment, and the second layer of copper 905 is configured to be surface treated by one of chemical plating, electroplating or OSP film treatment.

[0065] According to one embodiment of the present invention, the surface treatment of the second copper layer 905 can be configured to be performed after the electroplating treatment of the first copper layer 903, ultimately forming a treated layer on the surface of the second copper layer 905 formed by chemical plating, electroplating, or OSP film attachment. According to this embodiment of the present invention, by transferring the electroplated leads from the first copper layer (pad layer) to the second copper layer (the copper layer inside the plastic-encapsulated chip), although the copper metal is cut during the cutting step, the upper and lower layers of the copper metal are pressed with resin material. Therefore, the copper metal will not be rolled during the cutting process, thereby avoiding the problem of burrs on the pad edges. In addition, because the electroplated leads are introduced into the second copper layer for electroplating, a larger area of ​​second copper is present in the finished packaged chip. Compared with the electroplated leads introduced into the first copper layer for electroplating, it is easier to dissipate heat from the chip outside the packaged chip, thereby further improving the chip's heat dissipation performance. In addition, since the residual copper rate of the first layer of copper is usually greater than the residual copper rate of the second layer of copper, according to an embodiment of the present invention, the second layer of copper is electroplated by introducing an electroplating lead into the second layer of copper, thereby increasing the residual copper rate of the second layer of copper. By configuring the residual copper rates of the first layer of copper and the second layer of copper to be close, the problem of substrate warping can be improved.

[0066] According to other embodiments of the present invention, the second copper layer can be surface treated with an organic solderability preservative (OSP). Using OSP to treat the second copper layer eliminates the risk of cutting burrs caused by electroplated leads. Furthermore, OSP treatment prevents oxidation of the second copper layer after surface treatment, further enhancing the stability of the packaged chip.

[0067] According to the embodiments of the present invention, the above examples are for illustrative purposes only and should not be understood as limiting the present invention. The above embodiments may be modified accordingly without departing from the scope of the present invention. For example, the first layer of copper and the second layer of copper may be formed by other metals such as aluminum. In addition, according to the embodiments of the present invention, in addition to the first layer of copper and the second layer of copper, an intermediate layer of metal may be present in the substrate, and the metal layers in the substrate are connected by connecting vias to transmit signals from the chip to the exposed pads.

[0068] Figure 10 The invention shows a manufacturing process for reducing cutting burrs in packaged chips according to an embodiment of the invention.

[0069] refer to Figure 10 According to an embodiment of the present invention, a production process for reducing cutting burrs in the process of forming a finished packaged chip is provided, comprising: in step S101, forming a substrate corresponding to the chip, and performing surface treatment on the substrate, wherein the substrate is configured with a first layer of copper and a second layer of copper, the second layer of copper is used to connect with the bumps of the chip, and the first layer of copper is configured to form an exposed pad. According to an embodiment of the present invention, the first layer of copper and the second layer of copper can be configured in one of the following ways: 1) the first layer of copper is configured to be surface-treated by chemical plating, and the second layer of copper is configured to be surface-treated by electroplating, chemical plating, or by attaching an OSP film; 2) the first layer of copper is configured to be surface-treated by a first layer of metal and a second layer of gold The connecting through holes between the metals and the electroplated leads configured in the second layer of copper are electroplated, and the second layer of copper is configured to be processed by electroplating, chemical plating, or by attaching an OSP film for surface treatment; in step S102, the chip is attached to the substrate to ensure that the pins of the chip are connected to the second layer of copper of the substrate through the bumps; in step S103, welding is performed to weld the chip and the substrate together, wherein the bumps of the chip are welded to the exposed metal of the substrate at 260°C under the action of solder paste and flux; in step S104, the welded chip and substrate are filled with a plastic packaging material, wherein the plastic packaging material is configured as a resin material; in step S105, the chip after being filled with the plastic packaging material is cut into finished products to form a packaged chip product.

[0070] Those skilled in the art will appreciate that the embodiments of the present invention may be modified as appropriate without departing from the scope of the present invention. In some cases, the actions described herein may be performed in a different order and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous. For example, after soldering, the first layer of copper may be electrolessly plated for surface treatment.

[0071] Those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and steps described herein can be implemented as hardware, software, or a combination of both. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. A skilled person may implement the described functionality in different ways for each specific application, but such design decisions should not be interpreted as causing a departure from the scope of this disclosure.

[0072] The above embodiments of the present disclosure are merely for ease of description and to help fully understand the present disclosure, and are not intended to limit the scope of the present disclosure. Therefore, it should be understood that, in addition to the above embodiments disclosed herein, all modifications and changes or modified and changed forms of the technical concept of the present disclosure fall within the scope of the present disclosure.

Claims

1. A packaging structure for reducing cutting burrs, comprising a chip, a substrate and a plastic packaging material, characterized in that: The substrate is configured to include a first metal layer and a second metal layer, the second metal layer is configured to be connected to a chip pin, and the first metal layer is configured to form an exposed pad; The molding material is configured to be used for molding the chip and the substrate, and is configured on a side opposite to the exposed pad side of the substrate. The first metal layer is configured to be processed by an electroless plating process configured to form electroless nickel palladium gold on the first metal layer.

2. The packaging structure for reducing cutting burrs according to claim 1, characterized in that: The substrate further includes N metal layers between the first metal layer and the second metal layer, where N is a natural number.

3. The packaging structure for reducing cutting burrs according to claim 2, characterized in that: The substrate further includes a connecting via configured to connect metal layers within the substrate.

4. The packaging structure for reducing cutting burrs according to claim 1, wherein: The second metal layer is configured to be processed by an electroless plating process configured to form electroless nickel palladium gold on the second metal layer.

5. The packaging structure for reducing cutting burrs according to claim 1, wherein: The second metal layer is configured to be processed by an electroplating process, and the electroplating process is configured to form electroplated nickel-gold on the second metal layer by electroplating leads.

6. The packaging structure for reducing cutting burrs according to claim 1, wherein: The second metal layer is configured to be processed by attaching an OSP film.

7. The packaging structure for reducing cutting burrs according to claim 1, characterized in that: The plastic packaging material is a resin material.

8. A packaging structure for reducing cutting burrs, comprising a chip, a substrate and a plastic packaging material, characterized in that: The substrate is configured to include a first metal layer and a second metal layer, the second metal layer is configured to be connected to a chip pin, the first metal layer is configured to form an exposed pad, and the first metal layer and the second metal layer are connected via a connecting through hole; The molding material is configured to be used for molding the chip and the substrate, and is configured on a side opposite to the exposed pad side of the substrate. The second metal layer is configured to provide a plating lead in the second metal layer, and the first metal layer is configured to be plated through the plating lead and the connection through-hole provided in the second metal layer.

9. The packaging structure for reducing cutting burrs according to claim 8, characterized in that: The second metal layer is further configured to be processed by an electroless plating process configured to form electroless nickel palladium gold on the second metal layer.

10. The packaging structure for reducing cutting burrs according to claim 8, wherein: The second metal layer is further configured to be processed by attaching an OSP film.

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