Bipolar three-phase inverter circuit with stable midpoint and driving circuit

Abstract

The utility model discloses a bipolar three-phase inverter circuit with a stable midpoint and a driving circuit, the circuit is configured to comprise a PMOS transistor Q1 and an NMOS transistor Q2, the G pole of the PMOS transistor Q1 is used for bias signal access, the S pole is used as a power supply end for power supply + access, and the D pole is connected with the D pole of the NMOS transistor Q2 and is used as the output end of the inverter circuit for load access; and the G pole of the NMOS tube Q2 is used for accessing a bias signal, and the S pole of the NMOS tube Q2 is used as a power supply end for accessing a power supply. According to the inverter circuit, the bipolar three-phase bridge combining the NMOS and the PMOS is used for naturally neutralizing midpoint voltage offset to a certain extent through complementary work, the midpoint voltage floating problem of the inverter circuit is effectively solved, and the stability and efficiency of the circuit are improved.

Description

Technical Field

[0001] The utility model belongs to the field of electronic circuits, and in particular relates to a midpoint-stable bipolar three-phase inverter circuit and a drive circuit. Background Art

[0002] In the existing technology, three-phase inverter circuits generally use NMOS as switching elements. The all-N-type MOSFET three-phase inverter bridge drive circuit will also have problems such as load imbalance, resulting in inconsistent currents in each phase, causing the instantaneous current flowing through the midpoint to be non-zero, thereby causing the midpoint voltage to float and offset.

[0003] In addition, N-type MOSFET needs to meet V GS >V TH The S-pole of the upper bridge NMOS and the D-pole of the lower bridge NMOS are connected to the output terminal together, which makes the S-pole voltage of the upper bridge NMOS unstable. In addition, the midpoint voltage fluctuates due to load imbalance, which further leads to the problem of voltage difference fluctuation between the upper bridge GS, thereby affecting the opening and closing of the upper bridge MOS, and ultimately reducing the circuit stability. Utility Model Content

[0004] In order to solve the problems existing in the prior art, the utility model provides a bipolar three-phase inverter circuit with a stable midpoint, which can effectively improve the midpoint voltage floating problem of the inverter circuit and improve the stability and efficiency of the circuit.

[0005] The inverter circuit provided by the present invention is configured to include a PMOS transistor Q1 and an NMOS transistor Q2. The G pole of the PMOS transistor Q1 is used for bias signal access, the S pole serves as a power supply terminal for power + access, and the D pole is connected to the D pole of the NMOS transistor Q2 and serves as the output terminal of the inverter circuit for load access; the G pole of the NMOS transistor Q2 is used for bias signal access, and the S pole serves as a power supply terminal for power - access.

[0006] Furthermore, the circuit is also configured to include a switch resistance selection circuit.

[0007] Furthermore, the switch resistor selection circuit includes a diode D2, a diode D1, a resistor R1, a resistor R2, a resistor R3, and a resistor R4. The cathode of the diode D2 is connected to the G terminal of the PMOS tube Q1, and the anode is connected to one end of the resistor R1. The other end of the resistor R1 is used for bias signal access. The anode of the diode D1 is connected to the G terminal of the NMOS tube Q2 via the resistor R4, and the cathode is used for bias signal access. One end of the resistor R2 is connected to the G terminal of the PMOS tube Q1, and the other end is connected to one end of the resistor R1 for bias signal access. One end of the resistor R3 is connected to the G terminal of the NMOS tube Q2, and the other end is connected to the cathode of the diode D1.

[0008] Furthermore, the circuit is also configured to include capacitors C5 and C6 for delaying gate voltage changes. The capacitor C5 is connected in series between the S pole and the G pole of the PMOS transistor Q1, and the capacitor C6 is connected in series between the S pole and the G pole of the NMOS transistor Q2.

[0009] Furthermore, the circuit is also configured to include resistors R5 and R6 for limiting transient current. The resistor R5 is connected in series between the S pole and the G pole of the PMOS transistor Q1, and the resistor R6 is connected in series between the S pole and the G pole of the NMOS transistor Q2.

[0010] Furthermore, the circuit is further configured to include a low-pass filter for smoothing the output voltage.

[0011] Furthermore, the circuit is further configured to include a capacitor C11 and a capacitor C12 located between the S pole of the PMOS transistor Q1 and the S pole of the NMOS transistor Q2.

[0012] The present invention also provides a driving circuit for driving the midpoint-stable bipolar three-phase inverter circuit provided by the present invention. The driving circuit is configured to include a main control chip U1 for generating a PWM signal and a driving chip U2 for amplifying the output of the main control chip U1; the output of the driving chip U2 is a bias signal.

[0013] Furthermore, the power supply end of the driver chip U2 is used for power supply + access, and the power supply end of the main control chip U1 is connected to the power output end of the driver chip U2; the driver chip U2 converts the connected power supply + into the working voltage of the main control chip U1 and connects it to the power supply end of the main control chip U1.

[0014] Furthermore, the circuit is also configured to include a filter capacitor for filtering out voltage spikes in the power supply + connected to the power supply terminal of the driver chip U2.

[0015] The beneficial effects of the present invention are as follows: the inverter circuit uses a bipolar three-phase bridge combining NMOS and PMOS to work complementary to each other, which naturally neutralizes the midpoint voltage offset to a certain extent, effectively improves the midpoint voltage floating problem of the inverter circuit, and improves the stability and efficiency of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application, the following briefly introduces the drawings required for or involved in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Without inventive work, other drawings can be obtained based on these drawings:

[0017] Figure 1A circuit schematic diagram of the inverter circuit provided by the utility model;

[0018] Figure 2 This is the input and output timing diagram of the driver chip in the driver circuit provided by the utility model. DETAILED DESCRIPTION

[0019] This section describes the present invention more fully with reference to the accompanying drawings, which show illustrative embodiments of the present invention. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted according to an idealized or very formal meaning unless specifically defined herein.

[0021] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0022] The "midpoint" described in this article refers to the output point of the inverter circuit ( Figure 1 Point A in the figure); "midpoint voltage" refers to the output voltage of the inverter circuit ( Figure 1 The voltage at point A in the equation is 0.

[0023] The "power + / VCC" described in this article refers to the positive power supply, and "power -" refers to the circuit ground.

[0024] The “bias signal” described in this article refers to the signal that turns on the MOS transistor.

[0025] Please refer to Figure 1 The midpoint-stable bipolar three-phase inverter circuit provided by the present invention is configured to include a PMOS transistor Q1 and an NMOS transistor Q2. The G pole of the PMOS transistor Q1 is used for bias signal access, the S pole serves as the power supply terminal HV+ for power + access, and the D pole is connected to the D pole of the NMOS transistor Q2 and serves as the output terminal of the inverter circuit for load access; the G pole of the NMOS transistor Q2 is used for bias signal access, and the S pole serves as the power supply terminal for power - access.

[0026] This inverter circuit uses P-type MOSFET as the upper bridge switch. The N-type MOSFET needs to meet V GS >V TH , P-type MOSFET needs to meet V GS <V TH The bipolar three-phase bridge combined with NMOS and PMOS works complementary. When the NMOS tube is turned on, the PMOS tube is turned off. The two do not affect each other. The output voltage of the inverter circuit is stable, and the midpoint voltage is stable.

[0027] To accelerate the charge and discharge speeds of the PMOS and NMOS transistors and improve switching speed, this inverter circuit is also equipped with a switch resistor selection circuit. This circuit includes diode D2, diode D1, resistor R1, resistor R2, resistor R3, and resistor R4. Diode D2's cathode is connected to the G terminal of the PMOS transistor Q1, and its anode is connected to one end of resistor R1. The other end of resistor R1 is used to input a bias signal. Diode D1's anode is connected to the G terminal of the NMOS transistor Q2 via resistor R4, and its cathode is used to input a bias signal. Resistor R2 has one end connected to the G terminal of the PMOS transistor Q1, and the other end connected to the end of resistor R1 used for bias signal input. Resistor R3 has one end connected to the G terminal of the NMOS transistor Q2, and the other end connected to the cathode of diode D1.

[0028] By utilizing the unidirectional conductivity of the diode, when the bias signal is connected to turn on the diode, resistors R1 and R2 / resistors R3 and R4 are connected in parallel, reducing the resistance on the G pole of the PMOS tube and the G pole of the NMOS tube, accelerating the charging and discharging speed, and improving the switching speed of the PMOS tube and NMOS tube; the diode and resistor form a freewheeling loop, which can limit the current spike caused by the discharge of the Miller capacitance of the MOS tube when the PMOS tube and NMOS tube are turned off, thereby protecting the MOS tube and reducing EMI.

[0029] It is understandable that the G terminals of the PMOS transistor Q1 and the NMOS transistor Q2 of this inverter circuit can be connected in series with only resistors R2 and R3 as turn-on resistors. By configuring different resistance values, different voltages can be generated at the G terminals to achieve the purpose of MOS transistor turn-on control.

[0030] Please refer to Figure 1 The inverter circuit also includes decoupling capacitors C5 and C6 for delaying the change of the G pole voltage. C5 is connected in series between the S pole and the G pole of the PMOS tube Q1, and C6 is connected in series between the S pole and the G pole of the NMOS tube Q2.

[0031] Please refer to Figure 1The inverter circuit further includes a resistor R5 connected in series between the S and G poles of the PMOS transistor Q1, and a resistor R6 connected in series between the S and G poles of the NMOS transistor Q2. The resistors R5 and R6 are used to limit possible transient currents. The resistors have a current-limiting function. When a transient current occurs, the resistors R5 and R6 limit the current, thereby achieving the purpose of limiting the transient current.

[0032] In order to smooth the output voltage of this circuit, this circuit also includes resistor R7, resistor R8, capacitor C8 and capacitor C9. Resistor R7 and capacitor C8, resistor R8 and capacitor C9 respectively form low-pass filters to filter out the voltage in the output voltage that meets the passband of the low-pass filter, so as to smooth the output voltage. The connection method of the low-pass filter is as follows: Figure 1 shown.

[0033] This circuit also includes capacitors C11 and C12, which are connected as follows Figure 1 As shown; capacitor C11 and capacitor C12 are energy storage capacitors, which ensure power supply stability and filter power supply noise.

[0034] The bias signal described in this article can be provided by a constant current source, a constant voltage source, a PWM pulse signal generated by a PWM pulse generator, or a drive signal provided by any existing MOS tube drive circuit. This article configures the drive circuit to generate a PWM signal as a bias signal to control the conduction and cutoff of the PMOS tube Q1 and the NMOS tube Q2. Please refer to Figure 1 The driving circuit includes: a main control chip U1 for generating a PWM signal and a driving chip U2 for amplifying the output of the main control chip U1; the output of the driving chip U2 is used as a bias signal.

[0035] In this drive circuit, the main control chip U1 can output PWM signals, and the driver chip U2 is used to amplify the low-voltage control signal output by U1 to the driving voltage level required by the MOSFET. Its working principle is: the HV+ terminal is connected to the power supply, the VCC terminal is connected to the power supply (the power supply provides the voltage required for U2 to work, such as 5V), and GND is the power supply -; the main control chip U1 outputs a pair of complementary PWM signals (such as Figure 2 As shown in the figure, when the signal input to the driver chip's HIN pin is low, HO outputs a high level of VCC, the voltage difference between Q1's GS terminals is 0V, and Q1 is off. At the same time, the signal input to the driver chip's LIN pin is high, LO outputs a high level of +11V, the voltage difference between Q2's GS terminals is +11V, and Q2 is on. When the signal input to the driver chip's HIN pin is high, HO outputs a low level of VCC-11V, a voltage difference of -11V is formed between Q1's GS terminals, and Q1 is on. At the same time, the signal input to the driver chip's LIN pin is low, LO outputs a low level of 0V, the voltage difference between Q2's GS terminals is 0V, and Q2 is off.

[0036] The above control realizes the on / off of MOSFET in the upper and lower bridge arms, realizes the control of three-phase AC output, and can generate symmetrical three-phase AC voltage and current at the three load ends (U / V / W ends in the figure).

[0037] like Figure 1 As shown, the power supply terminal VCC of the driver chip U2 is used for power + access, and the power supply terminal of the main control chip U1 is connected to the power output terminal of the driver chip U2; the driver chip U2 converts the connected power + into the working voltage of the main control chip U1 and connects it to the power supply terminal of the main control chip U1.

[0038] The driving chip in the driving circuit configured in this article is an N+P type driving control IC chip.

[0039] Please refer to Figure 1 The driving circuit also includes capacitors C1, C2 and C3. Capacitor C1 keeps the 5V voltage output by the driving chip U2 stable. Capacitors C2 and C3 are filter capacitors to filter out voltage spikes.

[0040] In the circuit of this article, capacitors C1, C2, C3, C5, C6, C8, C9, C11, and C12 can all be ceramic capacitors, or C1, C3, C5, C6, C8, and C9 can be ceramic capacitors and C2, C11, and C12 can be electrolytic capacitors.

[0041] This inverter circuit uses a bipolar three-phase bridge combining NMOS and PMOS to work complementary to each other, effectively and naturally neutralize the midpoint voltage offset, improve the midpoint voltage floating problem, and improve the stability and efficiency of the circuit.

[0042] The present disclosure has been described using the aforementioned embodiments. However, the aforementioned embodiments are merely exemplary embodiments of the present disclosure. It should be noted that the disclosed embodiments do not limit the scope of the present disclosure. On the contrary, modifications and alterations made without departing from the spirit and scope of the present disclosure are within the scope of patent protection of the present disclosure.

Claims

1. A midpoint-stable bipolar three-phase inverter circuit, characterized in that: The circuit is configured to include a PMOS transistor Q1 and an NMOS transistor Q2. The G pole of the PMOS transistor Q1 is used for bias signal access, the S pole serves as a power supply terminal for power + access, and the D pole is connected to the D pole of the NMOS transistor Q2 and serves as the output terminal of the inverter circuit for load access; the G pole of the NMOS transistor Q2 is used for bias signal access, and the S pole serves as a power supply terminal for power - access.

2. The midpoint-stabilized bipolar three-phase inverter circuit according to claim 1, characterized in that: The circuit is also configured to include a switch resistance selection circuit.

3. The midpoint-stabilized bipolar three-phase inverter circuit according to claim 2, characterized in that: The switch resistor selection circuit includes a diode D2, a diode D1, a resistor R1, a resistor R2, a resistor R3, and a resistor R4. The cathode of the diode D2 is connected to the G terminal of the PMOS transistor Q1, and the anode is connected to one end of the resistor R1. The other end of the resistor R1 is used for bias signal access. The anode of the diode D1 is connected to the G terminal of the NMOS transistor Q2 via the resistor R4, and the cathode is used for bias signal access. One end of the resistor R2 is connected to the G terminal of the PMOS transistor Q1, and the other end is connected to the end of the resistor R1 for bias signal access. One end of the resistor R3 is connected to the G terminal of the NMOS transistor Q2, and the other end is connected to the cathode of the diode D1.

4. The midpoint-stabilized bipolar three-phase inverter circuit according to claim 1, characterized in that: The circuit is further configured to include capacitors C5 and C6 for delaying gate voltage changes. The capacitor C5 is connected in series between the S pole and the G pole of the PMOS transistor Q1, and the capacitor C6 is connected in series between the S pole and the G pole of the NMOS transistor Q2.

5. The midpoint-stabilized bipolar three-phase inverter circuit according to any one of claims 1 to 4, characterized in that: The circuit is further configured to include a resistor R5 and a resistor R6 for limiting transient current. The resistor R5 is connected in series between the S pole and the G pole of the PMOS transistor Q1, and the resistor R6 is connected in series between the S pole and the G pole of the NMOS transistor Q2.

6. The midpoint-stabilized bipolar three-phase inverter circuit according to claim 1, characterized in that: The circuit is also configured to include a low-pass filter for smoothing the output voltage.

7. The midpoint-stabilized bipolar three-phase inverter circuit according to claim 1, characterized in that: The circuit is further configured to include a capacitor C11 and a capacitor C12 located between the S-pole of the PMOS transistor Q1 and the S-pole of the NMOS transistor Q2.

8. A driving circuit for driving the midpoint-stabilized bipolar three-phase inverter circuit according to any one of claims 1 to 7, characterized in that: The driving circuit is configured to include a main control chip U1 for generating a PWM signal and a driving chip U2 for amplifying the output of the main control chip U1; the output of the driving chip U2 is a bias signal.

9. The driving circuit according to claim 8, wherein: The power supply terminal of the driver chip U2 is used for power supply + access, and the power supply terminal of the main control chip U1 is connected to the power output terminal of the driver chip U2; the driver chip U2 converts the connected power supply + into the working voltage of the main control chip U1 and connects it to the power supply terminal of the main control chip U1.

10. The driving circuit according to claim 9, wherein: The circuit is further configured to include a filter capacitor for filtering out voltage spikes in the power supply + connected to the power supply terminal of the driver chip U2.

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