Chip packaging structure and electronic equipment
By using resistive connectors to interconnect between substrates, the problems of large space occupied by traditional hot ball connections and complex ball planting processes are solved, and high-density interconnection and low-cost manufacturing of chip packaging structures are realized.
Patent Information
- Application Number
- CN202422640692.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-10-30
AI Technical Summary
In traditional chip stacking packaging technology, the solder ball interconnect takes up a large space, the ball planting process is complex and the cost is high, making it difficult to miniaturize the device.
Resistor connectors are used to interconnect between substrates, replacing the traditional hot ball connection, and the resistor connector does not occupy too much space in the horizontal direction, realizes electrical interconnection and simplifies the ball planting process.
This increases the interconnect density of chip stacked packages, reduces process complexity and cost, and promotes the miniaturization and lightweight design of chip packages.
Smart Images
Figure CN223296815U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, and more specifically, to a chip packaging structure and electronic equipment. Background Art
[0002] Traditional chip-on-chip packaging technology typically uses solder balls to interconnect upper and lower components, making stacked packaging difficult to implement. Taller devices require larger solder balls. Larger solder balls, however, have a larger horizontal diameter, occupying more horizontal space and hindering device miniaturization.
[0003] At the same time, the traditional chip stacking packaging technology uses solder balls, which adds a ball planting process, which is complex, difficult and costly. Utility Model Content
[0004] One purpose of the present invention is to provide a new technical solution for chip packaging structure and electronic equipment, which can at least solve the problems of the existing technology using solder ball interconnection, which occupies a large space and has a complex ball planting process, high difficulty and cost.
[0005] In a first aspect of the present invention, a chip packaging structure is provided, comprising: a first substrate; a second substrate, the second substrate being spaced apart and arranged in parallel with the first substrate; a resistor connector, the resistor connector being arranged on the first substrate and extending toward the second substrate so that the first substrate and the second substrate are electrically interconnected.
[0006] Optionally, two ends of the resistance connecting member are adhesively connected to the first substrate and the second substrate respectively.
[0007] Optionally, there are multiple resistor connectors, and the multiple resistor connectors are distributed in a ring shape on the first substrate.
[0008] Optionally, the resistance connecting member includes:
[0009] Resistor;
[0010] Two electrical connecting pieces are respectively arranged at two opposite ends of the resistor.
[0011] Optionally, the resistor element is a columnar resistor.
[0012] Optionally, the orthographic projection area of the electrical connecting piece on the resistor is not less than the cross-sectional area of the resistor.
[0013] Optionally, the first substrate and the second substrate are circuit boards respectively.
[0014] Optionally, a first chip is provided on the first substrate, and a second chip is provided on the second substrate.
[0015] Optionally, the chip packaging structure further includes: a packaging component, wherein the packaging component is provided between the first substrate and the second substrate to encapsulate the first substrate and the second substrate.
[0016] A second aspect of the present invention provides an electronic device, comprising the chip packaging structure described in the above embodiment.
[0017] The chip packaging structure of this invention uses a resistive connector as a transmission medium between the first and second substrates to interconnect the first and second substrates. Compared to conventional solder balls, the resistive connector does not occupy excessive horizontal space, which helps increase the interconnect density of the chip stack package while also simplifying the ball placement process and reducing costs.
[0018] Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
[0020] Figure 1 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present utility model;
[0021] Figure 2 It is a process flow chart of the chip packaging structure according to an embodiment of the present utility model.
[0022] Reference numerals:
[0023] Chip packaging structure 100;
[0024] a first substrate 10;
[0025] a second substrate 20;
[0026] Resistor connecting member 30; resistor 31; electrical connecting piece 32;
[0027] First chip 41; second chip 42;
[0028] Package 50. DETAILED DESCRIPTION
[0029] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention.
[0030] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present invention, its application, or uses.
[0031] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.
[0032] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.
[0033] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.
[0034] In the specification and claims of this utility model, references to features using the terms "first" or "second" may explicitly or implicitly include one or more of these features. In the description of this utility model, unless otherwise specified, "plurality" means two or more. Furthermore, in the specification and claims, "and / or" refers to at least one of the connected items, and the character " / " generally indicates an "or" relationship between the connected items.
[0035] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0036] In the description of this utility model, it should be noted that, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; and internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this utility model based on the specific circumstances.
[0037] The chip packaging structure 100 according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
[0038] like Figure 1 and Figure 2 As shown, the chip packaging structure 100 according to an embodiment of the present invention includes a first substrate 10 , a second substrate 20 and a resistive connection member 30 .
[0039] Specifically, the second substrate 20 is spaced apart and arranged in parallel with the first substrate 10. The resistor connector 30 is provided on the first substrate 10 and extends toward the second substrate 20 to electrically interconnect the first substrate 10 and the second substrate 20.
[0040] In other words, see Figure 1 and Figure 2 The chip package structure 100 according to an embodiment of the present invention is primarily composed of a first substrate 10, a second substrate 20, and a resistive connector 30. The second substrate 20 is spaced apart from the first substrate 10 and arranged parallel to each other. The resistive connector 30 is mounted on the first substrate 10 and extends upward toward the second substrate 20, thereby achieving electrical interconnection between the first and second substrates 10, 20.
[0041] like Figure 1 As shown, the present invention interconnects the first substrate 10 and the second substrate 20 using a resistive connector 30. The height dimension of the resistive connector 30 between the first substrate 10 and the second substrate 20 can meet the needs of devices of different heights. Furthermore, the horizontal dimension of the resistive connector 30 remains unchanged for devices of different heights, which reduces the horizontal space occupied and helps increase the interconnection density of the chip package structure 100. Conventional solder balls have the same diameter in both the vertical and horizontal directions. Therefore, as the device becomes taller, the horizontal diameter of the solder ball also increases, occupying horizontal space and reducing the interconnection density.
[0042] Specifically, traditional POP packaging solutions (Package on Package) typically use solder balls to interconnect upper and lower components, making stacked packaging difficult. Taller devices also require larger solder balls, resulting in larger horizontal diameters. This occupies 100% of the horizontal space within the chip package structure, hindering device miniaturization. In addition to worsening I / O spacing (input / output ports), traditional methods also add a costly ball re-balling process in addition to the SMT (Surface Mount Technology) process.
[0043] Thus, according to the chip package structure 100 of the present invention, a resistive connector 30 is used as a transmission medium between the first substrate 10 and the second substrate 20 to interconnect the first substrate 10 and the second substrate 20. Compared to solder balls in the prior art, the resistive connector 30 does not occupy excessive horizontal space, which helps increase the interconnect density of the chip stack package while also simplifying the ball placement process and reducing costs.
[0044] According to an embodiment of the present invention, two ends of the resistor connector 30 are adhesively connected to the first substrate 10 and the second substrate 20 respectively.
[0045] That is to say, if Figure 1 As shown, the two ends of the resistive connector 30 can be bonded to the first substrate 10 and the second substrate 20 respectively via solder paste. After bonding, they can be further secured by soldering to achieve stable interconnection between the first substrate 10 and the second substrate 20. By using the resistive connector 30 as a transmission medium between the first substrate 10 and the second substrate 20 for interconnection, the first substrate 10 and the second substrate 20 are interconnected. Compared to solder balls in the prior art, the resistive connector 30 does not occupy excessive horizontal space, which helps increase the interconnect density of the chip-on-chip package while saving the ball planting process, simplifying the process and reducing costs.
[0046] According to an embodiment of the present invention, there are multiple resistor connectors 30 , and the multiple resistor connectors 30 are distributed in a ring shape on the first substrate 10 .
[0047] In other words, a plurality of resistive connectors 30 may be provided on the first substrate 10, and the plurality of resistive connectors 30 may be distributed in a ring-like pattern on the first substrate 10. Each resistive connector 30 is bonded to the first substrate 10 and the second substrate 20, respectively, to achieve interconnection between the first substrate 10 and the second substrate 20. Of course, the number and distribution of the resistive connectors 30 can be specifically designed according to actual needs and will not be described in detail in this utility model.
[0048] According to an embodiment of the present invention, the resistance connecting member 30 includes a resistance member 31 and two electrical connection pieces 32. Specifically, the two electrical connection pieces 32 are respectively provided at opposite ends of the resistance member 31.
[0049] That is to say, if Figure 1 and Figure 2 As shown, the resistive connector 30 is primarily composed of a resistor 31 and two electrical connection plates 32. The two electrical connection plates 32 are bonded or soldered to opposite ends of the resistor 31. The resistor 31 is a resistor, and the electrical connection plates 32 can be metal sheets to ensure a current path is formed between the first substrate 10, the resistive connector 30, and the second substrate 20.
[0050] According to one embodiment of the present invention, Figure 1 and Figure 2 As shown, the resistor 31 is a columnar resistor. In other words, the resistor 31 can be configured as a columnar structure, for example, a square or circular column, to ensure that the horizontal dimensions of the resistor 31 are consistent, thereby preventing the horizontal space occupied by the device from increasing due to its height, and increasing the interconnection density within the chip package structure 100.
[0051] According to one embodiment of the present invention, Figure 1 and Figure 2 As shown, the orthographic projection area of the electrical connection piece 32 on the resistor 31 is not less than the cross-sectional area of the resistor 31. In other words, the orthographic projection area of the electrical connection piece 32 on the resistor 31 can be not less than the cross-sectional area of the resistor 31, ensuring that the electrical connection piece 32 can achieve a stable electrical connection with the first substrate 10 and the second substrate 20.
[0052] According to one embodiment of the present invention, the first substrate 10 and the second substrate 20 are circuit boards. In other words, the first substrate 10 and the second substrate 20 can be circuit boards, which can be directly used as the substrates of the chip package structure 100 without the need for an additional substrate. This reduces the overall size and material of the chip package structure 100, facilitating a miniaturized and lightweight design of the chip package structure 100.
[0053] According to an embodiment of the present invention, a first chip 41 is provided on the first substrate 10 , and a second chip 42 is provided on the second substrate 20 .
[0054] That is to say, if Figure 1 and Figure 2 As shown, a first chip 41 may be provided on the first substrate 10, and the first chip 41 may be a logic chip. A second chip 42 may be provided on the second substrate 20, and the second chip 42 may be a memory chip. The types and quantities of the first chip 41 and the second chip 42 may be specifically set according to actual needs. The present invention uses a resistor connector 30 to replace the solder balls in the prior art, which can not only save the ball planting process, but also effectively reduce the horizontal space occupied by the chip packaging structure 100, increase the interconnection density within the first substrate 10 and the second substrate 20, and the user can set more chips or other components on the first substrate 10 or the second substrate 20 to achieve more functions.
[0055] According to an embodiment of the present invention, the chip packaging structure 100 further includes: a packaging component 50 , which is disposed between the first substrate 10 and the second substrate 20 to encapsulate the first substrate 10 and the second substrate 20 .
[0056] In other words, if Figure 1 and Figure 2 As shown, the chip packaging structure 100 further includes: a packaging component 50 . The packaging component 50 can be disposed between the first substrate 10 and the second substrate 20 . The packaging component 50 can be made of conventional device packaging materials to achieve overall packaging of the chip packaging structure 100 .
[0057] In the manufacturing process of the chip packaging structure 100 of the present invention, as Figure 2 As shown, first, the resistive connector 30 and the first chip 41 can be mounted on the first substrate 10. Then, the second chip 42 can be mounted on the second substrate 20. After completion, the second substrate 20 is assembled and mounted together with the first substrate 10, ensuring that the two ends of the resistive connector 30 are electrically connected to the first substrate 10 and the second substrate 20 respectively. Finally, the chip is encapsulated with a packaging material. The manufacturing process of the chip packaging structure 100 of the present invention eliminates the solder ball implantation process, resulting in a simpler process and lower costs.
[0058] In summary, the chip package structure 100 according to the present invention utilizes a resistive connector 30 as a transmission medium between the first substrate 10 and the second substrate 20 for interconnection. Compared to conventional solder balls, the resistive connector 30 does not occupy excessive horizontal space, thus increasing the interconnect density of the stacked chip package and facilitating miniaturization and lightweight design. It also reduces the need for bumping, resulting in a simpler and more cost-effective process.
[0059] Of course, for those skilled in the art, other structures and working principles of the chip packaging structure 100 are understandable and achievable, and will not be described in detail in the present invention.
[0060] According to a second aspect of the present invention, an electronic device is provided, comprising the chip packaging structure 100 of the above-described embodiment. Since the chip packaging structure 100 of the embodiment of the present invention has the above-described technical effects, the electronic device of the embodiment of the present invention should also have corresponding technical effects. Specifically, the electronic device of the present invention employing the chip packaging structure 100 of the above-described embodiment is advantageous in increasing the interconnect density of the chip stack package, facilitating miniaturization and lightweight design, while also saving on the ball implantation process, resulting in a simple process and low cost.
[0061] Of course, for those skilled in the art, other structures and working principles of the electronic device are understandable and achievable, and will not be described in detail in this utility model.
[0062] Although some specific embodiments of the present invention have been described in detail through examples, those skilled in the art will appreciate that the above examples are for illustration only and are not intended to limit the scope of the present invention. Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.
Claims
1. A chip packaging structure (100), characterized in that: include: a first substrate (10); a second substrate (20), the second substrate (20) being spaced apart and arranged in parallel with the first substrate (10); A resistance connecting member (30) is provided on the first substrate (10), and the resistance connecting member (30) extends toward the second substrate (20) so that the first substrate (10) and the second substrate (20) are electrically interconnected.
2. The chip packaging structure (100) according to claim 1, characterized in that: Two ends of the resistance connecting member (30) are respectively bonded and connected to the first substrate (10) and the second substrate (20).
3. The chip packaging structure (100) according to claim 1, characterized in that: There are a plurality of the resistance connecting members (30), and the plurality of the resistance connecting members (30) are distributed in a ring shape on the first substrate (10).
4. The chip packaging structure (100) according to claim 1, characterized in that: The resistor connecting member (30) comprises: Resistor (31); Two electrical connection pieces (32), the two electrical connection pieces (32) are respectively arranged at opposite ends of the resistor (31).
5. The chip packaging structure (100) according to claim 4, characterized in that: The resistor (31) is a columnar resistor.
6. The chip packaging structure (100) according to claim 4, characterized in that: The orthographic projection area of the electrical connecting piece (32) on the resistor (31) is not less than the cross-sectional area of the resistor (31).
7. The chip packaging structure (100) according to claim 1, characterized in that: The first substrate (10) and the second substrate (20) are respectively circuit boards.
8. The chip packaging structure (100) according to claim 1, characterized in that: A first chip (41) is provided on the first substrate (10), and a second chip (42) is provided on the second substrate (20).
9. The chip packaging structure (100) according to claim 1, characterized in that: Also includes: A packaging component (50) is provided between the first substrate (10) and the second substrate (20) to package the first substrate (10) and the second substrate (20).
10. An electronic device, characterized in that: A chip packaging structure (100) comprising any one of claims 1-9.