Semiconductor structure

Abstract

A semiconductor structure includes: a substrate; the collector layer is positioned on the substrate; a base layer on the collector layer; the emitting electrode layers and the base electrode contact layers are located on the base electrode layer, the emitting electrode layers extend in the first direction and are arranged in parallel in the second direction, the first direction is perpendicular to the second direction, and the base electrode contact layers are located between the adjacent emitting electrode layers. Each base contact layer comprises a leading-out region and a main body region which are adjacent to each other, in the second direction, the leading-out region has a first size, the main body region has a second size, and the first size is larger than the second size; and the base conducting layer is electrically connected with the leading-out region, so that the stray capacitance (junction capacitance) CBC between the base layer and the collector layer is reduced, and the cut-off frequency and the radio frequency gain of the device are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor structure. Background Art

[0002] A heterojunction bipolar transistor (HBT) is a type of bipolar transistor in which the emitter and substrate layers are constructed from different semiconductor materials to form a heterojunction. Compared to conventional bipolar transistors, HBTs exhibit superior high-frequency signal characteristics and substrate emission efficiency. They can operate at signals up to hundreds of GHz and are widely used in modern high-speed circuits, radio frequency systems, and mobile phones.

[0003] Due to limitations such as process uniformity, the size of a single heterojunction bipolar transistor is relatively small, making it impossible for a single device to meet the needs of high-power products. Therefore, several heterojunction bipolar transistors need to be connected in parallel to provide high power. However, the parasitic capacitance of high-power devices has become a difficult problem in product design.

[0004] Therefore, the existing heterojunction bipolar transistor structure needs to be further improved. Utility Model Content

[0005] The technical problem solved by the utility model is to provide a semiconductor structure to improve the performance of the semiconductor structure.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a collector layer located on the substrate; a base layer located on the collector layer; a plurality of emitter layers and a plurality of base contact layers located on the base layer, the plurality of emitter layers extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction being perpendicular to each other, each of the base contact layers being located between adjacent emitter layers, each of the base contact layers including adjacent lead-out regions and main body regions, along the second direction, the lead-out regions having a first size, the main body regions having a second size, the first size being larger than the second size; a base conductive layer, the base conductive layer being electrically connected to the lead-out regions.

[0007] Optionally, the main body region is located on both sides of the lead-out region in the first direction.

[0008] Optionally, it further includes: an emitter contact layer located on each of the emitter layers, wherein the emitter contact layer covers part or all of the surface of the emitter layer.

[0009] Optionally, the collector layer includes a first collector portion and a second collector portion located on a portion of the first collector portion; the semiconductor structure further includes: a collector contact layer located on the first collector portion.

[0010] Optionally, it also includes: a passivation layer located on the collector layer, the base layer, several of the emitter layers, and several of the base contact layers, the passivation layer having a first opening, the first opening exposing the lead-out area, the base conductive layer being located in the first opening and extending to a portion of the surface of the passivation layer.

[0011] Optionally, the emitter layer has a sidewall adjacent to the base contact layer, the sidewall includes a first sub-sidewall adjacent to the lead-out region, and a second sub-sidewall adjacent to the main region, and the first sub-sidewall is recessed relative to the second sub-sidewall.

[0012] Optionally, the lead-out region is located in the middle of the base contact layer.

[0013] Optionally, the ratio of the first size to the second size is in the range of 3:2.

[0014] Optionally, the first size ranges from 1 μm to 1.4 μm.

[0015] Optionally, the projection shape of the lead-out area on the surface of the substrate includes a circle, a polygon or an ellipse.

[0016] Compared with the prior art, the technical solution of the embodiment of the utility model has the following beneficial effects:

[0017] In the semiconductor structure provided by the technical solution of the present utility model, each base contact layer is located between adjacent emitter layers, and each base contact layer includes an adjacent lead-out region and a main body region. Along the second direction, the lead-out region has a first size, and the main body region has a second size, the first size is larger than the second size, and the lead-out region is used to lead out the current of the base layer. The lead-out region is located between adjacent emitter layers and occupies a smaller base layer area, which is beneficial to increasing the proportion of the emitter layer occupied by the surface area of ​​the base layer. Therefore, under the requirement of a fixed emitter layer area, the contact area between the collector layer and the base layer is reduced, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the base layer and the collector layer. BC , which is beneficial to improving the cutoff frequency and RF gain of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figures 1 to 3 It is a schematic diagram of the structure of a heterojunction bipolar transistor;

[0019] Figures 4 to 8It is a structural schematic diagram of a semiconductor structure in one embodiment of the present utility model. DETAILED DESCRIPTION

[0020] It should be noted that the terms “surface” and “on” in the present invention are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0021] As described in the background art, the existing heterojunction bipolar transistor structure needs to be further improved. Now, a heterojunction bipolar transistor structure is described in conjunction with the following.

[0022] Figures 1 to 3 It is a structural diagram of a heterojunction bipolar transistor.

[0023] Please refer to Figures 1 to 3 , Figure 1 for Figure 2 and Figure 3 The schematic diagram of the top view of the passivation layer is omitted. Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the DD1 direction, Figure 3 for Figure 1 The cross-sectional structural diagram along the EE1 direction in the figure, the heterojunction bipolar transistor device includes: a substrate 100; a first collector portion 101 located on the substrate 100, an isolation layer 102 and a prism structure located on the first collector portion 101, the prism structure including a second collector portion 103 and a base layer 104 located on the second collector portion 103, the collector layer including the first collector portion 101 and the second collector portion 103, the isolation layer 102 is located on the side wall of the first collector portion 101 and surrounds the first collector portion 101; a plurality of emitter layers 105 and a base contact layer located on the base layer 104, the plurality of emitter layers 105 are parallel to the first direction X and arranged along the second direction Y, the first The direction X is perpendicular to the second direction Y. The base contact layer includes a base bus 106 parallel to the second direction Y and a plurality of base portions 107 parallel to the first direction X. Each base portion 107 is located between adjacent emitter layers 105 and is electrically connected to the base bus 106. An emitter contact layer 108 is located on each emitter layer 105. A passivation layer 109 is located on the surface of the emitter layer 105, the emitter contact layer 108, and the base layer 104. The passivation layer 109 has an opening (not shown in the figure) therein. The opening exposes a portion of the surface of the base layer 104. The base contact layer is also located in the opening. A collector contact layer 110 is located on the first collector portion 101.

[0024] In the heterojunction bipolar transistor device, there is a parasitic capacitance (ie, junction capacitance) C at the contact surface (ie, PN interface) between the collector layer and the base layer 104.BC The base contact layer is electrically connected to the first layer of metal interconnection (M1) formed subsequently via the base bus 106. The base bus 106 occupies a larger area of ​​the base layer 104, making the emitter layer 105 occupy a smaller area of ​​the base layer 104. Since the area of ​​the emitter layer 105 determines the output power of the device, under the requirement of a fixed emitter layer 105 area, the arrangement of the base bus 106 makes the contact surface between the collector layer and the base layer 104 larger, resulting in a parasitic capacitance C BC Large, affecting the device's RF gain and cutoff frequency.

[0025] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure in which each base contact layer is located between adjacent emitter layers, each base contact layer includes an adjacent lead-out region and a main body region, along the second direction, the lead-out region has a first size, the main body region has a second size, the first size is larger than the second size, the lead-out region is used to lead out the current of the base layer, the lead-out region is located between adjacent emitter layers, and occupies a smaller base layer area, which is beneficial to increasing the proportion of the area occupied by the emitter layer on the surface of the base layer. Therefore, under the requirement of a fixed emitter layer area, the contact area between the collector layer and the base layer is reduced, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the base layer and the collector layer. BC , which is beneficial to improving the cutoff frequency and RF gain of the device.

[0026] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figures 4 to 8 It is a structural schematic diagram of a semiconductor structure in one embodiment of the present utility model.

[0028] Please refer to Figures 4 to 8 , Figure 4 The schematic diagram of the top view of the structure omits the passivation layer and the base conductive layer. Figure 5 The top view of the structure of the passivation layer is omitted. Figure 6 for Figure 5 Schematic diagram of the cross-sectional structure along the AA1 direction, Figure 7 for Figure 5 Schematic diagram of the cross-sectional structure along the BB1 ​​direction, Figure 8 for Figure 5: A schematic cross-sectional structure diagram along the CC1 direction in FIG, wherein the semiconductor structure includes: a substrate 200; a collector layer 201 located on the substrate 200; a base layer 202 located on the collector layer 201; a plurality of emitter layers 203 and a plurality of base contact layers 204 located on the base layer 202, wherein the plurality of emitter layers 203 extend along a first direction X and are arranged in parallel along a second direction Y, wherein the first direction X and the second direction Y are perpendicular to each other, wherein each base contact layer 204 is located between adjacent emitter layers 203, and each base contact layer 204 includes adjacent lead-out regions 204a and body regions 204b, wherein along the second direction Y, the lead-out regions 204a have a first size d1, and the body regions 204b have a second size d2, wherein the first size d1 is greater than the second size d2; and a base conductive layer 205, wherein the base conductive layer 205 is electrically connected to the lead-out regions 204a.

[0029] Here, each base contact layer 204 is located between adjacent emitter layers 203, and each base contact layer 204 includes adjacent lead-out regions 204a and main regions 204b. The lead-out regions 204a are used to lead out the current of the base layer 202. The lead-out regions 204a are located between adjacent emitter layers 203 and occupy a smaller area of ​​the base layer 202, which is beneficial to increasing the proportion of the area occupied by the emitter layer 203 on the surface of the base layer 202. Thus, under the requirement of a fixed emitter layer 203 area, the contact area between the collector layer 201 and the base layer 202 is reduced, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the base layer 202 and the collector layer 201. BC , which is beneficial to improving the cutoff frequency and RF gain of the device.

[0030] It should be noted that according to the known relationship Ft=Gm / [2*π*(C BE +C BC )], where Ft is the cutoff frequency, Gm is the transconductance coefficient, C BE is the parasitic capacitance between the base layer and the emitter layer, C BC is the parasitic capacitance between the base layer and the collector layer. It can be seen that reducing the parasitic capacitance C BC , which is beneficial to improving the cutoff frequency Ft of the device.

[0031] In this embodiment, the main body region 204 b is located on both sides of the lead-out region 204 a in the first direction X.

[0032] Specifically, the lead-out region 204a is located in the middle of the base contact layer 204. Locating the lead-out region 204a in the middle of the base contact layer 204 is beneficial to improving the uniformity of current extraction from the base layer 202.

[0033] In other embodiments, the lead-out region may not be disposed in the middle of the base contact layer.

[0034] In this embodiment, the ratio of the first size d1 to the second size d2 is 3:2.

[0035] Here, the purpose of selecting the ratio range of the first size d1 to the second size d2 is to make the lead-out region 204a electrically connected to the base conductive layer 205, that is, to play the role of current extraction, while not occupying too much area of ​​the base layer 202, which is conducive to reducing the contact area between the collector layer 201 and the base layer 202, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC , which is beneficial to improving the cutoff frequency and RF gain of the device.

[0036] In this embodiment, the first dimension d1 ranges from 1 μm to 1.4 μm.

[0037] In this embodiment, the collector layer 201 includes a first collector portion 201 a and a second collector portion 201 b located on a portion of the first collector portion 201 a .

[0038] The base contact layer 204 includes a multi-layer metal structure, which includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate 200 .

[0039] In this embodiment, the material of the first metal layer includes platinum; the material of the second metal layer includes titanium; the material of the third metal layer includes platinum; and the material of the fourth metal layer includes copper or gold.

[0040] In this embodiment, the semiconductor structure further includes an emitter contact layer 206 located on each of the emitter layers 203 .

[0041] The emitter contact layer 206 includes a stack of multiple metal layers, and the materials of two adjacent metal layers are different from each other; the material of the metal layer includes titanium or platinum.

[0042] In this embodiment, the emitter contact layer 206 includes a stack of a titanium metal layer, a platinum metal layer, a titanium metal layer, a platinum metal layer, and a titanium metal layer.

[0043] In this embodiment, the emitter contact layer 206 covers a portion of the surface of the emitter layer 203. In another embodiment, the emitter contact layer covers the entire surface of the emitter layer.

[0044] In this embodiment, the semiconductor structure further includes: a collector contact layer 207 located on the first collector portion 201 a .

[0045] In this embodiment, the material of the collector contact layer 207 includes metal, and the metal includes one or more of gold germanium, nickel, and gold.

[0046] Specifically, the collector contact layer 207 is parallel to the first direction X, and is located on both sides of the second collector portion 201 b in the second direction Y.

[0047] In this embodiment, the semiconductor structure further includes an isolation layer 208 located on the substrate 200 . The isolation layer 208 is located on a sidewall of the first collector portion 201 a and surrounds the first collector portion 201 a .

[0048] In this embodiment, the semiconductor structure also includes: a passivation layer 209 located on the collector layer 201, the base layer 202, several of the emitter layers 203, and several of the base contact layers 204, the passivation layer 209 having a first opening (not shown in the figure), the first opening exposing the lead-out area 204a, the base conductive layer 205 is located in the first opening and extends to a portion of the surface of the passivation layer 209.

[0049] The passivation layer 209 also has a second opening (not shown in the figure) and a third opening (not shown in the figure), the second opening exposes the emitter contact layer 206, and the third opening exposes the collector contact layer 207. The second opening has an emitter conductive layer (not shown in the figure), and the third opening has a collector conductive layer (not shown in the figure).

[0050] The material of the passivation layer 209 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the passivation layer 209 is silicon nitride.

[0051] In this embodiment, the sidewalls of the lead-out region 204a protrude symmetrically relative to the sidewalls of the main region 204b toward both sides in the second direction Y. In other embodiments, this limitation may not apply.

[0052] In this embodiment, the emitter layer 203 has a side wall 2031 adjacent to the base contact layer 204, and the side wall 2031 includes a first sub-side wall 2031a adjacent to the lead-out area 204a, and a second sub-side wall 2031b adjacent to the main area 204b, and the first sub-side wall 2031a is recessed relative to the second sub-side wall 2031b.

[0053] Specifically, the concave shape of the sidewall 2031 a adjacent to the lead-out area 204 a corresponds to the shape of the lead-out area 204 a.

[0054] The projection shape of the lead-out region 204a on the surface of the substrate 200 includes a circle, a polygon or an ellipse.

[0055] In this embodiment, the projection of the lead-out region 204a on the surface of the substrate 200 is circular, and the concave shape of the sidewall 2031a is arc-shaped.

[0056] In another embodiment, the projection shape of the lead-out region on the substrate surface may also be a polygon (such as a rectangle) or an ellipse, etc. That is, any shape that facilitates electrical connection with the base conductive layer may be selected.

[0057] Although the present invention is disclosed as above, it is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a collector layer located on the substrate; a base layer located on the collector layer; a plurality of emitter layers and a plurality of base contact layers located on the base layer, the plurality of emitter layers extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction being perpendicular to each other, each base contact layer being located between adjacent emitter layers, each base contact layer including adjacent lead-out regions and body regions, along the second direction, the lead-out regions having a first size, the body regions having a second size, the first size being larger than the second size; A base conductive layer is electrically connected to the lead-out region.

2. The semiconductor structure according to claim 1, wherein The main body region is located on both sides of the lead-out region in the first direction.

3. The semiconductor structure according to claim 1, wherein: Also includes: An emitter contact layer is located on each of the emitter layers, and the emitter contact layer covers part or all of the surface of the emitter layer.

4. The semiconductor structure according to claim 3, wherein: The collector layer includes a first collector portion and a second collector portion located on a portion of the first collector portion; the semiconductor structure further includes a collector contact layer located on the first collector portion.

5. The semiconductor structure according to claim 1, wherein Also includes: A passivation layer is located on the collector layer, the base layer, several emitter layers, and several base contact layers, wherein the passivation layer has a first opening, the first opening exposes the lead-out area, and the base conductive layer is located in the first opening and extends to a portion of the passivation layer surface.

6. The semiconductor structure according to claim 1, wherein The emitter layer has a sidewall adjacent to the base contact layer, the sidewall includes a first sub-sidewall adjacent to the lead-out region and a second sub-sidewall adjacent to the body region, and the first sub-sidewall is recessed relative to the second sub-sidewall.

7. The semiconductor structure according to claim 1, wherein: The lead-out region is located in the middle of the base contact layer.

8. The semiconductor structure according to claim 1, wherein: The ratio of the first size to the second size is in the range of 3:

2.

9. The semiconductor structure according to claim 1, wherein: The first size ranges from 1 μm to 1.4 μm.

10. The semiconductor structure according to claim 1, wherein: The projection shape of the lead-out area on the surface of the substrate includes a circle, a polygon or an ellipse.

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