SOC restart power-on control device, chip and equipment
By using multiple power supply units controlled by the controller to supply power to the SOC's clock domain, security domain, and application domain during the SOC restart and power-on process, the power-on failure problem caused by leakage of peripheral devices is solved, and the stable restart and functional safety of the SOC are achieved.
Patent Information
- Application Number
- CN202422465813.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2034-10-11
AI Technical Summary
During the restart and power-on process of the existing X9 platform SOC, power-on failure occurs due to leakage of peripheral devices. There is a lack of effective monitoring mechanism and it cannot meet functional safety requirements.
The first power supply unit, second power supply unit and third power supply unit controlled by the controller respectively power the clock domain, security domain and application domain of the SOC. After the clock domain is powered on, the SOC executes the self-start program and then controls the operation of the second and third power supply units to ensure the power-on of the security domain and application domain and avoid the impact of leakage of peripheral devices.
It effectively avoids the impact of leakage of peripheral devices on the SOC restart operation, ensures the stability and reliability of the SOC during the power-on process, and meets functional safety requirements.
Smart Images
Figure CN223308616U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of electronic chip circuits, and more specifically, to a SOC restart power-on control device, chip and equipment. Background Art
[0002] SemiDrive's X9 platform is a series of automotive-grade chips designed specifically for next-generation automotive cockpits. These chips integrate high-performance CPUs, GPUs, AI accelerators, and video processors to meet the powerful computing and communication capabilities required for automotive cockpit applications.
[0003] In the existing X9 platform, before the internal security and application domains of the system-on-chip (SOC) are fully powered up, leakage current from peripheral devices may enter the SOC, causing the SOC to power up and potentially causing a restart failure. Currently, the X9 platform lacks a monitoring mechanism for SOC restarts, which cannot be met in systems with functional safety requirements. Utility Model Content
[0004] The utility model provides an SOC restart power-on control device to overcome the defect in the prior art that power-on failure is easily caused by leakage of peripheral devices when the SOC is restarted and powered on.
[0005] In order to solve the above technical problems, the technical solutions of the present utility model are as follows:
[0006] A SOC restart power-on control device includes a controller, a first power supply unit connected to a SOC clock domain power supply terminal, a second power supply unit connected to a SOC security domain power supply terminal, and a third power supply unit electrically connected to a SOC application domain power supply terminal;
[0007] The first output terminal of the controller is connected to the control terminal of the first power supply unit, and is used to control the operation of the first power supply unit;
[0008] The second output terminal of the controller is connected to the first input terminal of the SOC for outputting a clock domain power-on PGOOD signal; the SOC performs self-startup after receiving the clock domain power-on PGOOD signal;
[0009] The first output terminal of the SOC is connected to the control terminals of the second power supply unit and the third power supply unit, and is used to control the operation of the second power supply unit and the third power supply unit.
[0010] In the present technical solution, the clock domain, security domain and application domain of the SOC are powered by the first power supply unit, the second power supply unit and the third power supply unit respectively. During use, the power supply of the clock domain is controlled by the controller, and the controller outputs an enable signal to the first power supply unit to control the operation of the first power supply unit and complete the power-on of the clock domain. When the clock domain is powered on, the controller outputs a clock domain power-on PGOOD signal to the SOC to indicate that the working status of the power supply is normal. After receiving the clock domain power-on PGOOD signal, the SOC triggers the internal self-starting program, and when the SOC completes self-starting, the SOC outputs an enable signal to the second power supply unit and the third power supply unit to control the operation of the second power supply unit and the third power supply unit and complete the power-on of the security domain and the application domain, completing the SOC restart power-on control. When the security domain and the application domain are powered on, the SOC communicates with the peripheral devices to prevent the leakage of the peripheral devices from affecting the restart operation of the SOC.
[0011] As a preferred solution, the device also includes a power supply, the output end of which is electrically connected to the power supply ends of the first power supply unit, the second power supply unit and the third power supply unit respectively; and the control end of the power supply is connected to the third output end of the controller.
[0012] As a preferred solution, the first power supply unit, the second power supply unit and the third power supply unit include DC-DC converters.
[0013] As a preferred solution, the device also includes a logic judgment module, and the output ends of the second power supply unit and the third power supply unit are connected to the input end of the logic judgment module; the output end of the logic judgment module is connected to the second input end of the SOC, for outputting a self-starting power supply success signal to the SOC.
[0014] As a preferred solution, the logic judgment module includes an AND gate circuit.
[0015] As a preferred embodiment, the AND gate circuit includes a first diode, a second diode and a resistor; the cathode of the first diode is electrically connected to the output end of the second power supply unit, and the cathode of the second diode is electrically connected to the output end of the third power supply unit; the anodes of the first diode and the second diode are electrically connected to one end of the resistor.
[0016] As a preferred solution, the second output end of the SOC is connected to the input end of the controller to notify the controller that the SOC self-starts successfully; the fourth output end of the controller is connected to the input end of the SOC peripheral device to output an enable signal to the SOC peripheral device.
[0017] Furthermore, the present invention also proposes a SOC chip, which is connected to the SOC restart power-on control device proposed in the present invention.
[0018] As a preferred solution, the SOC chip includes an X9 series chip.
[0019] Furthermore, the present invention also proposes a device, which includes the SOC chip proposed in the present invention.
[0020] Compared with the prior art, the beneficial effects of the technical solution of the utility model are:
[0021] The utility model supplies power to the clock domain, security domain and application domain of the SOC through the first power supply unit, the second power supply unit and the third power supply unit respectively. When the clock domain is powered on, the SOC executes a self-starting program, and then controls the second power supply unit and the third power supply unit to work, and powers on the security domain and the application domain; when the security domain and the application domain are powered on, the SOC communicates with peripheral devices to prevent leakage of peripheral devices from affecting the restart operation of the SOC. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 FIG1 is a structural diagram of a SOC restart power-on control device according to an embodiment of the present invention.
[0023] Figure 2 FIG2 is another structural diagram of a SOC restart power-on control device according to an embodiment of the present invention.
[0024] Figure 3 FIG2 is another structural diagram of a SOC restart power-on control device according to an embodiment of the present invention.
[0025] Figure 4 The figure is a circuit diagram of an AND gate circuit according to an embodiment of the present invention.
[0026] Among them, 1-controller, 2-first power supply unit, 3-second power supply unit, 4-third power supply unit, 5-power supply, 6-logic judgment module. DETAILED DESCRIPTION
[0027] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present invention, as detailed in the appended claims.
[0028] The terms used in this utility model are for the purpose of describing specific embodiments only and are not intended to limit the utility model. As used in this utility model and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0029] It should be understood that although the terms first, second, third, etc. may be used in this utility model to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, first information can also be referred to as second information without departing from the scope of this utility model, and similarly, second information can also be referred to as first information. Depending on the context, the word "if" as used herein can be interpreted as "when...", "when...", or "in response to determining."
[0030] The present invention is described in detail below with reference to the accompanying drawings and specific implementation methods.
[0031] Example 1
[0032] This embodiment proposes a SOC restart power-on control device, such as Figure 1 FIG. 1 is a structural diagram of the SOC restart power-on control device of this embodiment.
[0033] The SOC restart power-on control device proposed in this embodiment includes a controller 1, a first power supply unit 2 connected to the SOC clock domain power supply end, a second power supply unit 3 connected to the SOC security domain power supply end, and a third power supply unit 4 electrically connected to the SOC application domain power supply end.
[0034] The first output terminal of the controller 1 is connected to the control terminal of the first power supply unit 2 , and is used to control the operation of the first power supply unit 2 to complete the power-on operation of the SOC clock domain.
[0035] The second output terminal of the controller 1 is connected to the first input terminal of the SOC for outputting a clock domain power-on PGOOD signal; the SOC performs self-startup after receiving the clock domain power-on PGOOD signal.
[0036] The first output end of the SOC is connected to the control end of the second power supply unit 3 and the third power supply unit 4, and is used to control the operation of the second power supply unit 3 and the third power supply unit 4 to complete the power-on operation of the SOC security domain and application domain.
[0037] In this embodiment, the clock domain, security domain and application domain of the SOC are powered by the first power supply unit 2, the second power supply unit 3 and the third power supply unit 4 respectively. When the clock domain is powered on, the SOC executes a self-starting program, and then controls the second power supply unit 3 and the third power supply unit 4 to work and power on the security domain and the application domain; when the security domain and the application domain are powered on, the SOC communicates with peripheral devices to avoid leakage of peripheral devices affecting the restart operation of the SOC.
[0038] During the specific implementation process, the power supply of the clock domain is controlled by controller 1, which outputs an enable signal to first power supply unit 2, controlling the operation of first power supply unit 2 and completing the power-up of the clock domain. After the clock domain power-up is completed, controller 1 outputs a clock domain power-up PGOOD signal to the SOC to indicate that the power supply is operating normally. After receiving the clock domain power-up PGOOD signal, the SOC triggers the internal self-start program. After the SOC completes the self-start, the SOC outputs an enable signal to second power supply unit 3 and third power supply unit 4, controlling the operation of second power supply unit 3 and third power supply unit 4 and completing the power-up of the security domain and application domain, completing the SOC restart power-up control.
[0039] It should be noted that the default state of the PGOOD signal pin in the SOC is low, indicating that the SOC cannot perform self-start. When the controller 1 outputs the clock domain power-on PGOOD signal to the SOC, the clock domain power-on PGOOD signal is high. The SOC receives the signal and triggers its internal self-start program to complete the restart.
[0040] Exemplarily, the controller 1 includes a microcontroller unit (MCU).
[0041] Example 2
[0042] This embodiment makes improvements based on the SOC restart power-on control device proposed in embodiment 1, such as Figure 2 FIG. 1 is a structural diagram of the SOC restart power-on control device of this embodiment.
[0043] The SOC restart power-on control device proposed in this embodiment includes a controller 1, a first power supply unit 2 connected to the SOC clock domain power supply end, a second power supply unit 3 connected to the SOC security domain power supply end, and a third power supply unit 4 electrically connected to the SOC application domain power supply end.
[0044] The first output terminal of the controller 1 is connected to the control terminal of the first power supply unit 2 , and is used to control the operation of the first power supply unit 2 to complete the power-on operation of the SOC clock domain.
[0045] The second output terminal of the controller 1 is connected to the first input terminal of the SOC for outputting a clock domain power-on PGOOD signal; the SOC performs self-startup after receiving the clock domain power-on PGOOD signal.
[0046] The first output end of the SOC is connected to the control end of the second power supply unit 3 and the third power supply unit 4, and is used to control the operation of the second power supply unit 3 and the third power supply unit 4 to complete the power-on operation of the SOC security domain and application domain.
[0047] Furthermore, in an optional embodiment, the device also includes a power supply 5, the output end of the power supply 5 is electrically connected to the power supply ends of the first power supply unit 2, the second power supply unit 3 and the third power supply unit 4 respectively; the control end of the power supply 5 is connected to the third output end of the controller 1.
[0048] The power supply 5 added in this embodiment serves as the primary power supply of the device, supplying power to the first power supply unit 2, the second power supply unit 3 and the third power supply unit 4, which are then independently powered by the first power supply unit 2, the second power supply unit 3 and the third power supply unit 4 to power on the SOC clock domain, the security domain and the application domain respectively.
[0049] During the specific implementation process, the controller 1 outputs an enable signal to the power supply 5, and the power supply 5 works and supplies power to the first power supply unit 2, the second power supply unit 3 and the third power supply unit 4 respectively. Then, the controller 1 outputs an enable signal to the first power supply unit 2 to control the first power supply unit 2 to work and complete the clock domain power-on. When the clock domain power-on is completed, the controller 1 outputs a clock domain power-on PGOOD signal to the SOC to indicate that the working status of the power supply is normal. After receiving the clock domain power-on PGOOD signal, the SOC triggers the internal self-starting program, and when the SOC completes the self-starting, the SOC outputs an enable signal to the second power supply unit 3 and the third power supply unit 4 to control the second power supply unit 3 and the third power supply unit 4 to work and complete the power-on of the security domain and the application domain, completing the SOC restart power-on control.
[0050] Furthermore, in an optional embodiment, the first power supply unit 2, the second power supply unit 3 and the third power supply unit 4 include a DC-DC converter for converting the DC power output by the power supply 5 into a DC power supply of different voltages to meet the power-on requirements of the SOC clock domain, security domain and application domain.
[0051] Example 3
[0052] This embodiment makes improvements based on the SOC restart power-on control device proposed in embodiment 1 or 2, such as Figure 3 As shown in FIG, it is the architecture diagram of the SOC restart power-on control device of this embodiment. It should be noted that, Figure 3The omission of the connection representation between the first power supply unit 2, the second power supply unit 3 and the third power supply unit 4 and the SOC clock domain, the security domain and the application domain respectively does not mean that there is no connection relationship.
[0053] The SOC restart power-on control device proposed in this embodiment includes a controller 1, a first power supply unit 2 connected to the SOC clock domain power supply end, a second power supply unit 3 connected to the SOC security domain power supply end, and a third power supply unit 4 electrically connected to the SOC application domain power supply end.
[0054] The first output terminal of the controller 1 is connected to the control terminal of the first power supply unit 2 , and is used to control the operation of the first power supply unit 2 to complete the power-on operation of the SOC clock domain.
[0055] The second output terminal of the controller 1 is connected to the first input terminal of the SOC for outputting a clock domain power-on PGOOD signal; the SOC performs self-startup after receiving the clock domain power-on PGOOD signal.
[0056] The first output end of the SOC is connected to the control end of the second power supply unit 3 and the third power supply unit 4, and is used to control the operation of the second power supply unit 3 and the third power supply unit 4 to complete the power-on operation of the SOC security domain and application domain.
[0057] Furthermore, in an optional embodiment, the device also includes a logic judgment module 6, and the output ends of the second power supply unit 3 and the third power supply unit 4 are connected to the input end of the logic judgment module 6; the output end of the logic judgment module 6 is connected to the second input end of the SOC, for outputting a self-starting power supply success signal to the SOC.
[0058] The logic judgment module 6 added in this embodiment is used to determine whether the SOC security domain and application domain have completed the power-on operation. Specifically, when the logic judgment module 6 simultaneously receives the security domain power-on PGOOD signal and the application domain power-on PGOOD signal output by the second power supply unit 3 and the third power supply unit 4 respectively, the logic judgment module 6 is triggered and outputs a self-start power supply success signal to the SOC to ensure that the security domain and application domain have completed the power-on operation.
[0059] During the specific implementation, controller 1 outputs an enable signal to first power supply unit 2, controlling its operation and completing clock domain power-up. Once clock domain power-up is complete, controller 1 outputs a clock domain power-up PGOOD signal to the SOC, indicating that the power supply is operating normally. Upon receiving the clock domain power-up PGOOD signal, the SOC triggers its internal self-startup routine. After the SOC completes self-startup, it outputs enable signals to second and third power supply units 3 and 4, controlling their operation and executing security and application domain power-up. Once the security and / or application domains have completed power-up, second and third power supply units 3 and 4 output security and / or application domain power-up PGOOD signals to logic judgment module 6. When logic judgment module 6 receives both the security and application domain power-up PGOOD signals, it triggers and outputs a self-startup power-up success signal to the SOC.
[0060] Furthermore, in an optional embodiment, the logic judgment module 6 includes an AND gate circuit.
[0061] Furthermore, in an optional embodiment, the AND gate circuit includes a first diode D1, a second diode D2 and a resistor R; the cathode of the first diode is electrically connected to the output end of the second power supply unit 3, and the cathode of the second diode is electrically connected to the output end of the third power supply unit 4; the anodes of the first diode and the second diode are electrically connected to one end of the resistor.
[0062] For example, Figure 4 FIG. 1 is a circuit diagram of the AND gate circuit of this embodiment.
[0063] Furthermore, in an optional embodiment, the second output terminal of the SOC is connected to the input terminal of the controller 1 for notifying the controller 1 that the SOC self-starts successfully; the fourth output terminal of the controller 1 is connected to the input terminal of the SOC peripheral device for outputting an enable signal to the SOC peripheral device.
[0064] During implementation, when logic module 6 simultaneously receives the security domain power-on PGOOD signal and the application domain power-on PGOOD signal, it triggers and outputs a self-start power supply success signal to the SOC. After receiving the self-start power supply success signal, the SOC outputs the SOC_PWR_OK signal to controller 1, notifying it that the SOC has completed self-start. After receiving the SOC_PWR_OK signal, controller 1 outputs an enable signal to the SOC's peripheral components, causing them to activate and communicate with the SOC, commencing normal operation.
[0065] In this embodiment, the SOC's internal self-startup is not controlled by the controller 1. Therefore, there is a risk that the SOC's peripheral devices may still be powered during the SOC's self-startup. In this case, there is still a risk that the peripheral devices may leak power to the SOC, causing the SOC's self-startup to fail. In this embodiment, a logic judgment module 6 is added to determine the power-on status of the SOC's security domain and application domain, further coordinating with the controller 1's control of the peripheral devices, effectively preventing the peripheral device leakage from affecting the SOC's self-startup operation.
[0066] Example 4
[0067] This embodiment provides a SOC chip, to which the SOC restart and power-on control device provided in any one of Embodiments 1 to 3 is connected.
[0068] Specifically, in the SOC chip of this embodiment, its SOC clock domain power supply end is connected to the first power supply unit 2 , the SOC security domain power supply end is connected to the second power supply unit 3 , and the SOC application domain power supply end is connected to the third power supply unit 4 .
[0069] Furthermore, the first output terminal of the controller 1 is connected to the control terminal of the first power supply unit 2 for controlling the operation of the first power supply unit 2;
[0070] The second output terminal of the controller 1 is connected to the first input terminal of the SOC chip, and is used to output a clock domain power-on PGOOD signal; the SOC chip performs self-startup after receiving the clock domain power-on PGOOD signal;
[0071] The first output terminal of the SOC chip is connected to the control terminals of the second power supply unit 3 and the third power supply unit 4 , and is used to control the operation of the second power supply unit 3 and the third power supply unit 4 .
[0072] During the specific implementation process, the power supply of the clock domain in the SOC chip is controlled by the controller 1, which outputs an enable signal to the first power supply unit 2 to control the operation of the first power supply unit 2 and complete the power-on of the clock domain. After the clock domain is powered on, the controller 1 outputs a clock domain power-on PGOOD signal to the SOC chip to indicate that the working status of the power supply is normal. After receiving the clock domain power-on PGOOD signal, the SOC chip triggers the internal self-starting program. After the SOC chip completes the self-starting, the SOC chip outputs an enable signal to the second power supply unit 3 and the third power supply unit 4 to control the operation of the second power supply unit 3 and the third power supply unit 4 and complete the power-on of the security domain and the application domain, completing the restart power-on control of the SOC chip.
[0073] Furthermore, in an optional embodiment, the SOC chip proposed in this embodiment is the Xinchi X9 series chip.
[0074] Example 5
[0075] This embodiment provides a device, which includes the SOC chip provided in Embodiment 4.
[0076] The same or similar reference numerals correspond to the same or similar components;
[0077] The terms used in the drawings to describe positional relationships are for illustrative purposes only and should not be construed as limiting this patent;
[0078] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. A person skilled in the art will be able to make other variations or modifications based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.
Claims
1. A SOC restart power-on control device, characterized in that: The invention comprises a controller (1), a first power supply unit (2) connected to a SOC clock domain power supply terminal, a second power supply unit (3) connected to a SOC security domain power supply terminal, and a third power supply unit (4) electrically connected to a SOC application domain power supply terminal; Wherein, the first output end of the controller (1) is connected to the control end of the first power supply unit (2) and is used to control the operation of the first power supply unit (2); The second output terminal of the controller (1) is connected to the first input terminal of the SOC and is used to output a clock domain power-on PGOOD signal; the SOC performs self-startup after receiving the clock domain power-on PGOOD signal; The first output end of the SOC is connected to the control ends of the second power supply unit (3) and the third power supply unit (4), and is used to control the operation of the second power supply unit (3) and the third power supply unit (4).
2. The SOC restart power-on control device according to claim 1, characterized in that: The device further comprises a power supply (5), wherein the output end of the power supply (5) is electrically connected to the power supply ends of the first power supply unit (2), the second power supply unit (3) and the third power supply unit (4) respectively; The control end of the power supply (5) is connected to the third output end of the controller (1).
3. The SOC restart power-on control device according to claim 2, characterized in that: The first power supply unit (2), the second power supply unit (3) and the third power supply unit (4) include DC-DC converters.
4. The SOC restart power-on control device according to any one of claims 1 to 3, characterized in that: The device further comprises a logic judgment module (6), the output ends of the second power supply unit (3) and the third power supply unit (4) are connected to the input end of the logic judgment module (6); the output end of the logic judgment module (6) is connected to the second input end of the SOC, and is used to output a self-starting power supply success signal to the SOC.
5. The SOC restart power-on control device according to claim 4, characterized in that: The logic judgment module (6) includes an AND gate circuit.
6. The SOC restart power-on control device according to claim 5, characterized in that: The AND gate circuit comprises a first diode, a second diode and a resistor; the cathode of the first diode is electrically connected to the output end of the second power supply unit (3), the cathode of the second diode is electrically connected to the output end of the third power supply unit (4); and the anodes of the first diode and the second diode are electrically connected to one end of the resistor.
7. The SOC restart power-on control device according to claim 4, characterized in that: The second output terminal of the SOC is connected to the input terminal of the controller (1) and is used to notify the controller (1) that the SOC self-start is successful; the fourth output terminal of the controller (1) is connected to the input terminal of the SOC peripheral device and is used to output an enable signal to the SOC peripheral device.
8. A SOC chip, characterized in that: The SOC chip is connected to the SOC restart power-on control device according to any one of claims 1 to 7.
9. The SOC chip according to claim 8, characterized in that: The SOC chip includes an X9 series chip.
10. A device, characterized in that Comprising the SOC chip as claimed in claim 8.