Laminated chip inductor

Abstract

The utility model discloses a laminated chip inductor, which comprises a main body and an outer electrode, the outer electrode is arranged on the outer surface of the main body, the main body comprises a plurality of conductor layers and an insulating layer, the plurality of conductor layers are laminated, and two adjacent conductor layers are isolated by the insulating layer. The conductor layer comprises a middle wire part and a leading-out part, the middle wire part is communicated with the outer electrode through the leading-out part, the leading-out part comprises a coil structure and at least two leading-out ends, and the width sum of the leading-out ends is 15%-40% of the width or length of the laminated chip inductor. By adopting the structure with multiple leading-out ends, the open circuit condition caused by ablation of the leading-out parts or change of internal stress of the inductor is effectively reduced, and the overall reliability and durability of the inductor are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of inductors, in particular to a laminated chip inductor. Background Art

[0002] Multilayer chip inductors are inductors that offer excellent magnetic shielding, high sintering density, and strong mechanical strength. A typical multilayer chip inductor structure consists of a coiled internal electrode within a multilayer ceramic body, a lead terminal at the end of the internal coil electrode, and external electrodes formed on the end faces and surrounding side surfaces of the multilayer ceramic body to provide electrical connection to the lead terminal. The multilayer ceramic body is formed by laminating layers into a green body. After forming, the lead terminals are exposed at the ends of the green body. The green body is then sintered to form the ceramic body. External electrodes are formed on the ends of the ceramic body and surrounding side surfaces. Electrical connection is established between the external electrodes and the lead terminals of the internal coil electrode, creating a multilayer chip inductor.

[0003] Conventional designs have only one lead-out terminal, which is exposed only on one side of the multilayer ceramic body. However, during the densification process of the ceramic body during sintering, the lead-out terminal exposed on the side of the multilayer ceramic body will partially burn, seriously affecting the conductivity between the internal and external electrodes. In addition, if the substrate on which the multilayer chip inductor is attached is subjected to external force, the substrate will deform, causing internal stress in the multilayer chip inductor. The generation of internal stress may cause the conductive part between the lead-out terminal and the external electrode of the multilayer chip inductor to shift, resulting in a disconnection of the conductive connection. Utility Model Content

[0004] The technical problem to be solved by the present invention is that the internal coil of the current multilayer chip inductor has only one lead-out terminal, and the lead-out terminal is only exposed on one side of the outer periphery of the multilayer ceramic body. When the ceramic body is sintered and densified or when the substrate is deformed by external force, it is easy for the lead-out terminal to be partially burned or offset, resulting in a short circuit at the connection part.

[0005] To solve the above-mentioned technical problems, the present invention provides a multilayer chip inductor, comprising a main body and an external electrode, the external electrode being disposed on the outer surface of the main body. The main body comprises a plurality of conductor layers and an insulating layer, the plurality of conductor layers being stacked, with two adjacent conductor layers separated by the insulating layer. The conductor layers comprise an intermediate conductor portion and a lead portion, the intermediate conductor portion communicating with the external electrode via the lead portion. The lead portion comprises a coil structure and at least two lead ends, the sum of the widths of the lead ends being 15% to 40% of the width or length of the multilayer chip inductor.

[0006] Furthermore, the widths of the lead ends are equal or unequal;

[0007] When the widths of the lead ends are different, the ratio of the widths of two adjacent lead ends is ≤5.

[0008] Furthermore, the width ratio of two adjacent lead ends is 0.5-2.

[0009] Furthermore, the multilayer chip inductor further includes two end surfaces arranged along its width direction, the lead ends include first lead ends located on the end surfaces, and the interval between two adjacent first lead ends located on the same end surface is ≥20 μm.

[0010] Furthermore, the interval between two adjacent first lead-out ends located on the same end surface is 20-50 μm.

[0011] Furthermore, the multilayer chip inductor further includes two side surfaces arranged along its length direction, and the lead-out end further includes a second lead-out end located on the side surfaces.

[0012] Furthermore, the total width of the first lead-out terminal and the total width of the second lead-out terminal are equal to or different from each other;

[0013] When the total width of the first lead end is not equal to the total width of the second lead end, the total width of the first lead end is greater than the total width of the second lead end, and the ratio of the total width of the first lead end to the total width of the second lead end is greater than 1 and less than 3.

[0014] Furthermore, the distance between the second lead end closest to the end surface and the end surface is less than or equal to 3% of the length of the side surface;

[0015] The distance between the first lead-out end closest to the side surface and the side surface is greater than or equal to 5% of the length of the end surface where the first lead-out end is located, and less than or equal to 10% of the length of the end surface where the first lead-out end is located.

[0016] Furthermore, the distance between the second lead-out end closest to the end surface and the end surface is 1-3% of the length of the side surface where the second lead-out end is located.

[0017] Furthermore, the number of the lead-out terminals is 2-3.

[0018] Compared with the prior art, the multilayer chip inductor of the embodiment of the present invention has the following advantages:

[0019] By adopting a multi-terminal structure, the embodiment of the present invention effectively reduces the occurrence of short circuits in the conductive portion of the inductor, thereby improving the overall reliability and durability of the inductor. In addition, by designing the width and position of the multiple terminals, the embodiment effectively controls production costs while ensuring good electrical performance of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 1 is a schematic structural diagram of a multilayer chip inductor provided by an embodiment of the present utility model;

[0021] Figure 2 It is an exploded schematic diagram of the main body provided by an embodiment of the present utility model;

[0022] Figure 3 This is a schematic diagram of a first exemplary structure of a lead-out portion and an insulating layer provided in an embodiment of the present utility model;

[0023] Figure 4 This is a schematic diagram of a second exemplary structure of the lead-out portion and the insulating layer provided in an embodiment of the present utility model;

[0024] Figure 5 This is a schematic diagram of a third exemplary structure of the lead-out portion and the insulating layer provided in an embodiment of the present utility model;

[0025] In the figure, 1. main body; 11. conductor layer; 111. intermediate wire portion; 112. lead portion; 1121. coil structure; 1122. lead end; 11221. first lead end; 11222. second lead end; 12. insulating layer; 13. end face; 14. side face; 15. upper cover; 16. lower cover; 2. external electrode. DETAILED DESCRIPTION

[0026] The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0027] like Figure 1 and Figure 2 As shown, the present invention provides a multilayer chip inductor, including a main body 1 and an external electrode 2. The external electrode 2 is disposed on the outer surface of the main body 1. The main body 1 includes multiple conductor layers 11 and an insulating layer 12. The multiple conductor layers 11 are stacked, and two adjacent conductor layers 11 are separated by the insulating layer 12. The conductor layer 11 includes an intermediate conductor portion 111 and a lead portion 112. The intermediate conductor portion 111 is connected to the external electrode 2 through the lead portion 112. The lead portion 112 includes a coil structure 1121 and at least two lead ends 1122. The coil structure 1121 and the lead ends 1122 are disposed on the insulating layer 12. The sum of the widths of the lead ends 1122 is 15%-40% of the width or length of the multilayer chip inductor.

[0028] Based on the above structure, this embodiment effectively reduces the problem of short circuits caused by ablation of the lead portion 112 or changes in internal stress of the inductor by adopting a structure with multiple lead terminals 1122, thereby improving the overall reliability and durability of the inductor. In addition, this embodiment effectively controls production costs while ensuring good electrical performance of the product by designing the width and position of the multiple lead terminals. That is, this embodiment stipulates that the total width of each lead terminal 1122 accounts for 15%-40% of the product length or width in order to balance the relationship between contact area and material cost. If the width is too small, the contact area with the external electrode 2 is small, which is not conducive to connection; if the width is too large, the slurry is wasted. The appropriate width ensures sufficient contact area to ensure good electrical performance, while also avoiding the cost increase caused by excessive use of materials.

[0029] It should be noted that the multilayer chip inductor also includes two end faces 13 arranged along its width direction and two side faces 14 arranged along its length direction. When multiple lead ends 1122 are on the side faces 14 of the product, the total width of the lead ends 1122 thereon accounts for 15-40% of the product length; when multiple lead ends 1122 are on the end faces 13 of the product, the total width of the lead ends 1122 thereon accounts for 15-40% of the product width.

[0030] Understandably, if Figure 2 As shown, the main body 1 further includes an upper cover 15 and a lower cover 16. The upper cover 15, the lead portion 112, the intermediate conductor portion 111, the lead portion 112, and the lower cover 16 are stacked in this order. The upper cover 15, the lower cover 16, and the intermediate conductor portion 111 of this embodiment are common structures of existing inductors and will not be described in detail here. It should be noted that the number of intermediate conductor portions 111 in this embodiment can be one or multiple stacked.

[0031] In actual applications, the widths of the lead ends 1122 may be equal or different. It is understood that when the widths of the lead ends 1122 are different, the widths may be adjusted based on the current requirements of each lead end 1122. For example, if one lead end 1122 may be required to carry more current, the width of this lead end 1122 may be wider than the widths of the other lead ends 1122 to reduce resistance and heat generation.

[0032] Preferably, the widths of the various lead terminals 1122 vary, reducing the risk of failure of the entire device due to failure of a single lead terminal 1122. Even if a problem occurs with a narrow lead terminal 1122, the other wider lead terminals 1122 can still maintain circuit connectivity. The width ratio of two adjacent lead terminals 1122 is ≤ 5. When the width ratio of adjacent lead terminals 1122 is greater than 5, one lead terminal 1122 may be smaller in width. This smaller lead terminal 1122 will become even smaller after ablation, and will not function as an electrical connection.

[0033] More preferably, the width ratio of two adjacent lead ends 1122 is 0.5-2. When the width ratio of adjacent lead ends 1122 is less than 0.5, the width of one of the lead ends 1122 is too small, resulting in failure to provide electrical connection when ablation occurs.

[0034] See also Figure 3 Lead ends 1122 include a first lead end 11221 located on end surface 13. The spacing between two adjacent first lead ends 11221 located on the same end surface 13 is ≥ 20 μm. If the spacing is less than 20 μm, the distance between the two adjacent lead ends 1122 is too small, making them easily connected during screen printing, which is not conducive to screen printing. Preferably, the spacing between two adjacent first lead ends 11221 located on the same end surface 13 is 20-50 μm to balance the requirements of device miniaturization and avoid occupying more surface area.

[0035] like Figures 4 to 5 As shown, the lead-out end 1122 also includes a second lead-out end 11222 located on the side 14. It can be understood that a portion of the multiple lead-out ends 1122 are arranged on the end surface 13 (that is, the first lead-out end 11221), and another portion of the lead-out ends 1122 are arranged on the side surface 14 adjacent to the end surface 13 (that is, the second lead-out end 11222), wherein the total width of the second lead-out end 11222 on the side surface 14 is equal to or different from the total width of the first lead-out end 11221 on the end surface 13.

[0036] By also providing lead terminals 1122 on side surface 14, this embodiment increases the number of connection points between the inductor and the external circuit. This increases the overall reliability of the inductor by providing lead terminals 1122 at one location. Even if a problem occurs with a lead terminal 1122 at one location, lead terminals 1122 at other locations can still maintain circuit connectivity. As can be appreciated, if the total width of the second lead terminals 11222 on side surface 14 is equal to the total width of the first lead terminals 11221 on end surface 13, the manufacturing process can be simplified and each lead terminal 1122 can have similar electrical characteristics, such as impedance and heat capacity. Depending on the needs of the actual application, the total width of the lead terminals 1122 on side surface 14 and the total width of the lead terminals 1122 on end surface 13 can be designed to be different. For example, lead terminals 1122 that need to carry higher currents can be designed to be wider, while lead terminals 1122 used only for auxiliary connections or testing can be designed to be narrower, optimizing for specific functions while saving material costs.

[0037] Preferably, since the contact area between the end face 13 and the external electrode 2 is larger, the total width of the first lead end 11221 is greater than the total width of the second lead end 11222, and the ratio of the total width of the first lead end 11221 to the total width of the second lead end 11222 is greater than 1 and less than 3. If the ratio is less than 1, that is, the total width of the second lead end 11222 of the side 14 is large, which is not conducive to electrical connection; if the ratio is greater than 3, the second lead end 11222 of the side 14 is too small, and there will be partial defects during the chamfering sintering process.

[0038] Furthermore, the distance between the second lead end 11222 closest to the end surface 13 and the end surface 13 is less than or equal to 3% of the length of the side surface 14. If the distance is too large, the contact area with the external electrode 2 is small, which is not conducive to electrical connection. Preferably, the distance between the second lead end 11222 closest to the end surface 13 and the end surface 13 is 1-3% of the length of the side surface 14 on which it is located. If the distance is too small, the green body may suffer edge defects during transportation or contact before sintering, thereby damaging the second lead end 11222 on the side surface 14.

[0039] Furthermore, the first lead-out end 11221 closest to the side surface 14 is at a distance from the side surface 14 that is greater than or equal to 5% of the length of the end surface 13 on which it is located. If the distance between the first lead-out end 11221 and the side surface 14 is too close, the lead-out electrode is easily damaged during the chamfering process. In addition, the first lead-out end 11221 closest to the side surface 14 is at a distance from the side surface 14 that is less than or equal to 10% of the length of the end surface 13 on which it is located, so as to avoid the coil being positioned downward as a whole due to the distance being too large.

[0040] Furthermore, the number of lead-out terminals 1122 is 2-3. It is understandable that if there is only one connection point, the contact area with the external electrode 2 is small. If there are 4 or more, the screen design is difficult and printing is difficult.

[0041] In summary, the present invention provides a multilayer chip inductor that, through its multi-lead-out terminal 1122 structure, effectively reduces the occurrence of short circuits caused by ablation of the lead portion 112 or changes in internal stress within the inductor, thereby improving the overall reliability and durability of the inductor. Furthermore, the present embodiment stipulates that the total width of each lead-out terminal 1122 should account for 15%-40% of the product's length or width to balance the relationship between contact area and material cost. A width that is too small results in a small contact area with the external electrode 2, hindering connection; a width that is too large results in waste of slurry. An appropriate width ensures sufficient contact area to guarantee good electrical performance while also avoiding the cost increase caused by excessive material use.

[0042] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and replacements can be made without departing from the technical principles of the present invention. These improvements and replacements should also be regarded as the scope of protection of the present invention.

Claims

1. A multilayer chip inductor, characterized in that: The multilayer chip inductor comprises a main body and an external electrode, wherein the external electrode is arranged on the outer surface of the main body, the main body comprises a plurality of conductor layers and an insulating layer, the plurality of conductor layers are stacked, and two adjacent conductor layers are isolated by the insulating layer, the conductor layer comprises an intermediate conductor portion and a lead portion, the intermediate conductor portion is connected to the external electrode through the lead portion, the lead portion comprises a coil structure and at least two lead ends, and the sum of the widths of the lead ends is 15%-40% of the width or length of the multilayer chip inductor.

2. The multilayer chip inductor according to claim 1, wherein: The widths of the lead ends are equal or unequal; When the widths of the lead ends are different, the ratio of the widths of two adjacent lead ends is ≤5.

3. The multilayer chip inductor according to claim 2, wherein: The width ratio of two adjacent lead ends is 0.5-2.

4. The multilayer chip inductor according to any one of claims 1 to 3, characterized in that: The multilayer chip inductor further includes two end surfaces arranged along its width direction. The lead ends include first lead ends located on the end surfaces. The interval between two adjacent first lead ends located on the same end surface is ≥20 μm.

5. The multilayer chip inductor according to claim 4, wherein: The interval between two adjacent first lead-out ends located on the same end surface is 20-50 μm.

6. The multilayer chip inductor according to claim 4, wherein: The multilayer chip inductor further includes two side surfaces arranged along the length direction thereof, and the lead-out end further includes a second lead-out end located on the side surfaces.

7. The multilayer chip inductor according to claim 6, wherein: The total width of the first lead-out terminal and the total width of the second lead-out terminal are equal to or different from each other; When the total width of the first lead end is not equal to the total width of the second lead end, the total width of the first lead end is greater than the total width of the second lead end, and the ratio of the total width of the first lead end to the total width of the second lead end is greater than 1 and less than 3.

8. The multilayer chip inductor according to claim 6, wherein: The distance between the second lead end closest to the end surface and the end surface is less than or equal to 3% of the length of the side surface; The distance between the first lead-out end closest to the side surface and the side surface is greater than or equal to 5% of the length of the end surface where the first lead-out end is located, and less than or equal to 10% of the length of the end surface where the first lead-out end is located.

9. The multilayer chip inductor according to claim 6, wherein: The distance between the second lead-out end closest to the end surface and the end surface is 1-3% of the length of the side surface where the second lead-out end is located.

10. The multilayer chip inductor according to claim 1, wherein: The number of the lead-out terminals is 2-3.

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