Anti-layering packaging structure

Abstract

The utility model provides an anti-layering packaging structure, comprising a lead frame comprising a chip carrier and pins; the semiconductor device is bonded on the chip carrier; a bridging strip electrically connected to the semiconductor device and the pin; the side wall of at least one of the chip carrier, the pins and the bridging strip is provided with a groove structure. And the plastic package layer wraps the lead frame, the semiconductor device and the bridging strip, and the plastic package layer is also filled into the groove structure to form an embedded structure. According to the utility model, the groove structures are designed on the side surfaces of the lead frame and the copper sheet, the groove structures and the plastic packaging layer form the embedded structure, and the embedded structure enables the peripheries and corners of the lead frame and the copper sheet to be difficult to layer, so that the requirement of zero layering on the lead frame and the copper sheet is met.

Description

Technical Field

[0001] The utility model belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to an anti-delamination packaging structure. Background Art

[0002] With the rapid development of microelectronics technology, metal oxide semiconductor field-effect transistor (MOSFET) chips are increasingly used in electronic devices. Delamination is a common defect mode in the packaging process of MOSFET chips, seriously affecting the chip's reliability and stability. Delamination typically occurs between the chip's lead frame and the encapsulation resin, leading to electrical connection failure and potentially even device malfunction.

[0003] To address delamination, the industry's current solution is to roughen the leadframe. This treatment increases the surface roughness of the leadframe, enhancing the mechanical bond between the leadframe and the encapsulation resin, thereby minimizing delamination. However, this approach has limitations.

[0004] On the one hand, automotive electronics products have extremely high requirements for reliability and stability. Automotive-grade products operate in environments with extreme temperatures, humidity, and vibration, and therefore have a low tolerance for delamination. Traditional frame roughening methods cannot meet the stringent chip delamination requirements of automotive-grade products, necessitating more advanced technologies to address this issue.

[0005] On the other hand, with the advancement of packaging technology, copper clip bonding has become the mainstream due to its high efficiency and low cost. However, compared with the traditional gold / copper / aluminum (Au / Cu / Al) bonding method, copper clip bonding has a more serious problem of interface delamination.

[0006] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Utility Model Content

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an anti-delamination packaging structure for solving the problem that the copper sheet and / or lead frame in the prior art is prone to delamination defects.

[0008] To achieve the above-mentioned objectives and other related objectives, the present invention provides an anti-delamination packaging structure, which includes: a lead frame, including a chip carrier and pins; a semiconductor device, bonded to the chip carrier; a jumper strip, electrically connected to the semiconductor device and the pins; wherein the sidewall of at least one of the chip carrier, the pins and the jumper strip is provided with a groove structure; and a plastic encapsulation layer, covering the lead frame, the semiconductor device and the jumper strip, and the plastic encapsulation layer is also filled with the groove structure to form a mosaic structure.

[0009] Optionally, the material of the lead frame includes copper, and the material of the jumper strip includes copper.

[0010] Optionally, sidewalls of at least two of the chip carrier, the pins, and the jumper strips are provided with groove structures.

[0011] Optionally, sidewalls of the chip carrier, the pins, and the jumper strips are all provided with groove structures.

[0012] Optionally, the groove structure is a continuous groove or a plurality of intermittent grooves arranged at intervals on the side walls around the chip carrier, the pins and the jumper strips.

[0013] Optionally, the groove structure has a width ranging from 75 micrometers to 125 micrometers, and a depth ranging from 75 micrometers to 125 micrometers.

[0014] Optionally, the lead frame has a thickness ranging from 150 micrometers to 2000 micrometers.

[0015] Optionally, the thickness of the bridging strip is in the range of 100 microns to 250 microns.

[0016] Optionally, the semiconductor device includes a MOS device, and the pins of the lead frame include a source pin and a gate pin, wherein the drain of the MOS device is connected to the chip carrier, the source of the MOS device is connected to the source pin through a first jumper strip, and the gate of the MOS device is connected to the gate pin through a second jumper strip or a bonding wire.

[0017] Optionally, when the gate of the MOS device is connected to the gate pin through the second jumper strip, a groove structure is provided on the sidewall of the second jumper strip.

[0018] Optionally, the material of the plastic packaging layer includes resin.

[0019] As described above, the anti-delamination packaging structure of the present invention has the following beneficial effects:

[0020] The present invention addresses the mechanism in which products based on copper clip packaging usually experience delamination starting from the four sides and corners and then gradually spreading toward the center. The present invention designs a groove structure on the side of the lead frame and the copper clip. The groove structure and the plastic encapsulation layer form a chimeric structure. The chimeric structure can prevent delamination from occurring around the four sides and corners of the lead frame and the copper clip, thereby meeting the demand for zero delamination on the lead frame and the copper clip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to illustrate the implementation of the present application and, together with the text description, to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0022] Figure 1 It is a schematic cross-sectional view of the anti-delamination packaging structure according to an embodiment of the present invention. Figure 2 The figure shows a top view of the anti-delamination packaging structure according to an embodiment of the present invention, wherein: Figure 1 To correspond Figure 2 Schematic diagram of the cross-sectional structure at A-A'.

[0023] Component number description

[0024] 10 Lead frame

[0025] 101 Chip Carrier

[0026] 102 Source pin

[0027] 103 Gate pin

[0028] 11 MOS devices

[0029] 111 Drain

[0030] 112 Source

[0031] 113 Gate

[0032] 12 jumper strips

[0033] 13 Groove structure

[0034] 14. Wire Bonding

[0035] 15 Plastic layer DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.

[0037] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0038] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0039] For ease of explanation, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged and not to scale. These schematic views are merely illustrative and should not limit the scope of protection of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0040] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0041] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0042] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0043] like Figure 1 and Figure 2 As shown, Figure 1 Corresponding to Figure 2 The cross-sectional structure diagram at AA′ in FIG. 1 shows a schematic diagram of a cross-sectional structure. This embodiment provides an anti-delamination packaging structure. The packaging structure includes: a lead frame 10 , a semiconductor device, a jumper strip 12 and a plastic packaging layer 15 .

[0044] like Figure 1 and Figure 2 As shown, the lead frame 10 includes a chip carrier 101 and pins. The chip carrier 101 provides necessary support for the device or chip and can also be used to electrically connect one or more electrodes of the device or chip. The pins can be spaced apart from the chip carrier 101 and can be used to electrically connect other electrodes of the device or chip other than those connected to the chip carrier 101. In one embodiment, the lead frame 10 can be made of copper. Of course, in other embodiments, the lead frame 10 can also be made of other materials, such as aluminum, tin, etc., and is not limited to the examples listed here.

[0045] The thickness of the lead frame 10 can be determined based on the actual requirements of the device. In some embodiments, the thickness of the lead frame 10 can range from 150 microns to 2000 microns. Based on the conductivity requirements, heat dissipation requirements of the device and the manufacturing cost requirements of the lead frame 10, the thickness of the lead frame 10 is preferably between 200 microns and 800 microns. In some embodiments, the thickness of the lead frame 10 can be 150 microns, 300 microns, 500 microns, 800 microns, etc. For devices with high power and high heat dissipation requirements, the lead frame 10 can be 1000 microns, 1500 microns, 2000 microns, etc.

[0046] like Figure 1 and Figure 2 As shown, a semiconductor device is bonded to chip carrier 101. The semiconductor device may be, for example, a MOS device, a transistor device, an IGBT device, a memory device, a logic circuit, etc., and is not limited to the examples listed here. In one embodiment, the semiconductor device is a MOS device, such as an NMOS device, a PMOS device, or a CMOS device.

[0047] like Figure 1 and Figure 2 As shown, the jumper strip 12 electrically connects the semiconductor device and the pin. One end of the jumper strip 12 can be connected to the semiconductor device electrode by welding or bonding, for example, while the other end spans the gap between the semiconductor device and the pin and is connected to the pin by welding or bonding. In one embodiment, the jumper strip 12 is made of copper. The thickness of the jumper strip 12 ranges from 100 microns to 250 microns. For example, the thickness of the jumper strip 12 can be 100 microns, 150 microns, 200 microns, 250 microns, etc., but is not limited to the examples listed here.

[0048] The side wall of at least one of the chip carrier 101, the pins and the jumper strips 12 is provided with a groove structure 13. The cross-sectional shape of the groove structure 13 can be, for example, rectangular, U-shaped, trapezoidal, etc., and is not limited to the examples listed here. The plastic layer 15 covers the lead frame 10, the semiconductor device and the jumper strips 12, and the plastic layer 15 is also filled with the groove structure 13 to form a mosaic structure. In one embodiment, the material of the plastic layer 15 can be resin. When the side wall of one of the chip carrier 101, the pins and the jumper strips 12 is selected to be provided with a groove structure 13, the priority of setting the groove structure 13 can be the jumper strip 12, the chip carrier 101 and the pins in sequence, but in actual application, it is not limited to the setting of the groove structure 13 in the above-mentioned order of priority.

[0049] In one embodiment, the width of the groove structure 13 ranges from 75 microns to 125 microns, and the depth ranges from 75 microns to 125 microns. The groove structure 13 with this width and depth range can, on the one hand, ensure that the formation of the groove does not affect the mechanical strength of the chip carrier 101, the pins and the jumper strip 12. On the other hand, it can ensure that the preparation of the groove structure 13 will not increase the difficulty of preparation due to its small scale. More importantly, the groove structure 13 with this width and depth range can ensure that the plastic encapsulation layer 15 can be effectively filled, and ensure that the plastic encapsulation layer 15 can effectively fill the groove structure 13 and form a mosaic structure with high strength with the groove structure 13.

[0050] In some embodiments, groove structures 13 are provided on the sidewalls of at least two of the chip carrier 101, the pins, and the jumper strips 12. Preferably, if groove structures 13 are provided on the sidewalls of at least two of the chip carrier 101, the pins, and the jumper strips 12, groove structures 13 are first provided on the sidewalls of the jumper strips 12, which are more prone to delamination, and then on the sidewalls of the chip carrier 101, which is also more prone to delamination. Of course, groove structures 13 can also be provided on the sidewalls of both the jumper strips 12 and the pins.

[0051] like Figure 1 and Figure 2 As shown, in one embodiment, the sidewalls of the chip carrier 101 , pins and jumper strips 12 are all provided with groove structures 13 , and the groove structures 13 on the sidewalls of the chip carrier 101 , pins and jumper strips 12 form a chimeric structure with the plastic packaging layer 15 .

[0052] In one embodiment, the groove structure 13 is a continuous groove or a plurality of intermittent grooves arranged at intervals on the sidewalls surrounding the chip carrier 101, the pins, and the jumper strips 12. In a specific embodiment, the groove structure 13 is disposed on the sidewalls surrounding the chip carrier 101, the pins, and the jumper strips 12, and in the corner areas between the sidewalls.

[0053] In one embodiment, Figure 1 and Figure 2 As shown, the semiconductor device is a MOS device 11, which includes a source 112, a drain 111 and a gate 113. The pins of the lead frame 10 include a source 112 pin 102 and a gate 113 pin 103. The drain 111 of the MOS device 11 is connected to the chip carrier 101, the source 112 of the MOS device 11 is connected to the source 112 pin 102 via a first jumper strip, and the gate 113 of the MOS device 11 is connected to the gate 113 pin 103 via a second jumper strip or a bonding wire 14.

[0054] In one embodiment, when the gate 113 of the MOS device 11 is connected to the gate 113 pin 103 through the second jumper strip, the sidewall of the second jumper strip is provided with a groove structure 13, and the sidewall of the second jumper strip provided with the groove structure 13 also cooperates with the plastic packaging layer 15 to form a mosaic structure.

[0055] As described above, the anti-delamination packaging structure of the present invention has the following beneficial effects:

[0056] The present invention addresses the mechanism in which products based on copper clip packaging usually experience delamination starting from the four sides and corners and then gradually spreading toward the center. The present invention designs a groove structure on the side of the lead frame and the copper clip. The groove structure and the plastic encapsulation layer form a chimeric structure. The chimeric structure can prevent delamination from occurring around the four sides and corners of the lead frame and the copper clip, thereby meeting the demand for zero delamination on the lead frame and the copper clip.

[0057] Therefore, the utility model effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed in the present invention are intended to be covered by the claims of the present invention.

Claims

1. An anti-delamination packaging structure, characterized in that: The packaging structure includes: Lead frame, including chip carrier and pins; a semiconductor device bonded to the chip carrier; A jumper strip electrically connected to the semiconductor device and the pin; wherein a groove structure is provided on a sidewall of at least one of the chip carrier, the pins and the jumper strips; The plastic packaging layer covers the lead frame, the semiconductor device and the jumper strip, and the plastic packaging layer is also filled into the groove structure to form a mosaic structure.

2. The anti-delamination packaging structure according to claim 1, characterized in that: The lead frame is made of copper, and the jumper strip is made of copper.

3. The anti-delamination packaging structure according to claim 1, characterized in that: At least two sidewalls of the chip carrier, the pins, and the jumper strips are provided with groove structures.

4. The anti-delamination packaging structure according to claim 3, characterized in that: The side walls of the chip carrier, the pins and the bridging strips are all provided with groove structures.

5. The anti-delamination packaging structure according to claim 1, characterized in that: The groove structure is a continuous groove or a plurality of intermittent grooves arranged at intervals on the side walls around the chip carrier, the pins and the bridging strips.

6. The anti-delamination packaging structure according to claim 1, characterized in that: The width of the groove structure ranges from 75 microns to 125 microns, and the depth ranges from 75 microns to 125 microns.

7. The anti-delamination packaging structure according to claim 1, characterized in that: The lead frame has a thickness ranging from 150 microns to 2000 microns.

8. The anti-delamination packaging structure according to claim 1, characterized in that: The thickness of the bridging strip ranges from 100 microns to 250 microns.

9. The anti-delamination packaging structure according to claim 1, characterized in that: The semiconductor device includes a MOS device, and the pins of the lead frame include a source pin and a gate pin, wherein the drain of the MOS device is connected to the chip carrier, the source of the MOS device is connected to the source pin via a first jumper strip, and the gate of the MOS device is connected to the gate pin via a second jumper strip or a bonding wire.

10. The anti-delamination packaging structure according to claim 9, characterized in that: When the gate of the MOS device is connected to the gate pin through the second jumper strip, a groove structure is provided on the sidewall of the second jumper strip.

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