Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel. The array substrate comprises a common electrode layer; the pixel electrode layer is located on the side, away from the data lines, of the common electrode layer and comprises a plurality of pixel electrode rows extending in the first direction. The pixel electrode row comprises a plurality of pixel electrode groups arranged along the first direction; the pixel electrode group comprises two pixel electrodes, and any pixel electrode in the pixel electrode group crosses the other pixel electrode and is electrically connected with the data line through the transistor; at least one of the common electrode layer and the pixel electrode layer comprises a plurality of first wires extending along the second direction; the first wire is electrically connected with the common electrode, and the orthographic projection of the first wire on the substrate covers the orthographic projection of the data line on the substrate.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] At the same resolution, the dual-gate pixel architecture can halve the number of source drivers compared to the single-gate pixel architecture, thereby reducing IC costs and serving as an effective low-cost solution. Utility Model Content

[0003] The utility model provides an array substrate and a display panel. The array substrate includes:

[0004] substrate;

[0005] multiple transistors;

[0006] A plurality of gate line groups are located on one side of the substrate, the gate line groups comprising: two gate lines extending along the first direction;

[0007] Multiple data lines;

[0008] a common electrode layer, located on a side of the data line facing away from the substrate; the common electrode layer includes a plurality of common electrodes;

[0009] a pixel electrode layer, located on a side of the common electrode layer facing away from the data line, comprising: a plurality of pixel electrode rows extending along a first direction; the pixel electrode rows comprising a plurality of pixel electrode groups arranged along the first direction; the gate line group being located in an area between adjacent pixel electrode rows, the pixel electrode group being located in an area formed by the intersection of the gate line group and the data line; the pixel electrode group comprising two pixel electrodes, and any pixel electrode in the pixel electrode group being electrically connected to the data line via the transistor across the other pixel electrode;

[0010] Among them, at least one of the common electrode layer and the pixel electrode layer includes: multiple first traces extending along the second direction; the first traces are electrically connected to the common electrode, and the orthographic projection of the first trace on the substrate covers the orthographic projection of the data line on the substrate.

[0011] In a possible implementation manner, the first wiring is located in the pixel electrode layer;

[0012] The common electrode layer has a first hollow; the orthographic projection of the first wiring on the substrate overlaps with the orthographic projection of the first hollow on the substrate.

[0013] In a possible implementation manner, the first wiring is disconnected at the position of the gate line group.

[0014] In a possible implementation, the common electrodes extend along the first direction and are arranged along the second direction, and an orthographic projection of the common electrodes on the substrate and an area between adjacent gate line groups are within the orthographic projection of the substrate;

[0015] The common electrode has a connecting portion at at least one end of the first hollow portion, and the common electrode is electrically connected to the first wiring through a first via hole at the connecting portion.

[0016] In a possible implementation manner, an extension length of the first trace is greater than an extension length of the first hollow portion.

[0017] In a possible implementation manner, the orthographic projection of the first trace on the substrate covers the orthographic projection of the first hollow on the substrate, and covers the orthographic projection of the connecting portion on the substrate.

[0018] In a possible implementation manner, the orthographic projection of the first wiring on the substrate covers the orthographic projection of a portion of the common electrode on both sides of the first hollow on the substrate.

[0019] In a possible implementation manner, the orthographic projection of the first wiring on the substrate does not overlap with the orthographic projections of the common electrodes on both sides of the first hollow on the substrate.

[0020] In a possible implementation manner, the first wiring is located in the common electrode layer and is integrally connected to the common electrode.

[0021] In a possible implementation manner, the orthographic projection of the outer edge of the pixel electrode on the substrate coincides with the outer edge of the data line on the substrate.

[0022] In a possible embodiment, the array substrate further includes: a plurality of second routing lines, and a plurality of second via groups; the second via group includes: two second vias; the two second vias of the second via group are respectively located on both sides of the gate line group and on different sides of the second routing line; the common electrodes on both sides of the gate line group are electrically connected to the second routing line through the two second vias of the second via group.

[0023] In a possible embodiment, the second trace and the data line are formed in the same layer and material; the array substrate further comprises: an organic insulating layer located between the data line and the common electrode layer, and a passivation layer located between the common electrode layer and the pixel electrode layer; the pixel electrode layer further comprises: an overlapping portion;

[0024] The second via hole penetrates the passivation layer and the organic insulating layer, and exposes a portion of the second wiring and a portion of the common electrode. The overlapping portion contacts the common electrode and the second wiring through the second via hole.

[0025] In a possible implementation, the common electrode has a recessed portion at the location of the second via hole; the orthographic projection of the second via hole on the substrate partially overlaps with the recessed portion and partially overlaps with the common electrode on a side of the recessed portion away from the gate line group.

[0026] In a possible implementation manner, the second wiring is located on a side of the common electrode layer facing the substrate and is in direct contact with the common electrode.

[0027] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram comparing the single gate pixel architecture and the dual gate pixel architecture;

[0029] Figure 2 This is the timing diagram of the dual gate pixel architecture in a monochrome red screen;

[0030] Figure 3 Schematic diagrams of two dual gate pixel architectures provided in embodiments of the present disclosure;

[0031] Figure 4 This is a schematic diagram of the display panel when it is refreshed;

[0032] Figure 5 This is a schematic diagram of data signal transition between frames of the RG mixed color screen;

[0033] Figure 6 This is a schematic diagram of the vertical color stripes produced when the RG color mixing screen is used;

[0034] Figure 7 is a schematic diagram of the vertical crosstalk pattern;

[0035] Figure 8 A schematic diagram of a vertical crosstalk pattern during data signal transition between frames;

[0036] Figure 9 A schematic diagram of a vertical crosstalk pattern in which parts are brighter and parts are darker when the data signal jumps between frames;

[0037] Figure 10 Schematic diagram of the array substrate structure and process flow of related technology;

[0038] Figure 11 for Figure 10 A schematic cross-sectional view at the data line position;

[0039] Figure 12A This is one of the schematic top views of the array substrate provided in the embodiment of the present disclosure;

[0040] Figure 12B for Figure 12A Schematic diagram of a single film layer in the middle gate line layer;

[0041] Figure 12C for Figure 12A Schematic diagram of a single film layer in the data line layer;

[0042] Figure 12D for Figure 12A Schematic diagram of a single film layer of the common electrode layer;

[0043] Figure 12E for Figure 12A Schematic diagram of a single film layer of the pixel electrode layer;

[0044] Figure 12F for Figure 12A Schematic diagram of the cross section along the dotted line e1;

[0045] Figure 12G A schematic cross-sectional view of another array substrate provided in an embodiment of the present disclosure;

[0046] Figure 13A A second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0047] Figure 13B for Figure 13A A partial enlarged schematic diagram;

[0048] Figure 13C for Figure 13A A schematic cross-sectional view along the dotted line e2;

[0049] Figure 13D for Figure 13A A schematic cross-sectional view along the dotted line e3;

[0050] Figure 13E for Figure 13B A schematic cross-sectional view along the dotted line e4;

[0051] Figure 14A This is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0052] Figure 14B for Figure 14A A schematic cross-sectional view along the dotted line e5;

[0053] Figure 15One of the cross-sectional schematic diagrams of a display panel provided for implementation of the present disclosure;

[0054] Figure 16 A fingerprint of a display panel structure diagram provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0057] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0058] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0059] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0060] Combine Figure 1 As shown, the Dual gate pixel architecture has half the number of data lines (Data) and twice the number of gate lines (Gate) compared to the Single Gate pixel architecture, so the pixel charging time of each row is also halved. In other words, the Dualgate pixel architecture saves the number of ICs at the expense of the pixel charging rate. Insufficient pixel charging rate will bring some problems related to image quality, such as common red, green and blue monochrome images or mixed color images, such as monochrome red (R), monochrome green (G), monochrome blue (B), red and green mixed color (yellow), red and blue mixed color (magenta), blue and green mixed color (indigo) will have horizontal or vertical stripes because some pixels have a long pre-charge charging time and some pixels do not have a short pre-charge charging time. Figure 1 Take the Dualgate pixel architecture on the right for example: the high level of each gate line will last for 4 hours (4 hours is used as an example, but 2 hours, 3 hours, 4 hours, 5 hours, 6 hours, 7 hours, and 8 hours are applicable). The gate signals corresponding to sub-pixels R1, R2, R3, and R4 are G1, G2, G3, and G4 respectively. See the timing diagram for details. Figure 2The final hour of the 4-hour high-level period for G1 / G2 / G3 / G4 is the actual data charging time for R1 / R2 / R3 / R4; the preceding 3 hours are pre-charging time. D1 / D2 / D3 are the data signals for R1 / R2 & R3 / R4, respectively. For the three red sub-pixels R1 / R2 / R4, during the first hour of their charging, the data line voltage levels are inconsistent with the charge levels of the corresponding red sub-pixels, making pre-charging impossible. This means that the actual charging time for each red sub-pixel is 1 hour (1 hour = 1.85us in 8K Dual Gate 60Hz products). Taking signal line delay into account, the actual charging time is even shorter than 1.85us. For R3, during the first hour of its charging, the data signal is R2's data. Since R3 and R2 must be charged with the same data, this results in a 2-hour charging time for R3. This results in a higher charging rate for R3 than for R1 / 2 / 4, resulting in uneven brightness on the screen.

[0061] In the Dual gate pixel architecture, some pixel architectures are all long-connected pixel architectures (each data line drives a sub-pixel at intervals of one sub-pixel, so the path from the data line to the sub-pixel it actually drives is long, hence the name). Figure 3 As shown, the sub-pixels connected to the same data line have the same color. These two architectures do not exhibit image quality issues such as horizontal, vertical, or diagonal stripes caused by different pre-charge times when displaying monochrome or mixed-color images. However, other issues exist. The main issues are mixed-color vertical stripes caused by parasitic capacitance Cpd between the data line and the pixel electrode, as well as V-crosstalk.

[0062] The mechanism of color mixing vertical lines caused by parasitic capacitance Cpd coupling: combined Figure 4 、 Figure 5 、 Figure 6As shown, the display panel is charged row by row from the opposite side of the bonded area (DPO) to the bonded area (DP). The pixels on the DP side of this frame (N frame) have just been charged. After a short blanking period between frames, the polarity of the data of the next frame is reversed and the pixels on the DPO side begin to be charged. The polarity reversal △Vdata between frames causes the DP side pixel voltage Vpixel to jump through Cpd coupling (△Vpixel=Cpd*△Vdata / Ctotal The voltage jump of the pixel on the DP side lasts for nearly one frame, so the pixel on the DP side is most affected by the polarity switching between Data frames; take RG color mixing as an example: the voltage of D1 / D2 / D4 / D5 that charges R and G jumps when the frame switches, and the voltage of D3 / D6 that charges B does not jump when the frame switches. The R and G pixel electrodes next to D1 / D2 / D4 / D5 will be pulled by the Data jump, and the "-" pixel will be pulled down, and the "+" pixel will be pulled up, and both will become brighter; the R and G pixels next to D3 / D6 will not be pulled, and the brightness remains unchanged, resulting in the following Figure 6 Shown are alternating light and dark vertical stripes.

[0063] Parasitic capacitance Cpd coupling leads to V-crosstalk mechanism: For example Figure 7 As shown, the grayscale 127 is used as the background, and the grayscale 255 pattern is displayed in the middle. The grayscale 255 pattern occupies 1 / 2 of the vertical length of the entire display panel in the vertical (V) direction. Figure 8 The data line is shown in the V-crosstalk pattern. Figure 7 Schematic diagram of voltage jump at different positions of the display panel, V-Crosstalk phenomenon caused by parasitic capacitance Cpd coupling Figure 9 As shown in FIG, the display panel may appear partially dark and partially bright in the vertical direction, that is, Figure 9 In the figure, region ① is dark due to coupling, and region ③ is bright due to coupling.

[0064] The use of all long-connected Dual gate pixel architecture can improve the shaking head problem through high resolution and high refresh rate. Figure 3As shown, using a fully connected dual gate pixel architecture, the entire display panel presents two columns of sub-pixels with the same polarity. This is because the voltage setting of the common electrode cannot ensure that all sub-pixels have completely consistent brightness at the same grayscale. In particular, when sub-pixels with positive polarity relative to the common electrode and sub-pixels with negative polarity relative to the common electrode display the same grayscale, the sub-pixels will display different brightness. This inconsistency can cause head shaking (a phenomenon in which the human eye misses some frames when it is not in a static state, causing the eye to continuously see positive or negative frames, resulting in some alternating bright and dark patterns). The fully connected dual gate display architecture widens the interval between bright and dark, making this difference easier for the human eye to perceive, thus exacerbating the head shaking phenomenon. However, if this design is used on a higher-resolution (PPI) display panel, the head shaking phenomenon can be alleviated due to the smaller sub-pixel size. Alternatively, a high refresh rate can be used to prevent the human eye from distinguishing the difference in time.

[0065] Based on this high refresh rate and high PPI display panel, in order to ensure the high transmittance and driving capability requirements of the display panel, a high transmittance hyper-dimensional switch display mode (High transmittance-Advanced Dimension Switch, HADS) is usually adopted, and an organic film is used in the process to reduce the load of the data signal line. Figure 10-11 As shown, the pixel plan and process flow of HADS are generally as follows: Figure 10 As shown in FIG, the process of the TFT substrate is Gate metal → insulating layer → semiconductor layer → source and drain metal layer (including data line) → organic film insulating layer ORG → transparent pixel electrode → insulating layer → common electrode layer; because the characteristic of the HADS pixel mode is that the transparent common electrode must completely cover the data line to shield the electric field of the data line, so that the black matrix area blocked above the data line can be small (the black matrix in this pixel structure is only used to prevent the color filter color resistance of adjacent sub-pixels from crossing colors when the alignment deviation between the color filter substrate and the array substrate is large) to achieve an increase in the pixel aperture ratio; placing the ORG layer after the source and drain metal layer can reduce the parasitic capacitance between the data line and the common electrode covering it, which can reduce the load of the data line and improve the pixel charging rate on the one hand; on the other hand, it can also reduce the coupling effect of the data line jump on the common electrode and reduce the risk of H-crosstalk; the cross-sectional view of this pixel structure above the data line is shown in FIG. Figure 11 As shown, in order to ensure the light transmittance efficiency of the pixel, the projection of the edge of the pixel electrode is set between the two patterns of the common electrode layer (referring to the common electrode layer, between the pattern covering the data line and the adjacent common electrode pattern). However, with such a setting, there is still a large lateral parasitic capacitance Cpd between the data line through the organic insulating layer and the pixel electrode.

[0066] See also Figures 12A-12F As shown, Figure 12B for Figure 12A Schematic diagram of a single film layer in the middle gate line layer. Figure 12C for Figure 12A Schematic diagram of a single film layer in the data line layer, Figure 12D for Figure 12A Schematic diagram of a single film layer of the common electrode layer, Figure 12E for Figure 12A Schematic diagram of a single film layer of the pixel electrode layer, Figure 12F for Figure 12A The cross-sectional view along the dotted line e1 in FIG. 1 shows an embodiment of the present disclosure that provides an array substrate, comprising:

[0067] Substrate 1;

[0068] a plurality of transistors T;

[0069] A plurality of gate line groups 20 are located on one side of the substrate 1 , and the gate line group 20 includes: two gate lines 2 extending along a first direction X;

[0070] Multiple data lines 3;

[0071] The common electrode layer 40 is located on the side of the data line 3 facing away from the substrate 1; the common electrode layer 40 includes a plurality of common electrodes 4;

[0072] The pixel electrode layer 50 is located on a side of the common electrode layer 40 facing away from the data line 3 and includes: a plurality of pixel electrode rows 500 extending along a first direction X; the pixel electrode rows 500 include a plurality of pixel electrode groups PZ arranged along the first direction X; the gate line group 20 is located in a region between adjacent pixel electrode rows 500, and the pixel electrode group PZ is located in a region formed by the intersection of the gate line group 20 and the data line 3; the pixel electrode group PZ includes two pixel electrodes 5, and any pixel electrode 5 in the pixel electrode group PZ is electrically connected to the data line 3 via the transistor T across the other pixel electrode 5;

[0073] Among them, at least one of the common electrode layer 40 and the pixel electrode layer 50 includes: multiple first traces 6 extending along the second direction Y; the first traces 6 are electrically connected to the common electrode 4, and the orthographic projection of the first traces 6 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1.

[0074] In the embodiment of the present disclosure, any pixel electrode 5 in the pixel electrode group PZ is electrically connected to the data line 3 through the transistor T across another pixel electrode 5, that is, a pixel architecture with all long connections, which can avoid horizontal stripes, vertical stripes, diagonal stripes and other image quality problems caused by different pre-charging times when displaying monochrome or mixed color images; moreover, in the embodiment of the present disclosure, the array substrate includes a first trace 6 electrically connected to the common electrode 4 and covering the data line 3, which can have a high aperture ratio, high transmittance, and a high pixel charging rate, thereby reducing horizontal crosstalk; in addition, the pixel electrode layer 50 is located on the side of the common electrode layer 40 away from the data line 3, which can make the pixel electrode 5 and the data line 3 farther apart in the direction perpendicular to the substrate 1, with more insulating layers in between, which can reduce the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3, and improve the vertical stripes and vertical crosstalk problems caused by the parasitic capacitance Cpd in monochrome or mixed color images.

[0075] In one possible embodiment, combining Figure 3 As shown, in the embodiment of the present disclosure, sub-pixels electrically connected to the same data line can have the same color. That is, by providing color resists of the same color in the corresponding areas of the color filter substrate through transistors in the regions of each pixel electrode electrically connected to the same data line, the sub-pixels electrically connected to the same data line can have the same color.

[0076] The array substrate of the embodiment of the present disclosure can be applied to display products with high resolution and high refresh rate; in the embodiment of the present disclosure, it can be adapted to display products with a resolution (PPI) ≥ 27-inch 4K, that is, products with a PPI of 160 or more; it can be adapted to display panels with a refresh rate ≥ 120Hz. That is, in the embodiment of the present disclosure, the resolution of the display panel can be 160 or more, and the refresh rate can be higher than 120Hz. The embodiment of the present disclosure is suitable for high refresh rate or high resolution products. For low cost considerations, it utilizes a fully long-connected Dual gate pixel architecture to circumvent the horizontal and vertical stripes on the image quality caused by the charging rate in the single-color and mixed-color display products of the prior art Dual gate pixel architecture, and proposes to reduce or eliminate the parasitic capacitance Cpd between the pixel electrode and the data line for the high-transmittance HADS pixel architecture, thereby improving the poor image quality problem caused by the coupling of the parasitic capacitance Cpd in the fully long-connected Dual gate pixel architecture.

[0077] In one possible embodiment, combining Figures 12A-12FAs shown, the first routing line 6 is located in the pixel electrode layer 50; the common electrode layer 40 has a first hollow 41; the orthographic projection of the first routing line 6 on the substrate 1 overlaps with the orthographic projection of the first hollow 41 on the substrate 1. In the embodiment of the present disclosure, the first routing line 6 is located in the pixel electrode layer 50, and the common electrode layer 40 has a first hollow 41 at the position of the data line 3, wherein the combination of the first routing line 6 and the common electrode 4 can cover the data line 3 and shield the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3; moreover, the dielectric layer at the overlapping position of the data line 3 and the common electrode is a superposition of the organic film layer 92 and the passivation layer 93, which reduces the parasitic capacitance between the data line 3 and the common electrode (the first routing line 6) covering it, thereby reducing the load of the data line, improving the pixel charging rate, and reducing the coupling effect of the voltage polarity jump of the data line 3 on the common electrode, thereby reducing the problem of horizontal crosstalk.

[0078] In one possible implementation, see Figures 12A-12F As shown, the orthographic projection shape of the first hollow 41 on the substrate 1 can be consistent with the shape of the data line 3 at that position. For example, if the data line 3 is bent, the first hollow 41 is also bent.

[0079] In one possible implementation, see Figures 12A-12F As shown, the first trace 6 is disconnected at the position of the gate line group 20. In the embodiment of the present disclosure, the first trace 6 covering the data line 3 does not need to completely cover the entire data line 3, and can be disconnected at the position of the gate line group 20. That is, at the position corresponding to the black matrix position of the color filter substrate covering the gate line group 20, the first trace 6 does not need to cover the data line 3, further reducing the parasitic capacitance between the common electrode layer 40 and the data line 3, reducing the load on the data line, and the light leakage of the data line 3 at this position will be covered by the black matrix parallel to the gate line 2, and there will be no risk of light leakage.

[0080] In one possible implementation, see Figures 12A-12F As shown, the common electrode 4 extends along the first direction X and is arranged along the second direction Y. The orthographic projection of the common electrode 4 on the substrate 1 and the area between adjacent gate line groups 20 are within the orthographic projection of the substrate 1. The common electrode 4 has connecting portions 42 at both ends of the first hollow 41. The common electrode 4 is electrically connected to the first trace 6 through the first via K1 at the connecting portions 42. In the disclosed embodiment, the common electrode 4 has a connecting portion 42 at at least one end of the first hollow 41. That is, in the second direction Y, the first hollow 41 does not penetrate the common electrode 4. This allows the common electrodes 4 located on both sides of the first hollow 41 in the first direction X to be electrically connected, avoiding the need to connect the common electrodes 4 in the first direction X through other structures, which would increase the manufacturing process of the array substrate and increase the cost of the array substrate.

[0081] In a possible embodiment, the common electrode 4 has connecting portions 42 at both ends of the first hollow 41, which can improve the reliability of the connection between the first trace 6 and the common electrode 4. Figure 12A As shown, the first wiring 6 between two adjacent gate line groups 20 can be connected to the common electrode 4 through two first vias K1. The two first vias K1 can be located on different sides of the first wiring 6 to avoid occupying too large an area of ​​the same pixel electrode 5 when they are set on the same side, thereby affecting the normal display of the pixel electrode 5.

[0082] In one possible implementation, see Figures 12A-12F As shown, the extension length d3 of the first trace 6 is greater than the extension length d4 of the first hollow 41. In this way, the first trace 6 can be electrically connected to the connection portions 42 at both ends of the first hollow 41.

[0083] In one possible implementation, see Figures 12A-12F As shown, the orthographic projection of the first trace 61 on the substrate 1 covers the orthographic projection of the first hollow 41 on the substrate 1, and covers the orthographic projection of the connection portion 42 on the substrate. In this way, the first trace 6 can be electrically connected to the connection portion 42 at the connection portion 42 at both ends of the first hollow 41.

[0084] In one possible implementation, see Figure 12F As shown, the width d1 of the first hollow 41 in the first direction X is greater than the width d2 of the first trace 6 in the first direction X. In this way, the dielectric layer at each position in the overlapping region of the data line 3 and the common electrode layer 40 is a superposition of the organic film layer 92 and the passivation layer 93, thereby minimizing the parasitic capacitance between the data line 3 and the common electrode (first trace 6) covering it. This can reduce the load on the data line, improve the pixel charging rate, and reduce the coupling effect of the voltage polarity jump of the data line 3 on the common electrode, thereby reducing the problem of horizontal crosstalk.

[0085] In one possible implementation, see Figure 12F As shown, the orthographic projection of the first trace 6 on the substrate covers the orthographic projection of a portion of the common electrode 4 on both sides of the first hollow 41 on the substrate 1. In other words, there may be an overlapping area S between the first trace 6 and the common electrode 4 on both sides of the first hollow 41. In this way, the combination of the first trace 6 and the common electrode 4 can completely shield the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3.

[0086] In some pixel designs, the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3 does not need to be completely eliminated. As long as it is reduced to a certain limit, the poor image quality caused by the full-length connection dual gate pixel architecture can be avoided. However, there is a higher requirement for reducing the load on the data line 3. In one possible implementation, see Figure 12G As shown, the orthographic projection of the first trace 6 on the substrate 1 does not overlap with the orthographic projection of the common electrodes 4 on both sides of the first hollow 41 on the substrate 1, that is, in a plane parallel to the substrate 1, the distance between the edges of the common electrodes 4 on both sides of the first hollow 41 and the edges of the data line 3 is increased. In this way, the coupling capacitance between the data line 3 and the common electrode layer 40 can be further reduced, the load of the data line can be reduced, the pixel charging rate can be improved, and the coupling effect of the voltage polarity jump of the data line 3 on the common electrode can be reduced, thereby reducing the problem of horizontal crosstalk.

[0087] In one possible implementation, see Figures 13A-13E As shown, the first wiring 6 is located in the common electrode layer 40 and is integrally connected to the common electrode 4. In the embodiment of the present disclosure, the first wiring 6 is located in the common electrode layer 40 and is integrally connected to the common electrode 4. The common electrode 4 can cover the data line 3, completely shielding the electric field of the data line 3. There is no longer any parasitic capacitance between the upper pixel electrode 5 and the data line 3, and the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3 can be eliminated; the upper pixel electrode layer 50 is not provided with a pattern for shielding the data line 3, and the pixel electrodes 5 of two adjacent sub-pixels can be closer (the minimum distance is based on the process of not short-circuiting, usually the distance is ≥3um), which can increase the aperture ratio of the display panel.

[0088] In one possible implementation, see Figure 13C As shown, the orthographic projection of the outer edge w1 of the pixel electrode 5 on the substrate 1 coincides with the outer edge w2 of the data line 3 on the substrate 1. In this way, the aperture ratio of the display panel can be improved.

[0089] In one possible implementation, see Figures 12A-12F 、 Figures 13A-13E As shown, the array substrate further includes: a plurality of second traces 7, and a plurality of second via groups K20; the second via group K20 includes: two second vias K2; the two second vias K2 of the second via group K20 are located on either side of the gate line group 2 and on different sides of the second trace 7; the common electrodes 4 on both sides of the gate line group 20 are electrically connected to the second trace 7 through the two second vias K2 of the second via group K20. In this way, the common electrodes 4 on both sides of the gate line group 20 can be connected together through the second trace 7.

[0090] In one possible implementation, see Figures 12A-12F 、 Figures 13A-13EAs shown, the second via hole K2 may be located at a region where the gate line group 20 and the data line 3 intersect.

[0091] In one possible implementation, see Figures 12A-12F 、 Figures 13A-13E As shown, the second wiring 7 is made of the same layer and material as the data line 3; the array substrate further includes: an organic insulating layer 92 located between the data line 3 and the common electrode layer 40, and a passivation layer 93 located between the common electrode layer 40 and the pixel electrode layer 50; the pixel electrode layer 40 further includes: an overlapping portion 51; a second via K2 penetrates the passivation layer 93 and the organic insulating layer 92, and exposes a portion of the second wiring 7, as well as a portion of the common electrode 4, and the overlapping portion 51 contacts the common electrode 4 and the second wiring 7 through the second via K2.

[0092] In one possible implementation, see Figures 12A-12F 、 Figures 13A-13E As shown, the second routing 7 may include a second routing main portion 71 and a second routing extension portion 72; wherein, the orthographic projection of the second routing extension portion 72 on the substrate 1 may overlap with the orthographic projection of the overlapping portion 51 on the substrate 1, so as to achieve electrical connection with the common electrode 4 through the second routing extension portion 72.

[0093] In one possible implementation, see Figures 12A-12D 、 Figure 13B As shown, the common electrode 4 has a recessed portion 43 at the location of the second via K2; the orthographic projection of the second via K2 on the substrate 1 partially overlaps with the recessed portion 43 and partially overlaps with the common electrode 4 on the side of the recessed portion 43 away from the gate line group 20. In the disclosed embodiment, the common electrode 4 has a recessed portion 43 at the location of the second via K2, which can facilitate contact between the overlapping portion 51 located in the upper layer and the second wiring 7 in the lower layer, avoiding obstruction by the common electrode 4 located in the middle layer, which would prevent the overlapping portion 51 in the upper layer from contacting the second wiring 7 in the lower layer; furthermore, the second via K2 partially exposes the second wiring 7 and partially exposes the common electrode 4, with half of the portion being used for connecting the second wiring 7 to the overlapping portion 51 and the other half being used for connecting the common electrode 4 to the overlapping portion 51. This helps to reduce the area of ​​the second via and increase the aperture ratio of the display panel.

[0094] In one possible implementation, see Figures 14A-14B As shown, the second trace 7 is located on the side of the common electrode layer 40 facing the substrate 1 and is in direct contact with the common electrode 4. In the disclosed embodiment, the second trace 7 is located on the side of the common electrode layer 40 facing the substrate 1 and is in direct contact with the common electrode 4. When the resolution and refresh rate of the display panel are both high, the uniformity of the common electrode voltage can be improved. Moreover, the second trace 7 and the common electrode 4 do not require a via hole to be connected, and can be in direct contact, which improves connectivity. By eliminating the area of ​​the via hole, the pixel transmittance can also be improved.

[0095] In one possible implementation, see Figure 16 As shown, the common electrode layer 40 may also be disposed on a side of the pixel electrode layer 50 away from the substrate 1 , and the parasitic capacitance Cpd between the data line 3 and the pixel electrode 5 may be reduced by increasing the lateral distance between the pixel electrode 5 and the data line 3 .

[0096] Based on the same utility model concept, the present disclosure also provides a display panel, see Figure 15 As shown, it includes an array substrate as provided in an embodiment of the present disclosure, and also includes a color filter substrate arranged opposite to the array substrate. The color filter substrate may include: a color filter substrate 95, a black matrix 96 located on the side of the color filter substrate 95 facing the array substrate, and a color filter layer located on the side of the black matrix 96 facing the array substrate. The color filter layer may include: a first color resist 971, a second color resist 972, and a third color resist (not shown in the figure). The first color resist 971 can be a red color resist, the second color resist 972 can be a green color resist, and the third color resist can be a blue color resist. Optionally, the orthographic projection of the black matrix 96 on the substrate 1 can cover the orthographic projection of the gate line group 20 on the substrate 1; optionally, the color filter substrate may not be provided with a black matrix or a black matrix with a narrower line width at the position corresponding to the data line 3, that is, the data line 3 can be covered by the first trace 6 to shield the electric field on the data line 3 and shield light leakage.

[0097] Based on the same utility model concept, the embodiments of the present disclosure further provide a display device, including the above-mentioned display panel provided in the embodiments of the present disclosure. The implementation of the display device can refer to the embodiments of the display panel described above, and the repeated parts will not be repeated here. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. The other essential components of the display device should be understood by those of ordinary skill in the art and will not be described here in detail, nor should they be construed as limitations on the present disclosure.

[0098] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0099] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. An array substrate, wherein: include: substrate; multiple transistors; A plurality of gate line groups are located on one side of the substrate, the gate line groups comprising: two gate lines extending along a first direction; Multiple data lines; a common electrode layer, located on a side of the data line facing away from the substrate; the common electrode layer includes a plurality of common electrodes; a pixel electrode layer, located on a side of the common electrode layer facing away from the data line, comprising: a plurality of pixel electrode rows extending along a first direction; the pixel electrode rows comprising a plurality of pixel electrode groups arranged along the first direction; the gate line group being located in an area between adjacent pixel electrode rows, the pixel electrode group being located in an area formed by the intersection of the gate line group and the data line; the pixel electrode group comprising two pixel electrodes, and any pixel electrode in the pixel electrode group being electrically connected to the data line via the transistor across the other pixel electrode; Among them, at least one of the common electrode layer and the pixel electrode layer includes: multiple first traces extending along the second direction; the first traces are electrically connected to the common electrode, and the orthographic projection of the first trace on the substrate covers the orthographic projection of the data line on the substrate.

2. The array substrate according to claim 1, wherein: The first wiring is located in the pixel electrode layer; The common electrode layer has a first hollow; the orthographic projection of the first wiring on the substrate overlaps with the orthographic projection of the first hollow on the substrate.

3. The array substrate according to claim 2, wherein: The first wiring is disconnected at the position of the gate line group.

4. The array substrate according to claim 2 or 3, wherein: The common electrodes extend along the first direction and are arranged along the second direction, and an orthographic projection of the common electrodes on the substrate and an area between adjacent gate line groups are within the orthographic projection of the substrate; The common electrode has a connecting portion at at least one end of the first hollow portion, and the common electrode is electrically connected to the first wiring through a first via hole at the connecting portion.

5. The array substrate according to claim 4, wherein: An extension length of the first trace is greater than an extension length of the first hollow portion.

6. The array substrate according to claim 4, wherein: The orthographic projection of the first trace on the substrate covers the orthographic projection of the first hollow on the substrate, and covers the orthographic projection of the connecting portion on the substrate.

7. The array substrate according to claim 2, wherein: The orthographic projection of the first wiring on the substrate covers a portion of the orthographic projection of the common electrode on both sides of the first hollow on the substrate.

8. The array substrate according to claim 2, wherein: The orthographic projection of the first wiring on the substrate does not overlap with the orthographic projection of the common electrodes on both sides of the first hollow on the substrate.

9. The array substrate according to claim 1, wherein: The first wiring is located in the common electrode layer and is integrally connected to the common electrode.

10. The array substrate according to claim 9, wherein: The orthographic projection of the outer edge of the pixel electrode on the substrate coincides with the outer edge of the data line on the substrate.

11. The array substrate according to claim 3, wherein: The array substrate also includes: multiple second routing lines and multiple second via groups; the second via group includes: two second vias; the two second vias of the second via group are respectively located on both sides of the gate line group and on different sides of the second routing line; the common electrodes on both sides of the gate line group are electrically connected to the second routing line through the two second vias of the second via group.

12. The array substrate according to claim 11, wherein: The second wiring is formed in the same layer and material as the data line; the array substrate further comprises: an organic insulating layer between the data line and the common electrode layer, and a passivation layer between the common electrode layer and the pixel electrode layer; the pixel electrode layer further comprises: an overlapping portion; The second via hole penetrates the passivation layer and the organic insulating layer, and exposes a portion of the second wiring and a portion of the common electrode. The overlapping portion contacts the common electrode and the second wiring through the second via hole.

13. The array substrate according to claim 12, wherein: The common electrode has a recessed portion at the location of the second via hole; the orthographic projection of the second via hole on the substrate partially overlaps with the recessed portion and partially overlaps with the common electrode on a side of the recessed portion away from the gate line group.

14. The array substrate according to claim 11, wherein: The second wiring is located on a side of the common electrode layer facing the substrate and is in direct contact with the common electrode.

15. A display panel, wherein: Comprising the array substrate according to any one of claims 1 to 14.

Images