Mining keyboard test circuit

By designing a mining keyboard test circuit and using analog key circuits, voltage sampling circuits, current sampling circuits and single-chip microcomputers to achieve automatic testing, the problems of low mining keyboard detection efficiency and accuracy in the existing technology are solved, and fast and accurate testing results are achieved.

CN223362269UActive Publication Date: 2025-09-19HUA TIANXIN INTELLIGENT IOT CO LTD
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Patent Information

Application Number
CN202422117404.0
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-08-30
Publication Date
2025-09-19
Estimated Expiration
2034-08-30

AI Technical Summary

Technical Problem

In the prior art, the detection of mining keyboards relies on manual labor, which has low efficiency and accuracy and is prone to false detection and misdetection.

Method used

A mining keyboard test circuit was designed, consisting of a key simulation circuit, a voltage sampling circuit, a current sampling circuit, and a single-chip microcomputer. The circuit automatically receives instructions from the microcontroller, simulates key signals, and collects the output voltage and current of the mining keyboard, enabling automatic testing.

Benefits of technology

Through this test circuit, the mining keyboard can be tested quickly and accurately, which improves the test speed and accuracy and reduces human errors.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a mining keyboard test circuit, comprising a simulation button circuit respectively connected with a mining keyboard and a one-chip microcomputer and used for receiving instructions of the one-chip microcomputer and sending simulation button signals to the mining keyboard; the voltage sampling circuit is respectively connected with the mining keyboard and the single chip microcomputer, and is used for collecting the output voltage of the mining keyboard and sending the output voltage to the single chip microcomputer; the current sampling circuit is respectively connected with the mining keyboard and the single chip microcomputer, and is used for collecting the output current of the mining keyboard and sending the output current to the single chip microcomputer; and the single chip microcomputer is also connected with the mining keyboard and is used for receiving an output signal of the mining keyboard. The mining keyboard can be rapidly and accurately tested, and the testing speed and accuracy of the mining keyboard are improved.
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Description

Technical Field

[0001] The utility model belongs to the technical field of mining keyboards, in particular to a mining keyboard test circuit. Background Art

[0002] A mining keyboard is a keyboard specially used in mines. It can convert input instructions into CAN signals and output them to the control host computer to control the corresponding equipment. However, due to the intrinsic safety requirements of mines, there are restrictions on input current and voltage. Therefore, mining keyboards need to be tested regularly. In the existing technology, testing of mining keyboards is done manually by staff, which is time-consuming and inefficient, and is prone to false detection and misdetection.

[0003] Therefore, how to quickly and accurately test the mining keyboard is a technical problem to be solved by those skilled in the art. Utility Model Content

[0004] The purpose of the utility model is to solve the technical problem that the detection of mining keyboards in the prior art relies on manual labor, which has low efficiency and accuracy. To this end, the utility model provides a mining keyboard test circuit, which includes:

[0005] The analog key circuit is connected to the mining keyboard and the single-chip microcomputer respectively, and is used to receive instructions from the single-chip microcomputer and send analog key signals to the mining keyboard;

[0006] a voltage sampling circuit, connected to the mining keyboard and the single-chip microcomputer, respectively, for collecting the output voltage of the mining keyboard and sending it to the single-chip microcomputer;

[0007] a current sampling circuit, connected to the mining keyboard and the single-chip microcomputer, respectively, for collecting the output current of the mining keyboard and sending it to the single-chip microcomputer;

[0008] The single chip microcomputer is also connected to the mining keyboard and is used to receive output signals from the mining keyboard.

[0009] Furthermore, the analog key circuit includes a group A and a group B analog circuit, the group A analog circuit includes an A1 sub-analog circuit, an A2 sub-analog circuit, an A3 sub-analog circuit, and an A4 sub-analog circuit, and the group B sub-analog circuit includes a B1 sub-analog circuit, a B2 sub-analog circuit, a B3 sub-analog circuit, and a B4 sub-analog circuit, wherein:

[0010] The A1 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U1 is connected to the other end of the resistor R1, one end of the resistor R1 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U1 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U1 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U1 is connected to one end of the diode H1, the other end of the diode H1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the second power supply voltage VCC2;

[0011] The A2 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U3 is connected to the other end of the resistor R5, one end of the resistor R5 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U3 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U3 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U3 is connected to one end of the diode H3, the other end of the diode H3 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the second power supply voltage VCC2;

[0012] The A3 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U5 is connected to the other end of the resistor R9, one end of the resistor R9 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U5 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U5 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U5 is connected to one end of the diode H5, the other end of the diode H5 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the second power supply voltage VCC2;

[0013] The A4 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U7 is connected to the other end of the resistor R13, one end of the resistor R13 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U7 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U7 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U7 is connected to one end of the diode H7, the other end of the diode H7 is connected to one end of the resistor R14, and the other end of the resistor R14 is connected to the second power supply voltage VCC2;

[0014] The B1 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U2 is connected to the other end of the resistor R3, one end of the resistor R3 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U2 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U2 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U2 is connected to one end of the diode H2, the other end of the diode H2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the second power supply voltage VCC2;

[0015] The B2 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U4 is connected to the other end of the resistor R7, one end of the resistor R7 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U4 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U4 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U4 is connected to one end of the diode H4, the other end of the diode H4 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the second power supply voltage VCC2;

[0016] The B3 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U6 is connected to the other end of the resistor R11, one end of the resistor R11 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U6 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U6 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U6 is connected to one end of the diode H6, the other end of the diode H6 is connected to one end of the resistor R12, and the other end of the resistor R12 is connected to the second power supply voltage VCC2;

[0017] The B4 sub-analog circuit is specifically connected to the first port of the isolation optocoupler U8 and the other end of the resistor R15, one end of the resistor R15 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U8 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U8 is connected to the second ground wire GND2, the fourth end of the isolation optocoupler U8 is connected to one end of the diode H8, the other end of the diode H8 is connected to one end of the resistor R16, and the other end of the resistor R16 is connected to the second power supply voltage VCC2.

[0018] Furthermore, the voltage sampling circuit specifically includes:

[0019] The second end of the operational amplifier U3A is respectively connected to the other end of the resistor R17 and one end of the resistor R18, one end of the resistor R17 is connected to the mining keyboard power supply voltage VDD, the other end of the resistor R18 is connected to the first ground line DGND, the first and third ends of the operational amplifier U3A are both connected to one end of the resistor R19, the other end of the resistor R19 is simultaneously connected to one end of the resistor R20 and the second end of the operational amplifier U3B, the third end of the operational amplifier U3B is connected to the first ground line DGND, the first end of the operational amplifier U3B and the other end of the resistor R20 are both connected to one end of the resistor R21, the other end of the resistor R21 is respectively connected to one end of the capacitor C1 and the single-chip microcomputer, and the other end of the capacitor C1 is connected to the first ground line DGND.

[0020] Furthermore, the current sampling circuit specifically includes:

[0021] The second end of the chip V1 is respectively connected to one end of the resistor R22 and the power supply voltage VDD1 after passing through the sampling resistor. The other end of the resistor R22 is respectively connected to the mining keyboard power supply voltage VDD and the third end of the chip V1. The first end of the chip V1 is respectively connected to one end of the resistor R23, one end of the capacitor C2 and the second end of the operational amplifier U4A. The other end of the resistor R23 and the other end of the capacitor C2 are both connected to the first ground line DGND. The first and third ends of the operational amplifier U4A are both connected to one end of the resistor R24. The other end of the resistor R24 ​​is simultaneously connected to one end of the resistor R25 and the second end of the operational amplifier U4B. The third end of the operational amplifier U4B is connected to the first ground line DGND. The first end of the operational amplifier U4B and the other end of the resistor R25 are both connected to one end of the resistor R26. The other end of the resistor R26 is respectively connected to one end of the capacitor C3 and the single-chip microcomputer. The other end of the capacitor C3 is connected to the first ground line DGND.

[0022] Furthermore, all isolation optocouplers are of model PS2801-1.

[0023] Furthermore, the test circuit also includes a power supply circuit for supplying power to the analog key circuit, the voltage sampling circuit, the current sampling circuit and the single chip microcomputer.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] Compared with the existing technology, the present invention provides a mining keyboard test circuit that includes: an analog key circuit, connected to the mining keyboard and a single-chip microcomputer, for receiving instructions from the single-chip microcomputer and sending analog key signals to the mining keyboard; a voltage sampling circuit, connected to the mining keyboard and the single-chip microcomputer, for collecting the output voltage of the mining keyboard and sending it to the single-chip microcomputer; a current sampling circuit, connected to the mining keyboard and the single-chip microcomputer, for collecting the output current of the mining keyboard and sending it to the single-chip microcomputer; the single-chip microcomputer is also connected to the mining keyboard for receiving the output signal of the mining keyboard. This circuit can quickly and accurately test mining keyboards, improving the speed and accuracy of mining keyboard testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of this specification, the following is a brief introduction to the drawings required for use in the embodiments. The drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 The figure shows the overall structure of the mining keyboard test circuit in the embodiment of this specification;

[0028] Figure 2 Shown is a schematic diagram of the structure of each sub-analog circuit in the embodiments of this specification;

[0029] Figure 3 The figure shows a schematic diagram of the structure of the voltage sampling circuit in the embodiment of this specification;

[0030] Figure 4 FIG. 1 is a schematic diagram showing the structure of a current sampling circuit in an embodiment of this specification. DETAILED DESCRIPTION

[0031] To help those skilled in the art better understand the technical solutions in this specification, the following will provide a clear and complete description of the technical solutions in the embodiments of this specification, in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without creative work should fall within the scope of protection of this specification.

[0032] like Figure 1 The diagram shows the overall structure of the mining keyboard test circuit provided in the embodiments of this specification. Although this specification provides the structures shown in the following embodiments or figures, the structures described may include more or fewer structures by combining parts based on routine or no creative effort. These structures are not limited to the structures shown in the embodiments or figures of this specification. When the structures described are used in actual devices or end products, they can be executed sequentially or in parallel according to the embodiments or module structures.

[0033] The mining keyboard test circuit provided in the embodiments of this specification includes:

[0034] The analog key circuit is connected to the mining keyboard and the single-chip microcomputer respectively, and is used to receive instructions from the single-chip microcomputer and send analog key signals to the mining keyboard;

[0035] a voltage sampling circuit, connected to the mining keyboard and the single-chip microcomputer, respectively, for collecting the output voltage of the mining keyboard and sending it to the single-chip microcomputer;

[0036] a current sampling circuit, connected to the mining keyboard and the single-chip microcomputer, respectively, for collecting the output current of the mining keyboard and sending it to the single-chip microcomputer;

[0037] The single chip microcomputer is also connected to the mining keyboard and is used to receive output signals from the mining keyboard.

[0038] Specifically, the single-chip microcomputer receives the test instruction sent by the host computer and sends the analog key control instruction to the analog key circuit. After receiving the instruction, the analog key circuit sends the key instruction to the mining keyboard to be tested via a wired method. After receiving the key instruction, the mining keyboard will decode the key instruction and send the output signal to the single-chip microcomputer via CAN communication. At the same time, the voltage sampling circuit and the current sampling circuit respectively collect the output voltage and output current of the mining keyboard. The single-chip microcomputer compares the output signal with the sent analog key control instruction. If they are consistent and the output voltage and output current are normal, the function of the mining keyboard is normal. The single-chip microcomputer can also upload the output signal, output voltage and output current to the host computer for comparison. If a channel does not correspond, the channel fault of the keyboard module to be tested is reported to facilitate maintenance. After all channels are tested normally after the backtest is completed, it is reported that the function of the keyboard module to be tested is normal.

[0039] In addition, the test circuit also includes a power supply circuit for powering the analog key circuit, voltage sampling circuit, current sampling circuit and single-chip microcomputer. The single-chip microcomputer and the mining keyboard can be connected by CAN communication, serial bus, or other wired or wireless methods. The single-chip microcomputer and the host computer can be connected by CAN communication, serial bus, or other wired or wireless methods.

[0040] In the embodiments of this application, Figure 2 The above is a schematic diagram of the structure of each sub-analog circuit. The analog key circuit includes Group A and Group B analog circuits. The Group A analog circuit includes Sub-A1 analog circuit, Sub-A2 analog circuit, Sub-A3 analog circuit and Sub-A4 analog circuit. The Group B sub-analog circuit includes Sub-A1 analog circuit, Sub-A2 analog circuit, Sub-A3 analog circuit and Sub-A4 analog circuit. The sub-analog circuit includes Sub-A1 analog circuit, Sub-A2 analog circuit, Sub-A3 analog circuit and Sub-A4 analog circuit.

[0041] The A1 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U1 is connected to the other end of the resistor R1, one end of the resistor R1 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U1 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U1 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U1 is connected to one end of the diode H1, the other end of the diode H1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the second power supply voltage VCC2;

[0042] The A2 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U3 is connected to the other end of the resistor R5, one end of the resistor R5 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U3 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U3 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U3 is connected to one end of the diode H3, the other end of the diode H3 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the second power supply voltage VCC2;

[0043] The A3 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U5 is connected to the other end of the resistor R9, one end of the resistor R9 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U5 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U5 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U5 is connected to one end of the diode H5, the other end of the diode H5 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the second power supply voltage VCC2;

[0044] The A4 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U7 is connected to the other end of the resistor R13, one end of the resistor R13 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U7 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U7 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U7 is connected to one end of the diode H7, the other end of the diode H7 is connected to one end of the resistor R14, and the other end of the resistor R14 is connected to the second power supply voltage VCC2;

[0045] The B1 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U2 is connected to the other end of the resistor R3, one end of the resistor R3 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U2 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U2 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U2 is connected to one end of the diode H2, the other end of the diode H2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the second power supply voltage VCC2;

[0046] The B2 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U4 is connected to the other end of the resistor R7, one end of the resistor R7 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U4 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U4 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U4 is connected to one end of the diode H4, the other end of the diode H4 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the second power supply voltage VCC2;

[0047] The B3 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U6 is connected to the other end of the resistor R11, one end of the resistor R11 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U6 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U6 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U6 is connected to one end of the diode H6, the other end of the diode H6 is connected to one end of the resistor R12, and the other end of the resistor R12 is connected to the second power supply voltage VCC2;

[0048] The B4 sub-analog circuit is specifically connected to the first port of the isolation optocoupler U8 and the other end of the resistor R15, one end of the resistor R15 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U8 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U8 is connected to the second ground wire GND2, the fourth end of the isolation optocoupler U8 is connected to one end of the diode H8, the other end of the diode H8 is connected to one end of the resistor R16, and the other end of the resistor R16 is connected to the second power supply voltage VCC2.

[0049] Specifically, the models of all isolation optocouplers are PS2801-1, and the structure of each sub-analog circuit is the same. The A and B signals default to high 1. When A1 and B1 are low at the same time, the analog key 1 state is simulated. Similarly, there are 16 key combinations in total. In addition, the first power supply voltage VCC1 is the power supply voltage of the microcontroller, which is an internal power supply voltage of 3.3V. The second power supply voltage VCC2 is an external signal analog voltage of 24V. The second ground wire GND2 refers to the ground wire of the second power supply voltage VCC2, which provides a signal loop and is electrically isolated from the first ground wire DGND of the microcontroller through an isolation optocoupler to improve anti-interference ability and prevent high voltage from directly entering the microcontroller.

[0050] Taking the A1 sub-analog circuit as an example, the isolating optocoupler isolates the control signal to prevent crosstalk to the keyboard module under test. Resistors R1 / R2 act as current-limiting resistors for the power supply voltage on both sides of the optocoupler, limiting the current across the optocoupler to prevent damage from overcurrent or short circuits. Resistors in other locations perform the same function. Each output channel of the optocoupler is connected in series with an LED. When a simulated key command is issued, the optocoupler of the corresponding channel turns on, and the LED illuminates accordingly, indicating that the current key command has been issued.

[0051] In the embodiments of this application, Figure 3 FIG. 1 is a schematic diagram of the structure of a voltage sampling circuit, which specifically includes:

[0052] The second end of the operational amplifier U3A is respectively connected to the other end of the resistor R17 and one end of the resistor R18, one end of the resistor R17 is connected to the mining keyboard power supply voltage VDD, the other end of the resistor R18 is connected to the first ground line DGND, the first and third ends of the operational amplifier U3A are both connected to one end of the resistor R19, the other end of the resistor R19 is simultaneously connected to one end of the resistor R20 and the second end of the operational amplifier U3B, the third end of the operational amplifier U3B is connected to the first ground line DGND, the first end of the operational amplifier U3B and the other end of the resistor R20 are both connected to one end of the resistor R21, the other end of the resistor R21 is respectively connected to one end of the capacitor C1 and the single-chip microcomputer, and the other end of the capacitor C1 is connected to the first ground line DGND.

[0053] The voltage sampling circuit uses a resistor divider method. R17 and R18 form a voltage divider circuit, which collects the voltage at R18 and reduces the VDD voltage to a range that can be sensed by the microcontroller. U3A and U3B are operational amplifiers, with U3A forming a reverse follower circuit. U3B, R19, and R20 together form a reverse amplifier circuit, facilitating gain adjustment of the collected signal. Resistor R21 is a current-limiting resistor, preventing high-voltage interference from damaging the microcontroller interface. C1 is a filter capacitor, which filters the collected signal and absorbs high-frequency interference.

[0054] In the embodiments of this application, Figure 4 FIG. 1 is a schematic diagram of the structure of a current sampling circuit, which specifically includes:

[0055] The second end of the chip V1 is respectively connected to one end of the resistor R22 and the power supply voltage VDD1 after passing through the sampling resistor. The other end of the resistor R22 is respectively connected to the mining keyboard power supply voltage VDD and the third end of the chip V1. The first end of the chip V1 is respectively connected to one end of the resistor R23, one end of the capacitor C2 and the second end of the operational amplifier U4A. The other end of the resistor R23 and the other end of the capacitor C2 are both connected to the first ground line DGND. The first and third ends of the operational amplifier U4A are both connected to one end of the resistor R24. The other end of the resistor R24 ​​is simultaneously connected to one end of the resistor R25 and the second end of the operational amplifier U4B. The third end of the operational amplifier U4B is connected to the first ground line DGND. The first end of the operational amplifier U4B and the other end of the resistor R25 are both connected to one end of the resistor R26. The other end of the resistor R26 is respectively connected to one end of the capacitor C3 and the single-chip microcomputer. The other end of the capacitor C3 is connected to the first ground line DGND.

[0056] The current sampling circuit uses a current acquisition chip, V1. R22 is a sampling resistor in the milliohm range, which has a negligible impact on the VDD voltage. V1, the current acquisition chip, converts the current flowing through R22 into a collectible current output. Resistor R23 is a sampling resistor responsible for converting the current signal output by V1 into a voltage signal to facilitate subsequent op amp operation. Capacitor C2 is a filter capacitor, absorbing high-frequency interference while maintaining the stability of the converted voltage signal. The operational amplifier circuit composed of U4A and U4B performs the same function as the operational amplifier circuit composed of U3A and U3B in the voltage sampling circuit.

[0057] It should be understood that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intervening element at the same time; when an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intervening element at the same time. In addition, the "connection" used here may include wireless connection; the wording "and / or" used includes any unit and all combinations of one or more associated listed items.

[0058] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0059] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0060] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0061] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0062] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0063] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

[0064] The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A mining keyboard test circuit, characterized in that: The circuit comprises: The analog key circuit is connected to the mining keyboard and the single-chip microcomputer respectively, and is used to receive instructions from the single-chip microcomputer and send analog key signals to the mining keyboard; a voltage sampling circuit, connected to the mining keyboard and the single-chip microcomputer, respectively, for collecting the output voltage of the mining keyboard and sending it to the single-chip microcomputer; a current sampling circuit, connected to the mining keyboard and the single-chip microcomputer, respectively, for collecting the output current of the mining keyboard and sending it to the single-chip microcomputer; The single chip microcomputer is also connected to the mining keyboard and is used to receive output signals from the mining keyboard.

2. The mining keyboard test circuit according to claim 1, characterized in that: The analog key circuit includes a group A and a group B analog circuit, wherein the group A analog circuit includes an A1 sub-analog circuit, an A2 sub-analog circuit, an A3 sub-analog circuit, and an A4 sub-analog circuit, and the group B sub-analog circuit includes a B1 sub-analog circuit, a B2 sub-analog circuit, a B3 sub-analog circuit, and a B4 sub-analog circuit, wherein: The A1 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U1 is connected to the other end of the resistor R1, one end of the resistor R1 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U1 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U1 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U1 is connected to one end of the diode H1, the other end of the diode H1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the second power supply voltage VCC2; The A2 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U3 is connected to the other end of the resistor R5, one end of the resistor R5 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U3 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U3 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U3 is connected to one end of the diode H3, the other end of the diode H3 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the second power supply voltage VCC2; The A3 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U5 is connected to the other end of the resistor R9, one end of the resistor R9 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U5 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U5 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U5 is connected to one end of the diode H5, the other end of the diode H5 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the second power supply voltage VCC2; The A4 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U7 is connected to the other end of the resistor R13, one end of the resistor R13 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U7 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U7 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U7 is connected to one end of the diode H7, the other end of the diode H7 is connected to one end of the resistor R14, and the other end of the resistor R14 is connected to the second power supply voltage VCC2; The B1 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U2 is connected to the other end of the resistor R3, one end of the resistor R3 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U2 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U2 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U2 is connected to one end of the diode H2, the other end of the diode H2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the second power supply voltage VCC2; The B2 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U4 is connected to the other end of the resistor R7, one end of the resistor R7 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U4 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U4 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U4 is connected to one end of the diode H4, the other end of the diode H4 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the second power supply voltage VCC2; The B3 sub-analog circuit is specifically configured such that the first port of the isolation optocoupler U6 is connected to the other end of the resistor R11, one end of the resistor R11 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U6 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U6 is connected to the second ground line GND2, the fourth end of the isolation optocoupler U6 is connected to one end of the diode H6, the other end of the diode H6 is connected to one end of the resistor R12, and the other end of the resistor R12 is connected to the second power supply voltage VCC2; The B4 sub-analog circuit is specifically connected to the first port of the isolation optocoupler U8 and the other end of the resistor R15, one end of the resistor R15 is connected to the first power supply voltage VCC1, the second port of the isolation optocoupler U8 is connected to the single-chip microcomputer, the third end of the isolation optocoupler U8 is connected to the second ground wire GND2, the fourth end of the isolation optocoupler U8 is connected to one end of the diode H8, the other end of the diode H8 is connected to one end of the resistor R16, and the other end of the resistor R16 is connected to the second power supply voltage VCC2.

3. The mining keyboard test circuit according to claim 1, characterized in that: The voltage sampling circuit specifically includes: The second end of the operational amplifier U3A is respectively connected to the other end of the resistor R17 and one end of the resistor R18, one end of the resistor R17 is connected to the mining keyboard power supply voltage VDD, the other end of the resistor R18 is connected to the first ground line DGND, the first and third ends of the operational amplifier U3A are both connected to one end of the resistor R19, the other end of the resistor R19 is simultaneously connected to one end of the resistor R20 and the second end of the operational amplifier U3B, the third end of the operational amplifier U3B is connected to the first ground line DGND, the first end of the operational amplifier U3B and the other end of the resistor R20 are both connected to one end of the resistor R21, the other end of the resistor R21 is respectively connected to one end of the capacitor C1 and the single-chip microcomputer, and the other end of the capacitor C1 is connected to the first ground line DGND.

4. The mining keyboard test circuit according to claim 1, characterized in that: The current sampling circuit specifically includes: The second end of the chip V1 is respectively connected to one end of the resistor R22 and the power supply voltage VDD1 after passing through the sampling resistor. The other end of the resistor R22 is respectively connected to the mining keyboard power supply voltage VDD and the third end of the chip V1. The first end of the chip V1 is respectively connected to one end of the resistor R23, one end of the capacitor C2 and the second end of the operational amplifier U4A. The other end of the resistor R23 and the other end of the capacitor C2 are both connected to the first ground line DGND. The first and third ends of the operational amplifier U4A are both connected to one end of the resistor R24. The other end of the resistor R24 ​​is simultaneously connected to one end of the resistor R25 and the second end of the operational amplifier U4B. The third end of the operational amplifier U4B is connected to the first ground line DGND. The first end of the operational amplifier U4B and the other end of the resistor R25 are both connected to one end of the resistor R26. The other end of the resistor R26 is respectively connected to one end of the capacitor C3 and the single-chip microcomputer. The other end of the capacitor C3 is connected to the first ground line DGND.

5. The mining keyboard test circuit according to claim 2, characterized in that: All isolation optocouplers are model PS2801-1.

6. The mining keyboard test circuit according to claim 1, characterized in that: The test circuit also includes a power supply circuit for supplying power to the analog key circuit, the voltage sampling circuit, the current sampling circuit and the single chip microcomputer.