Driving circuit suitable for DO output and PWM output

Abstract

The utility model discloses a drive circuit suitable for DO output and PWM output, the drive circuit is formed by sequentially connecting a DO CPU input interface, a switch circuit, an amplification circuit, a push-pull circuit and a DO output interface, the DO CPU input interface of the drive circuit is connected with an MCU module, the DO output interface of the drive circuit is connected with a load end, high and low levels of the DO output are controlled through the MCU module, and the push-pull circuit is connected with the load end. The push-pull circuit is formed by combining an NPN triode and a PNP triode. According to the utility model, the previous output of a PNP triode is changed into the push-pull circuit output of the combination of the NPN triode and the PNP triode, and the MCU module is used for controlling the high and low levels output by the DO, so that the high level of the DO can be independently output, and the PWM waveform can also be output when the load end is provided with a pull-up resistor.

Description

Technical Field

[0001] The utility model relates to the technical field of electric vehicle battery management systems, in particular to a driving circuit suitable for DO output and PWM output. Background Art

[0002] Since BMS products are currently used in air-cooled energy storage projects, PWM output is required to adjust the fan speed. However, the current DO output circuit has a disadvantage. Since it only uses a PNP transistor output, when there is a pull-up resistor at the load end, there is a problem that the voltage level cannot be pulled low when the DO outputs the PWM waveform. Utility Model Content

[0003] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a driving circuit suitable for DO output and PWM output.

[0004] The technical solution of the utility model is as follows:

[0005] A drive circuit suitable for both DO and PWM outputs is disclosed. The drive circuit comprises a DO CPU input interface, a switch circuit, an amplifier circuit, a push-pull circuit, and a DO output interface, connected in sequence. The DO CPU input interface of the drive circuit is connected to an MCU module, and the DO output interface of the drive circuit is connected to a load end. The high and low levels of the DO output are controlled by the MCU module. The push-pull circuit is composed of an NPN transistor and a PNP transistor. In addition to being able to output a DO high level independently, it can also output a PWM waveform when a pull-up resistor is provided at the load end.

[0006] Furthermore, the switching circuit includes a current-limiting resistor R4, a resistor R5, and a MOS tube. The DO CPU input interface is connected to the G pole of the MOS tube through the current-limiting resistor R4, the S pole of the MOS tube is connected to the digital ground, the resistor R5 is connected between the G pole and the S pole of the MOS tube, and the D pole of the MOS tube is connected to the amplifier circuit.

[0007] Furthermore, the amplification circuit includes a resistor R1, a resistor R2 and a first PNP transistor, the D pole of the MOS transistor is connected to the B pole of the first PNP transistor through the resistor R2, the resistor R1 is connected between the B pole and the E pole of the first PNP transistor, and the C pole of the first PNP transistor is connected to the push-pull circuit.

[0008] Furthermore, the push-pull circuit includes a resistor R3, a resistor R6, an NPN transistor and a second PNP transistor, the C pole of the first PNP transistor is connected to the B pole of the NPN transistor through the resistor R3, the C pole of the NPN transistor is connected to the E pole of the first PNP transistor, the E pole of the NPN transistor is connected to the E pole of the second PNP transistor, the DO output interface is connected between the E pole of the NPN transistor and the E pole of the second PNP transistor, the B pole of the second PNP transistor is connected to the B pole of the first PNP transistor, the C pole of the second PNP transistor is connected to the digital ground, and the resistor R6 is connected between the B pole and the C pole of the second PNP transistor.

[0009] Compared with the prior art, the beneficial effect of the present invention is that: the present invention changes the previous PNP transistor output to a push-pull circuit output composed of an NPN transistor and a PNP transistor, and controls the high and low levels of the DO output through the MCU module. It can output a DO high level alone, and can also output a PWM waveform when there is a pull-up resistor at the load end. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0011] Figure 1 This is a circuit diagram of a driving circuit suitable for DO output and PWM output provided by the utility model;

[0012] Figure 2 This is a connection diagram of a drive circuit suitable for DO output and PWM output provided by the utility model. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0014] In order to illustrate the technical solution of the present invention, specific embodiments are provided below.

[0015] Example

[0016] See also Figures 1-2This embodiment provides a drive circuit suitable for both DO and PWM output. The drive circuit is composed of a DO CPU input interface, a switching circuit, an amplifier circuit, a push-pull circuit, and a DO output interface, which are connected in sequence. The DO CPU input interface of the drive circuit is connected to the MCU module, and the DO output interface of the drive circuit is connected to the load end. The high and low levels of the DO output are controlled by the MCU module. The push-pull circuit is composed of an NPN transistor and a PNP transistor. In addition to being able to output a DO high level independently, it can also output a PWM waveform when a pull-up resistor is installed at the load end.

[0017] The switching circuit includes a current-limiting resistor R4, a resistor R5, and a MOS transistor Q3. The DO CPU input interface is connected to the G pole of the MOS transistor Q3 through the current-limiting resistor R4. The S pole of the MOS transistor Q3 is connected to the digital ground. The resistor R5 is connected between the G pole and the S pole of the MOS transistor Q3. The D pole of the MOS transistor Q3 is connected to the amplifier circuit.

[0018] Among them, the amplification circuit includes resistors R1, R2 and a first PNP transistor Q1. The D pole of the MOS tube is connected to the B pole of the first PNP transistor Q1 through the resistor R2. The resistor R1 is connected between the B pole and the E pole of the first PNP transistor Q1. The C pole of the first PNP transistor Q1 is connected to the push-pull circuit.

[0019] Wherein, the push-pull circuit includes a resistor R3, a resistor R6, an NPN transistor Q2 and a second PNP transistor Q4, the C pole of the first PNP transistor Q1 is connected to the B pole of the NPN transistor Q2 through the resistor R3, the C pole of the NPN transistor Q2 is connected to the E pole of the first PNP transistor Q1, the E pole of the NPN transistor Q2 is connected to the E pole of the second PNP transistor Q4, the DO output interface is connected between the E pole of the NPN transistor Q2 and the E pole of the second PNP transistor Q4, the B pole of the second PNP transistor Q4 is connected to the B pole of the first PNP transistor Q1, the C pole of the second PNP transistor Q4 is connected to the digital ground, and the resistor R6 is connected between the B pole and the C pole of the second PNP transistor Q4.

[0020] The circuit principle is explained as follows: When the MCU module outputs a PWM waveform, it first controls the on / off of the MOS tube Q3 through the current-limiting resistor R4. The MOS tube Q3 controls the on / off of the first PNP transistor Q1 through the resistor R2. The first PNP transistor Q1 further controls the NPN transistor Q2 and the second PNP transistor Q4 through the resistor R3 to jointly control the load end. This can not only output a DO high level independently, but also output a PWM waveform.

[0021] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A driving circuit suitable for DO output and PWM output, characterized by: The drive circuit is composed of a DO CPU input interface, a switching circuit, an amplifier circuit, a push-pull circuit, and a DO output interface, which are connected in sequence. The DO CPU input interface of the drive circuit is connected to the MCU module, and the DO output interface of the drive circuit is connected to the load end. The high and low levels of the DO output are controlled by the MCU module. The push-pull circuit is composed of an NPN transistor and a PNP transistor. In addition to being able to output a DO high level independently, it can also output a PWM waveform when there is a pull-up resistor at the load end.

2. The driving circuit suitable for DO output and PWM output according to claim 1, characterized in that: The switching circuit includes a current-limiting resistor R4, a resistor R5, and a MOS transistor. The DO CPU input interface is connected to the G pole of the MOS transistor through the current-limiting resistor R4. The S pole of the MOS transistor is connected to the digital ground. The resistor R5 is connected between the G pole and the S pole of the MOS transistor. The D pole of the MOS transistor is connected to the amplifier circuit.

3. The driving circuit suitable for DO output and PWM output according to claim 2, characterized in that: The amplifier circuit includes a resistor R1, a resistor R2 and a first PNP transistor. The D pole of the MOS transistor is connected to the B pole of the first PNP transistor through the resistor R2. The resistor R1 is connected between the B pole and the E pole of the first PNP transistor. The C pole of the first PNP transistor is connected to the push-pull circuit.

4. The driving circuit suitable for DO output and PWM output according to claim 3, characterized in that: The push-pull circuit includes a resistor R3, a resistor R6, an NPN transistor and a second PNP transistor. The C pole of the first PNP transistor is connected to the B pole of the NPN transistor through the resistor R3, the C pole of the NPN transistor is connected to the E pole of the first PNP transistor, the E pole of the NPN transistor is connected to the E pole of the second PNP transistor, the DO output interface is connected between the E pole of the NPN transistor and the E pole of the second PNP transistor, the B pole of the second PNP transistor is connected to the B pole of the first PNP transistor, the C pole of the second PNP transistor is connected to the digital ground, and the resistor R6 is connected between the B pole and the C pole of the second PNP transistor.

Images