Chip testing device

Abstract

The utility model provides a chip testing device. The chip testing device comprises a testing probe; wherein the metal bump of the to-be-detected chip comprises a support column arranged on a chip protection layer and a solder cap positioned at the end part of the support column; the test probe comprises a memory metal piece; each test probe is provided with an opening end, the opening ends of the test probes are in contact conduction with the supporting columns when meeting a preset condition, so that the to-be-detected chip and the test probes perform signal transmission through the supporting columns, and the arrangement positions of the test probes correspond to the distribution of the metal bumps one by one. According to the utility model, the related test of the chip can be completed under the condition that the solder cap is not damaged.

Description

Technical Field

[0001] The utility model relates to the technical field of chip detection, and more specifically, to a chip testing device. Background Art

[0002] In the field of semiconductor chip stacking technology, performance testing is required before chips are formed or shipped, enabling quality inspection, grading, and defective product screening. Currently, various chip stacking methods exist, such as HBM, Wide-IO, and HMC. Testing these chips requires external probes to contact the metal bumps on the chip to transmit test signals and test results.

[0003] However, since the metal bumps on the chip are small and fragile, using existing probes to directly contact the metal bumps will damage the solder ends of the metal bumps, thereby affecting the subsequent bonding process and chip performance, and affecting product yield.

[0004] Therefore, there is an urgent need for a chip testing solution that can prevent the solder ends of the metal bumps from being damaged and affecting the chip performance while ensuring that the chip is connected to the test signal. Utility Model Content

[0005] In view of the above problems, the purpose of the present invention is to provide a chip testing device to solve the problem that the existing chip testing scheme may cause damage to the solder end of the chip, thereby affecting the chip performance.

[0006] The chip testing device provided by the present invention includes: a test probe; wherein the metal bumps of the chip to be tested include support columns arranged on the chip protection layer and solder caps located at the ends of the support columns; the test probe includes a memory metal part; the test probe has an open end, and the open end of the test probe contacts and conducts with the support column when a preset condition is met, so that the chip to be tested and the test probe transmit signals through the support column; the setting position of the test probe corresponds one-to-one to the distribution of the metal bumps.

[0007] In addition, an optional technical solution is to further include a probe holder and a driving device for driving the probe holder or the chip to be tested to move; wherein, the test probe is arranged on the probe holder; the test probe has a deformable internal cavity structure; within a first preset temperature range, the open end of the test probe is opened, and the test probe is moved to the outside of the support column by the driving device; within a second preset temperature range, the open end of the test probe retracts and clamps the support column, and the solder cap is avoided in the internal cavity of the test probe; the preset condition is the second preset temperature range.

[0008] In addition, an optional technical solution is that the first preset temperature ranges from 0 to 70°C; and the second preset temperature ranges from greater than 70°C.

[0009] In addition, an optional technical solution is that the cross section of the internal cavity is a circular structure; and the difference between the cross-sectional dimensions of the internal cavity and the solder cap is in the range of 0 to 50 μm.

[0010] In addition, an optional technical solution is that the test probe further includes a base portion connected to the probe holder; wherein an insulating protective layer is provided on the outer side of the base portion and surrounds the test probe.

[0011] In addition, an optional technical solution is that the open end is connected to the base portion via an inclined side arm; within the first preset temperature range, the size of the open end is larger than the size of the solder cap.

[0012] In addition, an optional technical solution is that the cross section of the base portion is rectangular or square.

[0013] In addition, an optional technical solution is to set a first positioning mechanism on the chip protection layer and a second positioning mechanism on the test probe; wherein the first positioning mechanism and the second positioning mechanism are used to cooperate in positioning the test probe and the metal bump.

[0014] In addition, an optional technical solution is that the test probe is connected to an external test system via a PCB board, and the chip to be tested is tested via the test system.

[0015] Using the above-mentioned chip testing device, the test probe has an open end and adopts a shape-changeable memory metal material, so that the open end of the test probe contacts and conducts with the support column when the preset conditions are met, and the conduction between the test probe and the metal bump is achieved through the support column, thereby avoiding direct contact between the test probe and the solder cap, ensuring the integrity of the solder cap's appearance, and avoiding the impact of subsequent processes and performance due to damage to the solder cap. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more clear and easy to understand. In the accompanying drawings:

[0017] Figure 1 This is a schematic structural diagram of a chip testing device according to an embodiment of the present invention in a first state;

[0018] Figure 2This is a schematic structural diagram of a chip testing device according to an embodiment of the present invention in a second state;

[0019] Figure 3 It is a bottom view of the chip testing device according to an embodiment of the present invention.

[0020] The reference numerals include: test probe 1 , base 11 , inclined side arm 12 , open end 13 , solder cap 21 , support column 22 , and chip protection layer 3 .

[0021] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0022] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0023] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present invention.

[0024] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present utility model refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that the term "and / or" used herein includes any and all combinations of one or more associated listed items.

[0025] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the field to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted in an idealized or overly formal sense unless defined as such herein.

[0026] To describe the chip testing device of the present invention in detail, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figures 1 to 3 The overall or partial schematic structures of the chip testing device according to the embodiment of the present utility model are shown from different angles.

[0028] like Figures 1 to 3 As shown together, the chip testing device of an embodiment of the present invention includes a test probe 1; wherein, the metal bumps of the chip to be tested include a support column 22 arranged on the chip protection layer 3 and a solder cap 21 located at the end of the support column 22. Usually, the material of the support column 22 is slightly harder than that of the solder cap 21. For example, the support column 22 can be made of copper, which is less susceptible to damage than the solder cap 21. In order to avoid direct contact between the traditional test probe 1 and the solder cap 21, the test probe 1 in the embodiment of the present invention has an open end 13 and may also have a deformable cavity structure (internal cavity).

[0029] Among them, the test probe 1 may include a memory metal part, or a memory metal and its alloy part. The ratio of the alloy and the memory metal can be flexibly set according to the deformation requirements of the test probe. It can be seen that according to the characteristics of the memory metal, the open end 13 of the test probe 1 can be in contact and connected with the support column 22 when the preset conditions are met, so that the chip to be tested and the test probe 1 can realize signal transmission through the support column 22. Among them, the setting position of the test probe 1 corresponds one by one to the distribution of the metal bumps, and the transmission of the test signal is realized through the support column 22 part to ensure the integrity of the solder cap 21 at its end.

[0030] Specifically, the chip testing device may also include a probe holder (not shown in the figure) for fixing the test probe 1, and a driving device (not shown in the figure) for driving the probe holder or the chip to be tested to move; wherein, the test probe 1 is arranged on the probe holder, and within the first preset temperature range, the open end of the test probe 1 is opened. At this time, the test probe 1 is moved to the outside of the support column 22 by the driving device. In this process, the chip to be tested can be driven to move to the test probe 1 by the driving device, and the test probe 1 can also be driven to move to the chip to be tested.

[0031] In addition, the above-mentioned preset conditions can be set as temperature conditions, so that the memory metal is in different shapes at different temperatures, thereby completing the connection or disconnection between the test probe 1 and the metal bump; wherein, within the first preset temperature range, the open end 13 of the test probe 1 is opened, and at this time the test probe 1 can be driven by the driving device to move to the outside of the support column 22, so that the entire metal bump is located in the internal cavity of the test probe 1; the external ambient temperature is changed so that within the second preset temperature range, the open end 13 of the test probe 1 retracts and clamps the support column 22, and the solder cap 21 at this time is avoided in the internal cavity of the test probe 1, thereby effectively protecting the solder cap 21 structure when the metal bump is in contact and conductive with the test probe 1. Therefore, the above-mentioned preset conditions are met, that is, the second preset temperature range is met.

[0032] Among them, the temperature range and shape types of memory metals can be diversified through material design and processing technology. Among them, the types of memory metal materials may include 1. Low temperature range materials: able to work in a temperature range as low as -100°C. For example, copper-based alloys (such as Cu-Zn-Al) can exhibit good shape memory effects in low temperature environments; 2. Normal temperature range materials: For example, nickel-titanium alloys (Nitinol) usually exhibit the best shape memory effect between -50°C and 100°C. 3. High temperature range: Nickel-titanium alloys with the addition of hafnium (Hf) or aluminum (Al) can increase the phase transition temperature to 200°C or even higher. For example, the phase transition temperature of Ni-Ti-Hf alloy can reach 200°C to 400°C. 4. Ultra-high temperature range: Iron-based alloys (such as Fe-Mn-Si) also exhibit shape memory effects in the temperature range of 200°C to 400°C. Such materials are suitable for extreme high temperature environments.

[0033] In a specific embodiment of the present invention, the memory metal adopts a metal material within the normal temperature range (for example, nickel-titanium alloy). At this time, the first preset temperature can be set to normal temperature, ranging from 0 to 70°C; the range of the second preset temperature is greater than 70°C, and the first preset temperature can also be preferably set to normal temperature, for example, 0 to 40°C, which can ensure that the open end 13 of the test probe 1 is in an open state at normal temperature, and the size of the open end 13 after opening is larger than the maximum size of the metal bump, so that the metal bump can penetrate into the internal cavity of the test probe 1. During the test process, the test probe 1 is temperature-controlled and heated or its ambient temperature is changed so that the ambient temperature reaches the second preset temperature range required for the deformation of the test probe 1. At this time, the open end 13 of the test probe 1 shrinks inward and deforms until it fits with the support column 22.

[0034] Since the solder cap 21 on the chip is usually a spherical structure, the support column 22 below it is a cylindrical structure, which is adapted to the outer shape of the metal bump. In order to achieve that the test probe 1 can effectively contact the support column 22 when deformed, the cross-section of the internal cavity of the test probe 1 (parallel to the direction of the chip protective layer 3) can be set to a circular structure, and ensure that the space of the internal cavity has sufficient margin to accommodate the solder cap 21. For example, the difference between the cross-sectional dimensions of the internal cavity and the solder cap 21 ranges from 0 to 50um, and can preferably be set to 0 to 27um. At this time, the solder cap 21 can be effectively avoided from colliding with the test probe 1, ensuring that the open end 13 of the test probe 1 can be safely avoided in the internal cavity before and after the inward deformation, thereby ensuring the integrity of the solder cap 21.

[0035] In the chip testing device of an embodiment of the present invention, the test probe 1 is a hollow structure having an open end 13, an internal cavity connected to the open end 13, and a base 11 connected to the probe bracket. Furthermore, the open end 13 and the base 11 are connected by an inclined side arm 12, so that when the open end 13 is connected to the support column 22, the solder cap 21 is avoided; within the first preset temperature range, the size of the open end 13 is larger than the size D of the solder cap 21, or further smaller than the size E of the internal cavity. At this time, when the test probe 1 is deformed due to the influence of temperature, since the base 11 is a solid structure, its deformation has little effect on the size. At the same time, under the action of the inclined side arm 12, the deformation of the open end 13 is the largest, thereby achieving the deformation effect of opening outward or contracting inward.

[0036] It should be noted that to prevent the test probe 1 from shrinking or expanding as a whole, which could cause the internal cavity to collide with the solder cap 21, the open end 13 and / or the inclined side arm 12 of the test probe 1 can be made of a memory metal material, while the base 11 and other parts can be made of conventional probe materials to ensure that the open end 13 is effectively opened or clamped. The cross-section of the base 11 can be set to a rectangular or square shape to facilitate its fixation on the probe holder and reduce interference with test probes 1 in other positions.

[0037] In addition, since there will be certain temperature changes during the process of testing the chip through the test probe 1, in order to avoid mutual interference between adjacent test probes 1 or the test probe 1 and the test chip, an insulating protective layer can be set around the test probe 1 on the outside of the base 11 of the test probe 1. The material and thickness of the insulating protective layer can be set according to the specific probe size, and can play both insulating and protective positioning roles. The insulating protective layer can also be understood as an insulating positioning layer.

[0038] Specifically, one or more probe holders can be provided. When multiple probe holders are provided, the setting positions and numbers of the probe holders correspond to the test probes, that is, one probe holder is provided for each test probe. At this time, the insulating positioning layer can be provided on the outside of each test probe, or a corresponding insulating positioning layer can be provided between two adjacent test probes. The provision of the insulating positioning layer can, on the one hand, perform position positioning and calibration on the test probe and the chip to be tested when they are docked, and on the other hand, can also isolate the two adjacent test probes to avoid collision or signal interference between the test probes and the adjacent test probes during deformation.

[0039] In addition, in order to improve the degree of integration of the device and simplify the manufacturing process, the probe holder can also be uniformly set, that is, a probe holder is set, and each test probe forms an integrated structure through a connecting part, that is, the test probes are distributed in a regular array on the probe holder, and the setting position of the test probe corresponds one-to-one to the array distribution of the metal bumps. At this time, the insulating positioning layer can be set between two adjacent test probes, or it can be set only at the outermost edge position of the probe holder to play a positioning role; it can be seen that when there are a large number of test probes, several insulating positioning layers can also be set in the middle, that is, corresponding insulating positioning layers are set after a plurality of test probes are separated to ensure regional isolation and positioning functions. In addition, the body of the insulating positioning layer can be solid or hollow, and the hollow structure has a better heat dissipation effect. The specific number and position of the settings are not specifically limited by the present invention, and can be flexibly set according to the structure of the chip to be tested and the test requirements.

[0040] Furthermore, to achieve a positioning effect and prevent the test probe from colliding with the solder cap, the length of the insulating positioning layer parallel to the chip protection layer is not less than the length of the test probe, or is set to be the same as the length of the test probe. This allows the test probe to be located outside the support column when the insulating positioning layer contacts the chip protection layer, achieving a positioning effect. Furthermore, a positioning structure can be provided on the chip protection layer. When the insulating positioning layer abuts the chip protection layer, its lower end can be restrained within the corresponding position of the positioning structure, preventing the insulating positioning layer from tilting and improving positioning accuracy.

[0041] In addition, the insulating positioning layer can adopt various forms such as plate structure or columnar structure. When it adopts plate structure, its positioning and isolation effects are better, but the space occupied will also be larger. When adopting columnar structure, although it can save space, the isolation effect between test probes may be affected to a certain extent. It can be set according to the distribution density of metal bumps on the chip to be tested.

[0042] It should be noted that, in a specific embodiment of the present invention, the insulation function can be achieved only by the insulating positioning layer. In this case, the length of the insulating positioning layer can be shortened, and the positioning between the chip to be tested and the test probe can be achieved by other positioning structures.

[0043] In addition, the test probe 1 can be connected to the external test system through the PCB. Under special needs, an adapter board can also be set up, that is, the test probe is connected to the PCB through the adapter board, and the PCB is connected to the external test system, and then the chip to be tested is tested through the test system. In other words, the test probe 1 can be fixed on the PCB through the probe bracket. During the test process, the external test system is connected to the test probe 1 through the PCB to realize the transmission of the test signal.

[0044] In another specific embodiment of the present invention, in order to ensure the position accuracy between the test probe 1 and the metal bump, a first positioning mechanism can be set on the chip protection layer 3, and a second positioning mechanism can be set on the test probe 1 or the probe bracket. During the test process, the test probe 1 and the metal bump are positioned by the cooperation of the first positioning mechanism and the second positioning mechanism, and the support column 22 is ensured to be in the center position of the opening end 13 as much as possible. When the opening end 13 shrinks and deforms and contacts and conducts with the support column 22, the solder cap 21 is ensured to be located in the internal cavity to avoid collision and damage between it and the test probe 1.

[0045] Specifically, the first positioning mechanism can be at least one alignment hole provided on the probe holder, and the second positioning mechanism in this case is a marker corresponding to the position of the alignment hole. When relative displacement occurs between the probe and the chip to be tested 6, the marker can be observed through the alignment hole by a camera device. If the marker can be accurately aligned with the alignment hole in a direction perpendicular to the probe holder, it indicates that the positions of the two are corresponding. At this time, the positions of the two can be further adjusted along this direction, and finally a contact test is achieved. The marker can be a special color or logo of the chip to be tested, etc.

[0046] In addition, the first positioning mechanism and the second positioning mechanism can also be configured as compatible structural members such as positioning blocks and grooves. For example, the first positioning mechanism includes at least one positioning block / groove, and the second positioning mechanism in this case is a groove / positioning block that is compatible with the positioning block / groove in position and shape. When the test probe 1 moves to the point where it contacts and conducts with the support column, the positioning block can be limited in the groove corresponding to the position. That is, through the cooperation of the positioning block and the groove, the position of the chip to be tested and the test probe can be accurately found.

[0047] Furthermore, a corresponding camera module can be set on the side of the alignment hole away from the marking object; wherein, the camera module can capture a real-time position image between the chip to be detected and the test probe, so that the test system controls the driving device to adjust the relative position of the chip to be detected and the test probe according to the position image.

[0048] In addition, a pressure sensor can be set above the test probe 1. When the test probe contacts the chip protective layer, the pressure sensor can detect a mutation signal. At this time, it can be confirmed that the test probe has moved to the corresponding position, thereby preventing the test probe from being damaged or broken due to excessive extrusion. That is, double insurance is achieved through the positioning structure and the pressure sensor to improve the test accuracy.

[0049] In another specific embodiment of the present invention, the test probe can also be set to a structural form of multiple test clamps, or a number of air holes can be directly set on the test probe, so that when the test probe is in contact with the support column, the internal cavity is a non-closed cavity structure, which can ensure that the inside of the test probe is connected to the outside world when temperature changes occur during the test process, thereby achieving a heat dissipation effect and preventing adverse effects of excessive temperature on the chip or test probe.

[0050] Specifically, the test probe 1 also includes a fixing portion connected to the probe bracket; wherein the test clamp is arranged on the fixing portion, and the test clamp cooperates with the fixing portion to form a non-closed cavity structure. When the test clamp is in contact with the support column, the solder cap is avoided in the cavity structure. The non-closed cavity structure can be achieved by controlling the gap between the test clamps. For example, when the test clamp is retracted inward to the junction of the support column, there will be a gap between each test clamp, or a through hole is provided on the fixing portion, thereby realizing the non-closed structure of the cavity, which can effectively conduct with the outside world when temperature changes occur during the test process, achieve heat dissipation effect, and prevent excessive temperature from causing adverse effects on the chip or the test clamp.

[0051] It can be seen that the test jaws are evenly or symmetrically distributed on the fixed part, thereby ensuring that the support column is evenly stressed during the test. In addition, the test jaws can be set to an arc-shaped plate structure or a columnar structure. For example, three test jaws can be set, and the gaps between the three test jaws are distributed in a "Y" shape, or four test jaws can be set, and the gaps between the four test jaws are distributed in a "cross" shape. The specific number or shape of the test jaws can be flexibly set according to the size of the support column or the test space, and is not limited to the specific structure shown in the accompanying drawings.

[0052] Furthermore, in order to ensure that the test clamp can effectively contact the support column after parallelization and realize the transmission of test signals, a protruding contour contact portion can be provided at the end of the test clamp. The size of the contour contact portion can be slightly larger than the size of the main body of the test clamp and smaller than the size of the support column, so that the contour contact portion can be adapted to the shape of the support column to realize effective contact and signal transmission.

[0053] It can be seen that in the embodiment of the test clamp, the test probe is set to a multi-test clamp structure that can form a non-closed cavity structure, and at the same time, it is combined with a shape-changeable memory metal material, so that the open end of the test clamp can be deformed accordingly when the preset conditions are met, so that the open end can be in contact with the support column in a clamping manner to avoid direct contact with the solder cap, thereby achieving conduction between the test probe and the metal bump through the support column, ensuring the integrity of the solder cap, and avoiding the chip performance and service life being affected by damage to the solder cap.

[0054] It should be noted that the above embodiments can be combined with each other and are not limited to one or two specific combinations.

[0055] When using the chip testing device of the present invention to test the chip to be tested, first, the test probe with the open end in an open state is moved to the outside of the metal bump of the chip to be tested by a driving device; then, the open end is controlled to retract and contact and conduct with the support column of the metal bump, and the test probe and the chip to be tested are connected through the support column; finally, the external testing system realizes the detection of the chip to be tested through the test probe.

[0056] Specifically, when using a chip testing device to test a chip to be tested, the probe holder and the test probe thereon are first moved by a driving device to directly above the metal bump on the chip to be tested; then, when the open end of the test probe is in an open state, the test probe is controlled to move downward or the chip to be tested moves upward until the first positioning mechanism and the second positioning mechanism are aligned with each other, at which time the open end is located outside the support column of the metal bump; then, the test probe is controlled to be within a second preset temperature range, and due to the characteristics of the memory metal, the open end of the test probe will shrink inward at this time and contact and conduct with the support column, and finally, the external testing system completes the relevant performance testing of the chip through the test probe.

[0057] Among them, when the test probe is connected to the chip to be tested, the test probe can be driven to move to the outside of the support column by the driving device, so that the entire metal bump is located in the internal cavity of the test probe; the chip to be tested can also be driven to move by the driving device, so that each metal bump is moved to the inside of the test probe at the corresponding position. This application does not specifically limit the driving object of the driving device.

[0058] According to the chip testing device of the utility model described above, the test probe is set to a cavity structure with an open end, and is combined with a shape-changeable memory metal material, so that the open end of the test probe can be deformed accordingly when the preset conditions are met, so that the open end can be opened and closed to contact and conduct with the support column, avoiding direct contact with the solder cap, thereby realizing the test signal transmission between the test probe and the metal bump through the support column, which can ensure the integrity of the solder cap and avoid affecting the chip performance and service life due to damage to the solder cap.

[0059] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed within the present invention. Any reference to a figure in a claim should not be construed as limiting the claim to which it relates.

[0060] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a system claim may also be implemented by a single unit or device through software or hardware. Second-order terms are used to indicate names and do not imply any particular order.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

[0062] The chip testing device according to the present invention has been described above by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various improvements may be made to the chip testing device described above without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A chip testing device, characterized in that: include: A test probe; wherein, The metal bumps of the chip to be tested include support pillars arranged on the chip protection layer and solder caps located at the ends of the support pillars; The test probe includes a memory metal piece; The test probe has an open end, and when a preset condition is met, the open end of the test probe contacts and conducts with the support column, so that the chip to be tested and the test probe perform signal transmission through the support column; The setting positions of the test probes correspond one-to-one to the distribution of the metal bumps.

2. The chip testing device according to claim 1, characterized in that: It also includes a probe holder and a driving device for driving the probe holder or the chip to be detected to move; wherein, The test probe is arranged on the probe bracket; The test probe has a deformable internal cavity structure; When the temperature is within a first preset temperature range, the open end of the test probe is opened, and the test probe is moved to the outside of the support column by the driving device; When the temperature is within a second preset range, the open end of the test probe retracts and clamps the support column, and the solder cap is retracted into the inner cavity of the test probe; The preset condition is the second preset temperature range.

3. The chip testing device according to claim 2, wherein: The first preset temperature range is 0 to 70°C; The second preset temperature is in a range of greater than 70°C.

4. The chip testing device according to claim 2, wherein: The cross section of the internal cavity is a circular structure; and The difference between the cross-sectional dimensions of the internal cavity and the solder cap ranges from 0 to 50 μm.

5. The chip testing device according to claim 2, wherein: The test probe further includes a base portion connected to the probe bracket; wherein, An insulating protection layer is arranged on the outer side of the base portion and surrounds the test probe.

6. The chip testing device according to claim 5, characterized in that: The open end is connected to the base portion via an inclined side arm; In the first preset temperature range, the size of the open end is larger than the size of the solder cap.

7. The chip testing device according to claim 5, characterized in that: The cross section of the base portion is rectangular or square.

8. The chip testing device according to claim 1, wherein: A first positioning mechanism is provided on the chip protection layer, and a second positioning mechanism is provided on the test probe; wherein, The first positioning mechanism and the second positioning mechanism are used to cooperate to position the test probe and the metal bump.

9. The chip testing device according to claim 1, wherein: The test probe is connected to an external test system via a PCB board, and the chip to be tested is tested via the test system.

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