Thyristor semiconductor

Abstract

The utility model discloses a thyristor semiconductor. A thyristor semiconductor includes a first layer on a first surface of a substrate, wherein the first layer is a first P layer. The second layer on the second surface of the substrate is a second P layer. The second surface is opposite to the first surface. The third layer is between the first layer and the substrate. The isolation region is located along an edge of the substrate. The isolation region is adjacent to the second P layer. The emitter near the third layer is connected to the cathode.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to thyristors, and more particularly, to semiconductor-based thyristors. Background Art

[0002] Thyristors are semiconductor switches used to control the flow of electric current. Thyristors are used in applications such as household appliances (lighting, heating, temperature control, alarm activation, fan speed), power tools (for controlling motor speed, stapling events, battery charging), and outdoor equipment (sprinklers, gas engine ignition, electronic displays, area lighting, exercise equipment, and fitness equipment). In many applications, thyristors perform critical functions and help meet environmental, speed, and reliability specifications that their electromechanical counterparts cannot achieve.

[0003] Like a diode, a thyristor is a three-terminal device with a PNPN configuration consisting of an anode terminal connected to the first P-section, a cathode terminal connected to the second N-section, and a gate terminal connected to the P-section closest to the cathode. A thyristor is known to have three PN junctions. When a positive voltage is applied to the gate terminal of the device, the thyristor turns on and remains on even if the gate terminal signal is removed. If the current flowing through the thyristor drops below the latching current level, the thyristor turns off.

[0004] The non-repetitive peak off-state voltage, also known as VDSM, is a key thyristor characteristic. VDSM applies when there is no signal between the gate and cathode and within the rated junction temperature range. VDSM applies for periods less than half a sine wave at commercial frequencies. The repetitive peak reverse current of the silicon-controlled rectifier (SCR), also known as IRRM, is another important thyristor characteristic. IRRM is the maximum instantaneous value of the reverse current resulting from the application of a repetitive peak reverse voltage. VDSM and IRRM are affected by the arrangement of the materials that make up the three PN junctions.

[0005] It is with respect to these and other considerations that the present improvements may be useful. Utility Model Content

[0006] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] An exemplary embodiment of a thyristor semiconductor according to the present disclosure may include: a first layer located on a first surface of a substrate, wherein the first layer is a first P layer; a second layer located on a second surface of the substrate is a second P layer; the second surface is opposite the first surface; a third layer located between the first layer and the substrate; an isolation region located along an edge of the substrate; the isolation region connected to the second P layer; and an emitter electrode adjacent to the third layer connected to a cathode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A to Figure 1B is a diagram showing a thyristor semiconductor according to the prior art;

[0009] Figures 2A to 2B is a diagram illustrating a thyristor semiconductor according to an exemplary embodiment;

[0010] Figure 3 It is shown that according to the prior art Figure 1A to Figure 1B A flow chart of a method for manufacturing a thyristor semiconductor;

[0011] Figure 4 is a diagram showing a method for Figures 2A to 2B A flow chart of a first method for manufacturing a thyristor semiconductor; and

[0012] Figure 5 is a diagram showing a method for Figures 2A to 2B A flow chart of a second manufacturing method of a thyristor semiconductor. DETAILED DESCRIPTION

[0013] Disclosed are a thyristor semiconductor and a method for manufacturing the thyristor semiconductor. The semiconductor thyristor is characterized by a double base region on the cathode side to increase VDSM and a single base region on the anode side to retain sufficient substrate width, thereby reducing IRRM.

[0014] For convenience and clarity, terms such as "top," "bottom," "upper," "lower," "vertical," "horizontal," "lateral," "transverse," "radial," "inner," "outer," "left," and "right" may be used herein to describe the relative placement and orientation of features and components, each relative to the geometry and orientation of other features and components appearing in the perspective, exploded perspective, and cross-sectional views provided herein. The terminology is not intended to be limiting and includes the words specifically mentioned, their derivatives, and words of similar meaning.

[0015] Figure 1A to Figure 1B is a representative diagram showing a thyristor semiconductor 100 according to the related art. Figure 1A is a cross-sectional view of a thyristor semiconductor 100, and Figure 1BFIG1 is a top view of a thyristor semiconductor 100. The thyristor semiconductor 100 is called a single-sided mesa thyristor. As shown in the figure, the thyristor semiconductor 100 includes a gate 104, a cathode 120, and an anode 116. Figure 1A The trench 106 shown in the two parts 106a and 106b is arranged to surround the emitter 102 of the thyristor semiconductor 100, as shown in FIG. Figure 1B As shown, trench portion 106a is adjacent to gate 104 and trench portion 106b is adjacent to emitter 102. In addition to emitter 102, the semiconductor region is characterized by a P-base region 110, an N-substrate 112, and a P-base region 114. Isolation region 118 is provided along the outer edge of thyristor semiconductor 100 and surrounding trench 106. Emitter 102 is an N+ doped region (heavily doped). Therefore, for thyristor semiconductor 100, a PN junction exists between emitter 102 and P-base region 110, a second PN junction exists between P-base region 110 and N-substrate 112, and a third PN junction exists between N-substrate 112 and P-base region 114, for a total of three PN junctions, which are characteristic of thyristors.

[0016] Semiconductor silicon is etched to form trench 106, and then glass is applied as a passivation region. Glass 108 covers the entire trench 106, visible as glass portions 108a, 108b, and 108c. Glass portion 108c is positioned between gate 104 and emitter 102, and glass portion 108c is also positioned on both emitter 102 and P-base region 110. P-base region 110 and P-base region 114 are formed simultaneously and have identical doping characteristics. This is known as a symmetrical P-base diffusion structure on both the anode 116 and cathode 120 sides (in other words, on either side of N-substrate 112). By depositing and diffusing P-base region 110 and P-base region 114 simultaneously, thyristor semiconductor 100 has the same junction depth for both anode 116 and cathode 120.

[0017] To increase the breakdown voltage of the thyristor semiconductor to exceed that of the thyristor semiconductor 100, the P-base junction depth can be increased. For example, a lightly doped P-base diffusion region can be introduced to increase the breakdown voltage. This process is symmetrical, with the lightly doped P-base diffusion performed at both the cathode and anode. If the P-base region is added only at the cathode 120, the P-base region 110 is deeper than the P-base region 114. However, if the P-base region is added to both the cathode 120 and the anode 116, both the P-base region 110 and the P-base region 114 are deeper than before. Because both the P-base region 110 and the P-base region 114 are deeper than before, the thickness of the N-substrate can be reduced.

[0018] A thinner N-substrate reduces the drift region area of ​​the N-substrate. Consequently, the reverse breakdown capability of the thyristor semiconductor is limited due to the thinner N-substrate. To achieve a higher breakdown voltage, a thicker wafer can be used. However, a thicker wafer results in a higher V (on-state voltage). V is the main voltage when the thyristor is in the on state.

[0019] Furthermore, the VDSM capability can be improved by increasing the P-base junction depth of the thyristor semiconductor 100. However, this results in a thinner N-substrate, which increases the IRRM. It is difficult to design a thyristor semiconductor that optimizes both VDSM and IRRM.

[0020] Figures 2A to 2B is a representative diagram of a thyristor semiconductor 200 according to an exemplary embodiment. Figure 2A is a cross-sectional view of the thyristor semiconductor 200, and Figure 2B FIG2 is a top view of a thyristor semiconductor 200. The structure of the thyristor semiconductor 200 solves the above-described problems. The thyristor semiconductor 200 includes a gate 204, a cathode 220, and an anode 216, as shown in the figure. Figure 2A The trench 206 shown in the two parts 206a and 206b is arranged to surround the emitter 202 of the thyristor semiconductor 200, as shown in FIG. Figure 2B As shown, trench portion 206 a is adjacent to gate 204 and trench portion 206 b is adjacent to emitter 202 .

[0021] In addition to the emitter 202, the semiconductor region also features a P-base region 222 (at the gate 204), a P-base region 210, an N-substrate 212, and a P-base region 214. An isolation region 218 is provided on the opposite side of the thyristor semiconductor 200. The isolation region 218 is provided along the outer edge of the thyristor semiconductor 200 and surrounds the trench 206 of the thyristor semiconductor 100. The emitter 202 is an N+ doped region (heavily doped). Therefore, for the thyristor semiconductor 200, a PN junction exists between the emitter 202 and the P-base region 222, a second PN junction exists between the P-base region 210 and the N-substrate 212, and a third PN junction exists between the N-substrate 212 and the P-base region 214, for a total of three PN junctions, which are characteristic of thyristors.

[0022] Semiconductor silicon is etched to form trench 206, and then glass is used as a passivation region. Glass 208 covers the entire trench 206, visible as glass portions 208a, 208b, and 208c, wherein glass portion 208c is disposed between gate 204 and emitter 202, wherein glass 208c is also disposed on both emitter 202 and P-base region 222.

[0023] The P-base region 222 and the P-base region 214 are diffused simultaneously and have the same doping characteristics. Nevertheless, while the thyristor semiconductor 100 is symmetrical, the structure of the thyristor semiconductor 200 is asymmetrical due to the addition of the P-base region 210 in the cathode region. The thyristor semiconductor 200 is characterized by both the P-base region 210 and the P-base region 222 in the cathode 220 region. In some embodiments, this increases the blocking capacity of the thyristor semiconductor 200, thereby improving the VDSM characteristics. On the back side (anode 216), a single P-base region diffusion (P-base region 214) is used. This enables the thickness of the N-substrate 212 to be maintained so that it is not too thin and the use of a thicker wafer can be avoided. In some embodiments, due to the change in structure, the voltage capability of the thyristor semiconductor 200 is better than that of the thyristor semiconductor 100. In some embodiments, the N-substrate 212 of the thyristor semiconductor 200 is slightly thicker than the N-substrate 112 of the thyristor semiconductor 100 (note that the P-base region 114 ( FIG. 1 ) is slightly thicker than the P-base region 214 ( FIG. 2 )). Furthermore, in some embodiments, the P-base region 210 is doped differently than the P-base region 110. In an exemplary embodiment, the doping of the P-base region 210 is shallower (more lightly doped) than the doping of the P-base region 222. In some embodiments, the doping concentration of the P-base region 210 is 2.5E16 / cm 3 , and the doping concentration of the P base region 222 is 1.5E18 / cm 3 .

[0024] In some embodiments, the thyristor semiconductor 200 features a dual base region at the cathode 220, comprising both a P-base region 222 and a P-base region 210. Furthermore, in some embodiments, the thyristor semiconductor 200 features a single base region (P-base region 214) at the anode 216. The single base region at the anode 216 preserves the N-substrate width 212 sufficient to reduce IRRM. In some embodiments, the structure of the thyristor semiconductor 200 thus improves both VDSM and IRRM.

[0025] Figure 3 FIG1 is a flow chart illustrating a method 300 for producing the thyristor semiconductor 100 of FIG1 according to the prior art. An N-substrate is obtained (block 302). A P-type isolation photoresist and diffusion are applied simultaneously on both sides of the N-substrate (block 304). A P-base region diffusion is then applied on both sides of the N-substrate (block 306). The P-base region can be boron-doped or gallium-doped. An N+ photoresist and diffusion are then applied at the emitter (block 308). Subsequent trenching, passivation, contact, and metallization processes are then performed (block 310).

[0026] Figure 4FIG2 is a flow chart illustrating a method 400 performed in producing the thyristor semiconductor 200 of FIG2 according to some embodiments. As with method 300, the process begins by obtaining an N-substrate (block 402). A P-type isolation photoresist and diffusion operation are performed, with the operations occurring simultaneously on both sides of the N-substrate (e.g., the cathode side and the anode side) (block 404). To form the P-base layer 210, a P-base gallium diffusion is then performed on both sides of the N-substrate (e.g., the cathode side and the anode side) (block 406).

[0027] Next, a milling operation is performed on the back side (e.g., the anode side) to remove the anode P- (block 408). P-base diffusion is performed on both sides of the N-substrate (cathode side and anode side) (block 410), so that P-base region 222 and P-base region 214 are formed. In some embodiments, the P-base region is boron-doped. In other embodiments, the P-base region is gallium-doped. Therefore, using method 400, gallium diffusion is used to form P-base region 210 (block 406), but since gallium diffusion is performed on both the anode side and the cathode side, milling is performed on the anode side to remove P- (block 408), and then, P-base region 214 and P-base region 222 are formed using P-base diffusion (block 410).

[0028] To form the emitter 202 layer, an N+ emitter photoresist and diffusion are performed at the emitter (e.g., emitter 202) (block 412). In some embodiments, the N+ emitter doping is heavily doped compared to the N- substrate doping. Subsequently, trenching, passivation, contact, and metallization processes are performed (block 414) to form the thyristor semiconductor 200.

[0029] Figure 5 FIG2 is a flow chart illustrating an alternative method 500 for producing the thyristor semiconductor 200 of FIG2 according to some embodiments. As with methods 300 and 400, the process begins with a semiconductor wafer doped with an N-substrate (block 502). A P-type isolation photoresist and diffusion operation are performed, with the operations occurring simultaneously on both sides of the N-substrate (e.g., the cathode side and the anode side) (block 504). To form the P-base layer 210, a P-base boron diffusion is then performed on the cathode side of the N-substrate (block 506), thereby producing the P-base region 210 ( FIG2 ).

[0030] P-base diffusion is performed on both sides of the N-substrate (both on the cathode-side P-base region 222 and the anode-side P-base region 214) (block 508). In some embodiments, the P-base region is boron-doped. In other embodiments, the P-base region is gallium-doped. Thus, using method 500, boron diffusion is used to form the P-base region 210 (block 506), and because the boron diffusion is performed only on the cathode side, a milling step (as in block 408) is unnecessary, and the P-base region 214 and the P-base region 222 are then formed (block 508).

[0031] To form the emitter 202 layer, an N+ emitter photoresist and diffusion are performed at the emitter (e.g., emitter 202) (block 510). In some embodiments, the N+ emitter doping is heavily doped compared to the N- substrate doping. Subsequently, trenching, passivation, contact, and metallization processes are performed (block 512) to form the thyristor semiconductor 200.

[0032] As used herein, an element or operation recited in the singular and preceded by the word "a" or "an" should be understood to include plural elements or operations unless such exclusion is explicitly stated. In addition, reference to "one embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0033] Although the present disclosure refers to certain embodiments, many modifications, variations, and changes to the described embodiments are possible without departing from the field and scope of the present disclosure, as defined in the appended claims. Therefore, it is intended that the present disclosure not be limited to the described embodiments, but rather have the full scope defined by the following claims and their equivalents.

Claims

1. A thyristor semiconductor, characterized in that: The thyristor semiconductor comprises: A first layer, the first layer being disposed on the first surface of the substrate and comprising a first P layer; a second layer, the second layer being provided on a second surface of the substrate opposite to the first surface, and comprising a second P layer; a third layer disposed between the first layer and the substrate; an isolation region disposed along an edge of the substrate, wherein the isolation region is coupled to the second P layer; and An emitter is disposed adjacent to the first layer, wherein the emitter is coupled to a cathode.

2. The thyristor semiconductor according to claim 1, characterized in that The first P layer includes a P base region.

3. The thyristor semiconductor according to claim 2, characterized in that The second P layer includes the P base region.

4. The thyristor semiconductor according to claim 1, characterized in that The third layer includes a P-base region.

5. The thyristor semiconductor according to claim 1, characterized in that The emitter is N+ doped.

6. The thyristor semiconductor according to claim 1, characterized in that The substrate is N-doped.

7. The thyristor semiconductor according to claim 6, characterized in that The emitter and the first P layer form a first PN junction, the third layer and the substrate form a second PN junction, and the substrate and the second P layer form a third PN junction.

8. The thyristor semiconductor according to claim 1, characterized in that The thyristor semiconductor further includes a trench disposed adjacent to the isolation region.

9. The thyristor semiconductor according to claim 8, characterized in that The trench is adjacent to the substrate, the first P layer, and the third layer.

10. The thyristor semiconductor according to claim 8, characterized in that The trenches are covered with glass, wherein the glass serves as a passivation region.

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