Display circuit for oscilloscope probe impedance detection

Abstract

The utility model relates to a display circuit for oscilloscope probe impedance detection, and belongs to the technical field of electronic measurement. The circuit comprises an input impedance detection module, a comparator module, a calibration zeroing module, a signal latch module and a logic merging and nixie tube display module. The output end of the input impedance detection module I and the output end of the input impedance detection module II are connected with the input end of the comparator module I and the input end of the comparator module II respectively, the output end of the comparator module I is connected with the input end of the calibration zeroing module and the input end of the signal latch module I, and the output end of the comparator module II is connected with the input end of the calibration zeroing module and the input end of the signal latch module II. The output end of the signal latch module I and the output end of the signal latch module II are both connected with the logic merging and nixie tube display module. According to the utility model, rapid detection of probe impedance is realized through a hardware circuit structure, results are displayed in real time through a nixie tube, and the efficiency and reliability of measurement are improved.

Description

Technical Field

[0001] The utility model relates to a display circuit for impedance detection of an oscilloscope probe, belonging to the field of electronic measurement. Background Art

[0002] Oscilloscope probes are one of the key tools in electronic measurement, but during use, the probes may be damaged or their performance degraded, affecting the accuracy of the measurement results. Therefore, it is particularly important to detect the impedance state of the probe before use to ensure its normal operation. Existing measurement methods mostly use manual detection, which is not only complicated to operate and easily affected by human factors, but also has defects such as low efficiency and high risk of misjudgment. To solve the above problems, the utility model proposes a display circuit for oscilloscope probe impedance detection, which realizes rapid detection of probe impedance through a hardware circuit structure and uses a digital tube to display the results in real time, thereby improving the efficiency and reliability of the measurement. Summary of the Invention

[0003] In order to solve the above-mentioned problems existing in manual detection of oscilloscope probes, the utility model proposes a display circuit for oscilloscope probe impedance detection. Through the hardware circuit structure, it can quickly detect the input probe impedance state and accurately display it, thereby realizing fast and reliable probe status monitoring.

[0004] The technical solution of the utility model is: a display circuit for oscilloscope probe impedance detection, including an input impedance detection module I1-1, an input impedance detection module II1-2, a comparator module I2-1, a comparator module II2-2, a calibration zero adjustment module 3, a signal latch module I4-1, a signal latch module II4-2 and a logic merging and digital tube display module 5;

[0005] The output ends of the input impedance detection module I1-1 and the input impedance detection module II1-2 are respectively connected to the input ends of the comparator module I2-1 and the comparator module II2-2, the output end of the comparator module I2-1 is respectively connected to the input ends of the calibration zeroing module 3 and the signal latch module I4-1, the output end of the comparator module II2-2 is respectively connected to the input ends of the calibration zeroing module 3 and the signal latch module II4-2, and the output ends of the signal latch module I4-1 and the signal latch module II4-2 are both connected to the logic merging and digital tube display module 5.

[0006] As a further solution of the present invention, the input impedance detection module I1-1 and the input impedance detection module II1-2 are used to detect the input impedance of the probe at different gears; wherein the input impedance detection module I1-1 corresponds to the X1 gear input, and the input impedance detection module II1-2 corresponds to the X10 gear input;

[0007] The comparator module I2-1 and the comparator module II2-2 are used for comparing the input signals under different gears and generating corresponding high and low level outputs; wherein the comparator module I2-1 corresponds to the X1 gear, and the comparator module II2-2 corresponds to the X10 gear;

[0008] The calibration zero module 3 is used for zero calibration of the output signals of the comparator module I2-1 and the comparator module II2-2, so as to ensure the consistency of the reference level of the comparator output and improve the detection precision;

[0009] The signal latching module I4-1 and the signal latching module II4-2 are used for latching the probe impedance states under different gears, so as to keep the stable display of the probe impedance states; wherein the signal latching module I4-1 corresponds to the latching of the X1 gear signal, and the signal latching module II4-2 corresponds to the latching of the X10 gear signal;

[0010] The logic merging and nixie tube display module 5 is used for performing logic merging processing on the latched probe impedance state signals and displaying the current impedance state of the probe through the nixie tube, so as to facilitate the user to intuitively view the state information of the probe and ensure the accuracy and stability of the nixie tube display.

[0011] As a further scheme of the utility model, the input impedance detection module I1-1 contains resistance R1, R3, R7, slide rheostat R2, capacitor C1 and wiring terminal X1; wiring terminal X1 is connected with the positive phase input end of operational amplifier U1A of comparator module 2-1, resistance R3, R7, one end of capacitor C1 respectively, the other end of resistance R3 is connected with VCC, the other end of resistance R7, capacitor C1 is grounded; one end of resistance R1 is connected with VCC, the other end of resistance R1 is connected with one end of slide rheostat R2 and the inverting input end of operational amplifier U1A of comparator module 2-1 respectively, the other end of slide rheostat R2 is grounded;

[0012] The input impedance detection module II1-2 contains resistance R6, R4, slide rheostat R5, R8, capacitor C2 and wiring terminal X10; wiring terminal X10 is connected with the positive phase input end of operational amplifier U1B of comparator module 2-2, resistance R6, R8, one end of capacitor C2 respectively, the other end of resistance R6 is connected with VCC, the other end of resistance R8, capacitor C2 is grounded; one end of resistance R4 is connected with VCC, the other end of resistance R4 is connected with one end of slide rheostat R5 and the inverting input end of operational amplifier U1B of comparator module 2-2 respectively, the other end of slide rheostat R5 is grounded.

[0013] As a further scheme of the utility model, the comparator module I2-1 includes LM393AD operational amplifier U1A and resistance R10, the output of LM393AD operational amplifier U1A is connected with the D end of 74F74D flip-flop U2A of signal latch module I4-1, one input of 74LS02D logic gate U6A of calibration zero module 3, one end of resistance R10 respectively, the other end of resistance R10 is connected with VCC, the 8 pin of LM393AD operational amplifier U1A is connected with VCC, the 4 pin of connecting operational amplifier U1A is grounded;

[0014] The comparator module II2-2 includes LM393AD operational amplifier U1B and resistance R11, the output of LM393AD operational amplifier U1B is connected with the D end of 74F74D flip-flop U2B of signal latch module II4-2, another input of 74LS02D logic gate U6A of calibration zero module 3, one end of resistance R11 respectively, the other end of resistance R11 is connected with VCC, the 8 pin of connecting operational amplifier U1A, 4 pin is suspended and not connected.

[0015] As a further scheme of the utility model, the calibration zero module 3 includes 74LS02D logic gate U6A, 74LS08N logic gate U7A, light emitting diode LED2, resistance R15 and switch S3, the output of 74LS02D logic gate U6A is connected with one end of switch S3, the other end of switch S3 is connected with the input of 74LS08N logic gate U7A, the output of 74LS08N logic gate U7A is connected with the anode of light emitting diode LED2, the cathode of light emitting diode LED2 is connected with one end of resistance R15, the other end of resistance R15 is connected with ground, light emitting diode LED2 indicates calibration state, and switch S3 is used for manual calibration control;

[0016] As a further scheme of the utility model, the signal latch module I4-1 includes 74F74D flip-flop U2A, resistance R12 and switch S1, the CLR end of 74F74D flip-flop U2A is connected with VCC and one end of switch S1 respectively, the other end of switch S1 is connected with one end of resistance R12, the other end of resistance R12 is grounded, the CLK end of 74F74D flip-flop U2A is grounded, the PR end of 74F74D flip-flop U2A is connected with VCC, and one input of 74LS08N logic gate U3A of logic merging and nixie tube display module 5 is connected with the Q end of 74F74D flip-flop U2A;

[0017] The signal latch module II4-2 includes a 74F74D trigger U2B, a resistor R9 and a switch S2; the CLR end of the 74F74D trigger U2B is respectively connected to VCC and one end of the switch S2, the other end of the switch S2 is connected to one end of the resistor R9, and the other end of the resistor R9 is grounded; the CLK end of the 74F74D trigger U2B is grounded, the PR end of the 74F74D trigger U2B is connected to VCC, and the Q end of the 74F74D trigger U2B is connected to the logic merge and the other input end of the 74LS08N logic gate U3A of the digital tube display module 5.

[0018] As a further solution of the present utility model, the logic merging and digital tube display module 5 includes a 74LS47D encoder U5, a 74LS08N logic gate U3A and a digital tube U4;

[0019] Pins 1 and 2 of the 74LS47D encoder U5 are connected to the output end of the 74LS08N logic gate U3A, pins 3, 4, and 5 of the 74LS47D encoder U5 are connected to VCC, pins 12, 9, 15, and 14 of the 74LS47D encoder U5 are respectively connected to pin D, pin E, pin F, and pin A of the digital tube U4, while pin F is connected to pin G, and pins B, C, and CA of the digital tube U4 are connected to VCC.

[0020] The present invention uses two comparator modules, I2-1 and II2-2, to detect the input impedance state of the probe in the multiplication 1 and multiplication 10 gears, respectively, and outputs high and low level signals. These high and low level signals are latched by the D flip-flops of the signal latch modules I4-1 and II4-2, and then logically merged by an AND gate (74LS08N logic gate U3A) to determine whether the probe is operating normally in the two gears. The result is converted into a signal that drives a 7-segment digital tube via a BCD encoder (74LS47D encoder U5), displaying "True" or "False" to indicate the status of the probe.

[0021] When performing the X1 gear test, S1 is closed to transmit the signal from the X1 input impedance detection module I1-1 to the comparator module I2-1, the calibration zero adjustment module 3, the signal latch module I4-1, and the logic merging and digital tube display module 5 in sequence;

[0022] When performing the X10 gear test, close S2 and transmit the signal from the X10 input impedance detection module II1-2 to the comparator module II2-2, the calibration zero adjustment module 3, the signal latch module II4-2, and the logic merging and digital tube display module 5 in sequence; S1 and S2 control the path of the input signal.

[0023] R2 and R5 serve as calibration resistors. During the calibration process, S3 must be closed to incorporate the calibration resistors into the circuit. During zero adjustment, R2 and R5 are connected to the power supply VCC through R1 and R4, respectively, to ensure that the signal is within the normal range. LED2 lights up green to indicate that zero adjustment is complete. S3 can then be disconnected to save circuit power.

[0024] R7 and R8 are connected to the input end of the circuit respectively to simulate the impedance of the oscilloscope probe. One end of R7 and R8 is connected to the signal input end respectively, and the other end is grounded. At this time, R7 and R8 form a voltage divider circuit to simulate the actual impedance state of the probe. In actual applications, the values ​​of R7 and R8 can be selected according to the impedance characteristics of the actual probe to ensure stable operation of the circuit.

[0025] The signal detection module receives the signal passing through the input end, transmits the signal to the seven-segment digital tube display module after A / D conversion; when the probes are normal, the seven-segment digital tube displays "T", indicating that the probes are working normally; if at least one gear is abnormal, it displays "F", indicating that the probe status is abnormal.

[0026] The beneficial effects of the utility model are:

[0027] 1. The utility model provides a display circuit for oscilloscope probe impedance detection, which can accurately measure and display the input impedance of the probe at different gears;

[0028] 2. Compared with the traditional impedance detection method, this utility model combines the input impedance detection module, the comparator module and the signal latch module to achieve higher detection accuracy and real-time performance;

[0029] 3. The calibration and zero adjustment module of the utility model can effectively eliminate the measurement error caused by system deviation, ensure the measured impedance value is more accurate, and improve the reliability of the entire measurement system;

[0030] 4. The design of the signal latch module of this utility model enables the impedance state of the probe to be stably displayed even in the case of signal fluctuations, thus avoiding the influence of transient signals on the results and enhancing the user's confidence in the measurement results;

[0031] 5. This utility model adopts a digital display mode, which intuitively displays the probe impedance status through a digital tube, allowing operators to quickly obtain the required information, improving work efficiency and reducing the possibility of human error;

[0032] 6. Through the design of the logic merging module, the utility model can effectively integrate the output signals of multiple modules and realize dynamic display under various states, providing users with more operational flexibility and scalability, and adapting to different experimental environments and needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the circuit principle of the utility model.

[0034] Figure 1 The reference numerals are as follows: 1-1-input impedance detection module I, 1-2-input impedance detection module II, 2-1-comparator module I, 2-2-comparator module II, 3-calibration zero adjustment module, 4-1-signal latch module I, 4-2-signal latch module II, 5-logic merger and digital tube display module, R1, R3, R4, R6, R7, R8, R9, R10, R11, R12, R15-resistors, R2, R5-sliding resistors, C1, C2-capacitors, X1, X10-terminal blocks, U1A, U1B-LM393AD operational amplifier, U6A-74LS02D logic gate, U7A, U3A-74LS08N logic gate, LED2-light-emitting diode, S1, S2, S3-switch, U2A, U2B-74F74D trigger, U5-74LS47D encoder, U4-digital tube. DETAILED DESCRIPTION

[0035] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0036] Example 1: Figure 1 As shown, a display circuit for oscilloscope probe impedance detection includes an input impedance detection module I1-1, an input impedance detection module II1-2, a comparator module I2-1, a comparator module II2-2, a calibration zero adjustment module 3, a signal latch module I4-1, a signal latch module II4-2 and a logic merging and digital tube display module 5;

[0037] The output ends of the input impedance detection module I1-1 and the input impedance detection module II1-2 are respectively connected to the input ends of the comparator module I2-1 and the comparator module II2-2, the output end of the comparator module I2-1 is respectively connected to the input ends of the calibration zeroing module 3 and the signal latch module I4-1, the output end of the comparator module II2-2 is respectively connected to the input ends of the calibration zeroing module 3 and the signal latch module II4-2, and the output ends of the signal latch module I4-1 and the signal latch module II4-2 are both connected to the logic merging and digital tube display module 5.

[0038] As a further solution of the present invention, the input impedance detection module I1-1 and the input impedance detection module II1-2 are used to detect the input impedance of the probe at different gears; wherein the input impedance detection module I1-1 corresponds to the X1 gear input and is used for impedance detection at the multiplication gear 1, and the input impedance detection module II1-2 corresponds to the X10 gear input and is used for impedance detection at the multiplication gear 10;

[0039] The comparator module I2-1 and the comparator module II2-2 are used to compare the input signals under different gears and generate corresponding high and low level outputs; wherein the comparator module I2-1 corresponds to the X1 gear and is used to compare the input signal of the multiplication gear 1, and the comparator module II2-2 corresponds to the X10 gear and is used to compare the input signal of the multiplication gear 10;

[0040] The calibration and zeroing module 3 is used to perform zero calibration on the output signals of the comparator module I2-1 and the comparator module II2-2;

[0041] The signal latch module I4-1 and the signal latch module II4-2 are used to latch the probe impedance state under different gears, wherein the signal latch module I4-1 corresponds to the latching of the X1 gear signal, and the signal latch module II4-2 corresponds to the latching of the X10 gear signal;

[0042] The logic combining and digital tube display module 5 is used to perform logic combining processing on the latched probe impedance state signal and display the current impedance state of the probe through the digital tube.

[0043] As a further solution of the present invention, the input impedance detection module I1-1 includes resistors R1, R3, R7, a sliding rheostat R2, a capacitor C1 and a wiring terminal X1; the wiring terminal X1 is respectively connected to the non-inverting input terminal of the operational amplifier U1A of the comparator module 2-1, the resistors R3, R7, and one end of the capacitor C1, the other end of the resistor R3 is connected to VCC, and the other ends of the resistor R7 and the capacitor C1 are both grounded; one end of the resistor R1 is connected to VCC, and the other end of the resistor R1 is respectively connected to one end of the sliding rheostat R2 and the inverting input terminal of the operational amplifier U1A of the comparator module 2-1, and the other end of the sliding rheostat R2 is grounded;

[0044] The input impedance detection module II1-2 includes resistors R6, R4, sliding rheostats R5, R8, capacitor C2 and terminal X10; terminal X10 is respectively connected to the positive input terminal of the operational amplifier U1B of the comparator module 2-2, resistors R6, R8 and one end of the capacitor C2, the other end of the resistor R6 is connected to VCC, and the other ends of the resistor R8 and capacitor C2 are both grounded; one end of the resistor R4 is connected to VCC, and the other end of the resistor R4 is respectively connected to one end of the sliding rheostat R5 and the inverting input terminal of the operational amplifier U1B of the comparator module 2-2, and the other end of the sliding rheostat R5 is grounded.

[0045] As a further solution of the present invention, the comparator module I2-1 includes an LM393AD operational amplifier U1A and a resistor R10; the output end of the LM393AD operational amplifier U1A is respectively connected to the D end of the 74F74D trigger U2A of the signal latch module I4-1, one input end of the 74LS02D logic gate U6A of the calibration zeroing module 3, and one end of the resistor R10, the other end of the resistor R10 is connected to VCC, the 8th pin of the LM393AD operational amplifier U1A is connected to VCC, and the 4th pin of the operational amplifier U1A is connected to ground;

[0046] The comparator module II2-2 includes U1B of the LM393AD operational amplifier and a resistor R11; the output end of the LM393AD operational amplifier U1B is respectively connected to the D end of the 74F74D trigger U2B of the signal latch module II4-2, the other input end of the 74LS02D logic gate U6A of the calibration zeroing module 3, and one end of the resistor R11. The other end of the resistor R11 is connected to VCC, and the 8th pin and the 4th pin of the operational amplifier U1A are left floating.

[0047] As a further solution of the present invention, the calibration zeroing module 3 includes a 74LS02D logic gate U6A, a 74LS08N logic gate U7A, a light-emitting diode LED2, a resistor R15 and a switch S3; the output end of the 74LS02D logic gate U6A is connected to one end of the switch S3, the other end of the switch S3 is connected to the input end of the 74LS08N logic gate U7A, the output end of the 74LS08N logic gate U7A is connected to the anode of the light-emitting diode LED2, the cathode of the light-emitting diode LED2 is connected to one end of the resistor R15, and the other end of the resistor R15 is connected to the ground.

[0048] As a further solution of the present invention, the signal latch module I4-1 includes a 74F74D trigger U2A, a resistor R12 and a switch S1; the CLR terminal of the 74F74D trigger U2A is respectively connected to VCC and one end of the switch S1, the other end of the switch S1 is connected to one end of the resistor R12, and the other end of the resistor R12 is grounded; the CLK terminal of the 74F74D trigger U2A is grounded, the PR terminal of the 74F74D trigger U2A is connected to VCC, and the Q terminal of the 74F74D trigger U2A is connected to a logic merge and an input terminal of the 74LS08N logic gate U3A of the digital tube display module 5;

[0049] The signal latch module II4-2 includes a 74F74D trigger U2B, a resistor R9 and a switch S2; the CLR end of the 74F74D trigger U2B is respectively connected to VCC and one end of the switch S2, the other end of the switch S2 is connected to one end of the resistor R9, and the other end of the resistor R9 is grounded; the CLK end of the 74F74D trigger U2B is grounded, the PR end of the 74F74D trigger U2B is connected to VCC, and the Q end of the 74F74D trigger U2B is connected to the logic merge and the other input end of the 74LS08N logic gate U3A of the digital tube display module 5.

[0050] As a further solution of the present utility model, the logic merging and digital tube display module 5 includes a 74LS47D encoder U5, a 74LS08N logic gate U3A and a digital tube U4;

[0051] Pins 1 and 2 of the 74LS47D encoder U5 are connected to the output end of the 74LS08N logic gate U3A, pins 3, 4, and 5 of the 74LS47D encoder U5 are connected to VCC, pins 12, 9, 15, and 14 of the 74LS47D encoder U5 are respectively connected to pin D, pin E, pin F, and pin A of the digital tube U4, while pin F is connected to pin G, and pins B, C, and CA of the digital tube U4 are connected to VCC.

[0052] The working principle of this utility model:

[0053] To test the X1 position, the operator presses S1. This closes, transmitting the signal from the X1 input to the subsequent circuitry. Switch S2 is connected to the X10 input terminal, enabling access to the X10 position. To test the X10 position, the operator presses S2. Once S2 closes, the signal from the X10 input is transmitted to the subsequent circuitry. The switch states of S1 and S2 control the path of the input signal.

[0054] R2 and R5 serve as calibration resistors. During calibration, S3 must be closed to incorporate the calibration resistors into the circuit. During zero adjustment, R2 and R5 are connected to the power supply VCC via R1 and R4, respectively, to ensure the signal is within the normal range. LED2 illuminates green to indicate zero adjustment is complete. S3 can then be disconnected to conserve circuit power.

[0055] R7 and R8 are connected to the circuit's input terminals, simulating the impedance of the oscilloscope probe. One end of each terminal is connected to the signal input terminal, and the other end is grounded. R7 and R8 form a voltage divider circuit, simulating the probe's actual impedance. In practical applications, the values ​​of R7 and R8 can be selected based on the actual probe's impedance characteristics to ensure stable circuit operation.

[0056] The 74LS47D encoder U5 converts the signal into A / D and transmits it to the digital tube U4.

[0057] When all the probes are normal, the seven-segment digital tube displays "T" (or "t"), indicating that the probes are working normally; if at least one gear is abnormal, it displays "F", indicating that the probe status is abnormal.

[0058] When S1 or S2 is closed, the input signal enters the circuit of the present invention through the input terminal, passes through the calibration resistors R2 and R5, and is then transmitted to the analog probe impedance R7 and R8, simulating the state of the probe impedance.

[0059] After passing through the analog impedance, the signal enters the signal comparator module. The comparator compares the input signal with the set threshold and outputs the result to the digital tube U4.

[0060] When performing a second measurement, the operator must disconnect S1 and S2 after completing the first measurement to ensure the circuit is disconnected. Then, select the appropriate gear as needed and repeat the operation.

[0061] The utility model can accurately measure the input impedance of the oscilloscope probe through the coordinated work of various modules;

[0062] Signal acquisition: When making a measurement, the operator selects the X1 or X10 position as needed and connects the probe to the circuit by pressing the corresponding switch (S1 or S2).

[0063] Calibration process: Before measurement, connect the calibration resistors R2 and R5 to the circuit by closing S3, and use a known good probe to zero until LED2 lights up to indicate that the device is normal.

[0064] Signal comparison: After passing through R7 and R8, the signal enters the comparator module. The comparator determines the state of the input signal based on the set threshold and outputs the result to the digital tube display module in real time.

[0065] Result display: Through logical combination and digital tube display module 5, the result output by the comparator is converted into a digital display on the seven-segment digital tube in real time, which is convenient for users to read.

[0066] The specific embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A display circuit for oscilloscope probe impedance detection, characterized in that: It comprises an input impedance detection module I (1-1), an input impedance detection module II (1-2), a comparator module I (2-1), a comparator module II (2-2), a calibration zero adjustment module (3), a signal latch module I (4-1), a signal latch module II (4-2) and a logic merging and digital tube display module (5); The output ends of the input impedance detection module I (1-1) and the input impedance detection module II (1-2) are respectively connected to the input ends of the comparator module I (2-1) and the comparator module II (2-2); the output end of the comparator module I (2-1) is respectively connected to the input ends of the calibration zero adjustment module (3) and the signal latch module I (4-1); the output end of the comparator module II (2-2) is respectively connected to the input ends of the calibration zero adjustment module (3) and the signal latch module II (4-2); and the output ends of the signal latch module I (4-1) and the signal latch module II (4-2) are both connected to the logic merging and digital tube display module (5).

2. The display circuit for oscilloscope probe impedance detection according to claim 1, wherein: The input impedance detection module I (1-1) and the input impedance detection module II (1-2) are used to detect the input impedance of the probe at different gears; The comparator module I (2-1) and the comparator module II (2-2) are used to compare input signals under different gears and generate corresponding high and low level outputs; The calibration zeroing module (3) is used to perform zeroing calibration on the output signals of the comparator module I (2-1) and the comparator module II (2-2); The signal latch module I (4-1) and the signal latch module II (4-2) are used to latch the impedance states of the probes at different gears; The logic merging and digital tube display module (5) is used for performing logic merging processing on the latched probe impedance state signal and displaying the current impedance state of the probe through the digital tube.

3. The display circuit for oscilloscope probe impedance detection according to claim 1, wherein: The input impedance detection module I (1-1) includes resistors R1, R3, R7, a sliding rheostat R2, a capacitor C1 and a wiring terminal X1; the wiring terminal X1 is respectively connected to the non-inverting input terminal of the operational amplifier U1A of the comparator module I (2-1), the resistors R3, R7 and one end of the capacitor C1, the other end of the resistor R3 is connected to VCC, and the other ends of the resistor R7 and the capacitor C1 are both grounded; one end of the resistor R1 is connected to VCC, the other end of the resistor R1 is respectively connected to one end of the sliding rheostat R2 and the inverting input terminal of the operational amplifier U1A of the comparator module I (2-1), and the other end of the sliding rheostat R2 is grounded; The input impedance detection module II (1-2) includes resistors R6, R4, sliding rheostats R5, R8, capacitor C2 and a wiring terminal X10; the wiring terminal X10 is respectively connected to the non-inverting input terminal of the operational amplifier U1B of the comparator module II (2-2), the resistors R6, R8 and one end of the capacitor C2, the other end of the resistor R6 is connected to VCC, and the other ends of the resistor R8 and the capacitor C2 are both grounded; one end of the resistor R4 is connected to VCC, and the other end of the resistor R4 is respectively connected to one end of the sliding rheostat R5 and the inverting input terminal of the operational amplifier U1B of the comparator module II (2-2), and the other end of the sliding rheostat R5 is grounded.

4. The display circuit for oscilloscope probe impedance detection according to claim 1, wherein: The comparator module I (2-1) includes an LM393AD operational amplifier U1A and a resistor R10; the output end of the LM393AD operational amplifier U1A is respectively connected to the D end of the 74F74D trigger U2A of the signal latch module I (4-1), an input end of the 74LS02D logic gate U6A of the calibration zero adjustment module (3), and one end of the resistor R10, the other end of the resistor R10 is connected to VCC, the 8th pin of the LM393AD operational amplifier U1A is connected to VCC, and the 4th pin of the operational amplifier U1A is connected to ground; The comparator module II (2-2) includes an LM393AD operational amplifier U1B and a resistor R11; the output end of the LM393AD operational amplifier U1B is respectively connected to the D end of the 74F74D trigger U2B of the signal latch module II (4-2), the other input end of the 74LS02D logic gate U6A of the calibration zero adjustment module (3), and one end of the resistor R11, the other end of the resistor R11 is connected to VCC, and the 8th pin and the 4th pin of the operational amplifier U1A are left floating.

5. The display circuit for oscilloscope probe impedance detection according to claim 1, wherein: The calibration zero adjustment module (3) comprises a 74LS02D logic gate U6A, a 74LS08N logic gate U7A, a light emitting diode LED2, a resistor R15 and a switch S3; the output end of the 74LS02D logic gate U6A is connected to one end of the switch S3, the other end of the switch S3 is connected to the input end of the 74LS08N logic gate U7A, the output end of the 74LS08N logic gate U7A is connected to the anode of the light emitting diode LED2, the cathode of the light emitting diode LED2 is connected to one end of the resistor R15, and the other end of the resistor R15 is grounded.

6. The display circuit for oscilloscope probe impedance detection according to claim 1, wherein: The signal latch module I (4-1) includes a 74F74D trigger U2A, a resistor R12, and a switch S1; the CLR terminal of the 74F74D trigger U2A is connected to VCC and one end of the switch S1 respectively, the other end of the switch S1 is connected to one end of the resistor R12, and the other end of the resistor R12 is grounded; the CLK terminal of the 74F74D trigger U2A is grounded, the PR terminal of the 74F74D trigger U2A is connected to VCC, and the Q terminal of the 74F74D trigger U2A is connected to a logic merge and an input terminal of a 74LS08N logic gate U3A of a digital tube display module (5); The signal latch module II (4-2) includes a 74F74D trigger U2B, a resistor R9 and a switch S2; the CLR terminal of the 74F74D trigger U2B is respectively connected to VCC and one end of the switch S2, the other end of the switch S2 is connected to one end of the resistor R9, and the other end of the resistor R9 is grounded; the CLK terminal of the 74F74D trigger U2B is grounded, the PR terminal of the 74F74D trigger U2B is connected to VCC, and the Q terminal of the 74F74D trigger U2B is connected to the other input terminal of the 74LS08N logic gate U3A of the logic merge and the digital tube display module (5).

7. The display circuit for oscilloscope probe impedance detection according to claim 1, characterized in that: The logic merging and digital tube display module (5) comprises a 74LS47D encoder U5, a 74LS08N logic gate U3A and a digital tube U4; Pins 1 and 2 of the 74LS47D encoder U5 are connected to the output end of the 74LS08N logic gate U3A, pins 3, 4, and 5 of the 74LS47D encoder U5 are connected to VCC, pins 12, 9, 15, and 14 of the 74LS47D encoder U5 are respectively connected to pin D, pin E, pin F, and pin A of the digital tube U4, while pin F is connected to pin G, and pins B, C, and CA of the digital tube U4 are connected to VCC.

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