Multi-chip packaging structure

Abstract

The utility model discloses a multi-chip packaging structure, comprising a frame which comprises a base island and a pin group which is arranged at an interval with the base island; the heat conductor is arranged on the first surface of the base island, and the heat conductor comprises a conductive layer; the first chip is arranged on the conducting layer of the heat conductor and is electrically connected with the pin group; the second chip is arranged on the first surface of the base island and is electrically connected with the conductive layer of the heat conductor and the first chip; and the plastic package body at least wraps a part of the base island and a part of the pin group. The multi-chip packaging structure provided by the utility model can realize serial packaging of multiple chips, has a high-voltage internal insulation design, and improves the working efficiency of the chips.

Description

TECHNICAL FIELD

[0001] The utility model belongs to chip packaging technical field, and specifically relates to a multi-chip packaging structure. BACKGROUND

[0002] At present, most of the packaging products on the market do not carry out internal insulation design; the number of packaged chips is single, the circuit connection efficiency is low, and the chip working efficiency and heat dissipation are affected; the pin polarity usually has only three poles, and the use efficiency of the source electrode chip is not optimized.

[0003] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present utility model and should not be construed as acknowledging or implying in any form that this information constitutes prior art with respect to the present utility model. SUMMARY

[0004] The utility model discloses a multi-chip packaging structure, which can realize multi-chip series packaging and has high-voltage internal insulation design, thereby improving the chip working efficiency.

[0005] In order to achieve the above-mentioned purpose, the technical scheme provided by the utility model in one embodiment is as follows:

[0006] A multi-chip packaging structure comprises:

[0007] A frame comprises a base island and a pin group arranged at intervals with the base island;

[0008] A heat conductor is arranged on the first surface of the base island, and the heat conductor comprises an electrically conductive layer;

[0009] A first chip is arranged on the electrically conductive layer of the heat conductor and electrically connected with the pin group;

[0010] A second chip is arranged on the first surface of the base island and electrically connected with the electrically conductive layer of the heat conductor and the first chip; and

[0011] A plastic package body is arranged to at least wrap part of the base island and part of the pin group.

[0012] In one or more embodiments of the utility model, the pin group comprises first pins, second pins and third pins arranged at intervals, and the first pins, the second pins and the third pins are respectively electrically connected with the first chip.

[0013] In one or more embodiments of the utility model, the first pins are arranged as gate pins and connected with the gate lead wires of the first chip.

[0014] The second pin is arranged as a Kelvin pole pin and connected with a source lead of the first chip.

[0015] The third pin is arranged as a source pin and connected with a source lead of the first chip.

[0016] In one or more embodiments of the present application, the frame is a metal frame.

[0017] In one or more embodiments of the present application, the heat conductor further comprises a ceramic layer, the ceramic layer is arranged on the first surface of the base island, and the conductive layer is arranged on the side surface of the ceramic layer away from the first surface.

[0018] In one or more embodiments of the present application, the heat conductor is a copper clad ceramic sheet.

[0019] In one or more embodiments of the present application, the material of the plastic package body comprises epoxy resin.

[0020] In one or more embodiments of the present application, a tinning layer is arranged on the surface of the frame exposed by the plastic package body.

[0021] In one or more embodiments of the present application, the multi-chip packaging structure further comprises a heat sink, and the heat sink is arranged on the surface of the base island exposed by the plastic package body.

[0022] In one or more embodiments of the present application, the second chip is fixed on the first surface of the base island by tin paste; and / or,

[0023] The heat conductor is fixed on the first surface of the base island by tin paste; and / or,

[0024] The first chip and the second chip are arranged in series.

[0025] Compared with the prior art, the multi-chip packaging structure can realize series packaging of multiple chips and has high-voltage internal insulation.

[0026] The multi-chip packaging structure insulates the back surface of the first chip, effectively avoids the risk of breakdown of the source and gate of the first chip due to reverse voltage of the frame, and protects the reverse voltage of the source of the second chip. Through the internal insulation design, the chip working environment is optimized, and the risk of abnormal high voltage breakdown is avoided.

[0027] The multi-chip packaging structure adopts a multi-pin structure, and the polarity of the multi-pin is divided into a source, a gate and a Kelvin pole, which effectively improves the working efficiency of the chip.

[0028] The multi-chip packaging structure of the utility model, series connection circuit design between chips can promote the efficiency of the use of the connection, effective voltage division, improve product efficiency.

[0029] The multi-chip packaging structure of the utility model, through the exposed fin design, it is beneficial to product heat dissipation. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to make the person in the art better understand the technical scheme in the utility model, the technical scheme in the utility model embodiments will be described clearly and completely below in conjunction with the drawings of the utility model embodiments, obviously, the described embodiments are only some embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the utility model.

[0031] Figure 1 It is the exploded view of the multi-chip packaging structure in the utility model embodiment 1.

[0032] Figure 2 It is the internal schematic view of the multi-chip packaging structure in the utility model embodiment 1.

[0033] Figure 3 It is the schematic view of the multi-chip packaging structure in the utility model embodiment 2.

[0034] Figure 4 It is the schematic view of the multi-chip packaging structure in the utility model embodiment 3. DETAILED DESCRIPTION

[0035] In order to make the person in the art better understand the technical scheme in the utility model, the technical scheme in the utility model embodiments will be described clearly and completely below in conjunction with the drawings of the utility model embodiments, obviously, the described embodiments are only some embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the utility model.

[0036] As the background art, the existing chip packaging structure, mostly do not carry out internal insulation design;The number of packaged chips is single, and the circuit connection efficiency is low, which affects the chip working efficiency and heat dissipation;Pin polarity usually only has three poles, and the use efficiency of the source chip is not optimized.

[0037] Based on this, the utility model provides a kind of multi-chip packaging structure, for realizing multi-chip series connection and packaging structure high voltage internal insulation, optimize chip working efficiency.

[0038] As Figure 1 And Figure 2As shown, the multi-chip packaging structure in the embodiment 1 of the utility model, including, frame 10, heat conductor 20, first chip 30, second chip 40 and plastic package body 50.

[0039] Frame 10 is metal frame, and its material is preferably copper.Frame 10 includes base island 11 and pin group 12 arranged at intervals with base island 11.Base island 11 has a first surface for carrying heat conductor 20, first chip 30 and second chip 40.Pin group 12 includes first pin 121, second pin 122 and third pin 123 arranged at intervals.The first pin 121, the second pin 122 and the third pin 123 are electrically isolated and respectively connected with the first chip 30.

[0040] Preferably, the first pin 121 is arranged as a gate pin, the second pin 122 is arranged as a Kelvin pin, and the third pin 123 is arranged as a source pin.

[0041] It can be understood that the source of the chip is usually connected to the source pin, but in the multi-chip packaging structure of the application, the Kelvin pin is arranged, and the source of the first chip 30 is connected to the Kelvin pin through another lead line, which can reduce the influence of the source lead inductance in the multi-chip packaging structure, improve the high-speed switching function of the chip, and also improve the efficiency of large and medium-sized high-efficiency power switches.

[0042] The heat conductor 20 is arranged on the first surface of the base island 11.The heat conductor 20 includes a ceramic layer 21 and a conductive layer 22.The ceramic layer 21 is fixed on the first surface of the base island 11 by the tin paste 60.The conductive layer 22 is arranged on the side surface of the ceramic layer 21 away from the first surface of the base island 11.The heat conductor 20 is preferably a single-sided copper-clad ceramic sheet.

[0043] The first chip 30 is a main chip, which can be a SiC chip.The first chip 30 is arranged on the conductive layer 22 of the heat conductor 20 and electrically connected with the pin group 12.Exemplarily, the first chip 30 includes a source, a drain and a gate.The gate of the first chip 30 is connected with the lead of the first pin 121, the source of the first chip 30 is connected with the lead of the second pin 122, and the source of the first chip 30 is also connected with the lead of the third pin 123.The drain of the first chip 30 is electrically connected with the conductive layer 22.

[0044] In this embodiment, the length of the plurality of pins on the pin group 12 is relatively short, so the multi-chip packaging structure in this embodiment is suitable for surface mounting.

[0045] The second chip 40 is a secondary chip, which can be a Si chip. The second chip 40 is fixed on the first surface of the base island 11 through the tin paste 60 and is arranged in a spaced manner with the heat conductor 20. The second chip 40 is electrically connected with the conductive layer 22 of the heat conductor 20 through a lead wire, and the second chip 40 is connected in series with the first chip 30 through the conductive layer 22. The second chip 40 is electrically connected with the source electrode of the first chip 30 through a lead wire.

[0046] The plastic package 50 is preferably epoxy resin. The plastic package 50 at least wraps part of the base island 11 and part of the pin group 12. The heat conductor 20, the first chip 30, the second chip 40 and the lead wire for electrical connection are all covered in the plastic package 50. The frame 10 is provided with a tinned layer on the surface exposed by the plastic package 50.

[0047] In order to improve the heat dissipation performance of the packaging structure, the surface of the base island 11 exposed by the plastic package 50 is further provided with a heat dissipation fin.

[0048] As shown in Figure 3 Embodiment 2 of the utility model provides a plug-in multi-chip packaging structure. The difference between embodiment 2 and embodiment 1 is that the pin group 12 in embodiment 2 has a plurality of long pins, which are all long strip-shaped pins. Therefore, the multi-chip packaging structure in embodiment 2 is suitable for through-hole plug-in packaging.

[0049] As shown in Figure 4 Embodiment 3 of the utility model provides a multi-chip packaging structure with a folded corner. The difference between embodiment 3 and embodiment 1 is that the pin group 12 in embodiment 3 has a plurality of long pins, which are all folded. Therefore, the multi-chip packaging structure in embodiment 3 is suitable for surface corner packaging.

[0050] Compared with the prior art, the multi-chip packaging structure of the utility model is suitable for high-voltage environment, can realize series packaging of multi-chips, and has high-voltage internal insulation in the packaging structure.

[0051] The multi-chip packaging structure of the utility model insulates the back surface of the first chip, effectively avoids the risk of breakdown of the source electrode and the gate electrode of the first chip due to the reverse voltage of the frame, and protects the reverse voltage of the source electrode of the second chip. Through the internal insulation design, the chip working environment is optimized, and the risk of abnormal high-voltage breakdown is avoided.

[0052] The multi-chip packaging structure of the utility model adopts a multi-pin structure, and the polarity of the multi-pin is divided into a source electrode, a gate electrode and a Kelvin electrode, which effectively improves the working efficiency of the chip.

[0053] The multi-chip packaging structure of the utility model improves the efficiency of the connected line, effectively divides the voltage, and improves the working efficiency of the product.

[0054] The multi-chip packaging structure is convenient for heat dissipation through the exposed cooling fins.

[0055] It is apparent for a person skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, but that it can be implemented in other embodiments without deviating from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than that of the above description, and all changes coming within the meaning and equivalency range of the claims are intended to be embraced therein. Any reference signs in the claims should not be construed as limiting the claims to the figures in which the reference signs are used.

[0056] Furthermore, it should be understood that, although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the specification is described in this way only for the sake of clarity, and a person skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by a person skilled in the art.

Claims

1. A multi-chip package structure, characterized in that: include: A frame, the frame comprising a base island and a pin group spaced apart from the base island; a heat conductor, disposed on the first surface of the base island, the heat conductor comprising a conductive layer; A first chip is disposed on the conductive layer of the heat conductor and is electrically connected to the pin group; a second chip disposed on the first surface of the base island and electrically connected to the conductive layer of the heat conductor and the first chip; as well as The plastic package at least wraps a portion of the base island and a portion of the pin group.

2. The multi-chip package structure according to claim 1, wherein: The pin group includes a first pin, a second pin, and a third pin that are spaced apart from each other. The first pin, the second pin, and the third pin are electrically connected to the first chip respectively.

3. The multi-chip package structure according to claim 2, wherein: The first pin is set as a gate pin and connected to the gate lead of the first chip; The second pin is configured as a Kelvin pin and connected to a source lead of the first chip; and The third pin is set as a source pin and connected to the source lead of the first chip.

4. The multi-chip package structure according to claim 1, wherein: The frame is a metal frame.

5. The multi-chip package structure according to claim 1, wherein: The heat conductor further includes a ceramic layer, which is disposed on the first surface of the base island. The conductive layer is disposed on a side surface of the ceramic layer that is away from the first surface.

6. The multi-chip package structure according to claim 1, wherein: The heat conductor is a copper-clad ceramic sheet.

7. The multi-chip package structure according to claim 1, wherein: The material of the plastic package body includes epoxy resin.

8. The multi-chip package structure according to claim 1, wherein: A tin-plated layer is provided on the surface of the frame exposed by the plastic packaging body.

9. The multi-chip package structure according to claim 1, wherein: It also includes a heat sink, which is arranged on the surface of the base island exposed by the plastic package body.

10. The multi-chip package structure according to claim 1, wherein: The second chip is fixed on the first surface of the base island by solder paste; and / or, The heat conductor is fixed on the first surface of the base island by solder paste; and / or, The first chip and the second chip are arranged in series.

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