Mainboard and mainboard management device
By adding resistors near the signal branch points on the motherboard, the problem of signal quality degradation caused by signal line length exceeding the limits of the ESPI protocol was solved, thereby improving the stability and accuracy of signal transmission and ensuring the stable operation of the server system.
Patent Information
- Application Number
- CN202521860767.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-29
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2035-08-29
AI Technical Summary
In traditional server architectures, during signal transmission between the motherboard and management board, the length of the signal line exceeds the length limit specified by the ESPI protocol, resulting in signal quality degradation, severe signal reflection and backtracking, and affecting the stability and accuracy of data transmission between the CPU and BMC.
Adding resistors near signal branch points on the motherboard reduces signal reflection and improves signal quality by matching the characteristic impedance of the signal lines, ensuring that the signal line length does not exceed a specific limit.
It improves the stability and accuracy of data transmission between the CPU and BMC, ensuring the stable operation of the server system, especially when the signal line length is increased.
Smart Images
Figure CN223450417U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the utility model relates to computer field, specifically, relate to a kind of mainboard and mainboard management device. BACKGROUND
[0002] In traditional server architecture, mainboard is the heart of server, it bears central processing unit (Central Processing Unit, for short CPU) and other key components, and management board, such as baseboard management controller (Baseboard Management Controlle, for short BMC) board is used to monitor and manage the independent microcontroller of system state.
[0003] In the signal transmission process between mainboard and independent management board, especially when using embedded serial peripheral interface (Embedded Serial Peripheral Interface, for short ESPI) protocol, the signal of long link will be affected by signal reflection, impedance mismatch and signal attenuation, resulting in signal integrity damage, signal waveform distortion, and further affecting the stability of corresponding device operation.
[0004] Therefore, there is a technical problem of low device operation stability in the prior art. UTILITY MODEL CONTENT
[0005] The embodiment of the utility model provides a kind of mainboard and mainboard management device, to at least solve the technical problem of low operation stability of the device where mainboard and management board are located.
[0006] According to one embodiment of the utility model, a kind of mainboard is provided, and mainboard includes central microprocessor, programmable logic device, signal branch point and resistance, central microprocessor, programmable logic device and resistance are connected with signal branch point respectively, and resistance is used to connect signal branch point and baseboard management controller on management board.
[0007] Optionally, as an optional embodiment, the length of signal line between resistance and signal branch point is less than or equal to the first length.
[0008] Optionally, as an optional embodiment, the length of signal line between central microprocessor and signal branch point is less than or equal to the second length.
[0009] Optionally, as an optional embodiment, the length of signal line between programmable logic device and signal branch point is less than or equal to the third length.
[0010] Optionally, as an optional embodiment, signal branch point is the bifurcation point of embedded serial peripheral interface signal.
[0011] Optionally, as an optional embodiment, the signal line between the central microprocessor and the signal branching point is an embedded serial presence detect interface signal line, the signal line between the programmable logic device and the signal branching point is an embedded serial presence detect interface signal line, and the signal line between the resistor and the signal branching point is an embedded serial presence detect interface signal line.
[0012] According to another embodiment of the present application, a mainboard management device is provided, comprising: a mainboard and a management board, wherein the mainboard comprises a central microprocessor, a programmable logic device, a signal branching point and a resistor, the central microprocessor, the programmable logic device and the resistor are connected to the signal branching point respectively, and the management board comprises a baseboard management controller connected to the signal branching point through the resistor.
[0013] Optionally, as an optional embodiment, the length of the signal line between the resistor and the baseboard management controller is less than or equal to a fourth length.
[0014] Optionally, as an optional embodiment, the signal branching point is a branching point of an embedded serial presence detect interface signal.
[0015] Optionally, as an optional embodiment, the signal line between the baseboard management controller and the resistor is an embedded serial presence detect interface signal line.
[0016] The present application adds a resistor near the signal branching point on the mainboard, solves the technical problem that, when the management board is modularized designed (for example, the BMC is transferred from the mainboard to other board cards), the signal line length increases and exceeds the length limit specified in the ESPI protocol, the ESPI signal quality is reduced, signal reflection and backhook phenomena are serious, the stability and accuracy of data transmission between the CPU and the BMC are affected, and the stability of the device is low, and achieves the technical effect of improving the stability of the device. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0018] Figure 1 A structure diagram of a mainboard is provided for the embodiments of the present application.
[0019] Figure 2 A CPU end reading BMC waveform diagram after link optimization is provided for the embodiments of the present application.
[0020] Figure 3A structural diagram of a mainboard management device is provided in the embodiment of the present application. DETAILED DESCRIPTION
[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.
[0022] It should be noted that the terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.
[0023] The embodiments of the present application provide a mainboard and a mainboard management device, and the contents involved in the present application are explained here:
[0024] 1) Central Processing Unit (CPU) is the core component of a computer system, responsible for executing program instructions, processing data and controlling the operation of the computer system.
[0025] 2) Programmable Logic Device (PLD) is an electronic component that can be configured to perform specific logic functions. Common PLDs include CPLD (Complex Programmable Logic Device) and FPGA (Field-Programmable Gate Array).
[0026] 3) Signal Branch Point is a point in a circuit where a signal line branches or connects to multiple devices. In the present application, it is the branching point of the ESPI signal line.
[0027] 4) Resistor (R) is a circuit component used to limit the flow of current, and its resistance determines the size of the current. In the present application, it is used to match the characteristic impedance of the signal line, reduce reflection and improve signal quality.
[0028] 5) Baseboard Management Controller (BMC) is a microcontroller used for system management functions such as monitoring the health status of the server, controlling hardware resources and providing remote management capabilities.
[0029] 6) motherboard, the main circuit board of a computer system, which carries the CPU, memory, expansion slots and other key components, connecting all hardware devices through buses and interfaces.
[0030] 7) management board, in the utility model, refers to the circuit board carrying BMC, used for modular design, can be independent of the motherboard, providing remote management and monitoring functions.
[0031] As an optional embodiment, the above-mentioned motherboard, as shown in Figure 1 The motherboard 102 includes a central microprocessor 104, a programmable logic device 106, a signal branching point 108, and a resistor 110. The central microprocessor, programmable logic device, and resistor are connected to the signal branching point. The resistor is used to connect the signal branching point and the baseboard management controller on the management board. Figure 1 L1 is the signal connection line between the central microprocessor and the signal branching point, and L2 is the signal connection line between the programmable logic device and the signal branching point.
[0032] Optionally, the above-mentioned motherboard is used to represent the main circuit board of a computer system, which carries the CPU, memory, expansion slots and other key components, connecting all hardware devices through buses and interfaces.
[0033] It should be noted that the above-mentioned central microprocessor includes one or more processor cores, responsible for executing system instructions and processing data.
[0034] Further, the above-mentioned programmable logic device is a circuit for executing specific logic functions, such as CPLD (Complex Programmable Logic Device) and FPGA (Field-Programmable Gate Array).
[0035] It should be noted that the above-mentioned signal branching point includes the branching point of the ESPI signal line, i.e. the point where the signal line branches, used to connect multiple devices.
[0036] Further, the above-mentioned resistor is a circuit element used to reduce signal reflection and improve signal quality, whose resistance value needs to match the characteristic impedance of the target signal line.
[0037] Optionally, the above-mentioned management board refers to a separate circuit board carrying BMC (Baseboard Management Controller), used for remote management and monitoring of servers.
[0038] Further, the above-mentioned baseboard management controller is used for managing hardware resources of the server, providing remote management and monitoring capabilities, and communicating with a CPU on the mainboard through an ESPI signal line.
[0039] It should be noted that in the embodiment, a resistance is added near a signal branching point on the mainboard to connect the BMC on the management board, so as to optimize the quality of ESPI signal transmission. Specifically, the CPU and the CPLD on the mainboard are connected to the signal branching point and communicate through the ESPI signal line. The resistance is also connected to the signal branching point, but is connected to the BMC through the ESPI signal line. The addition of the resistance aims to reduce signal reflection when the signal line is transmitted over a long distance and improve signal integrity, so as to ensure stable data transmission between the BMC and the CPU.
[0040] By adding the resistance near the signal branching point on the mainboard, the embodiment of the utility model solves the technical problem that when the management board is modularized designed (for example, the BMC is transferred from the mainboard to other board cards), the length of the signal line increases and exceeds the length limit specified in the ESPI protocol, which leads to a decrease in the quality of the ESPI signal, serious signal reflection and backhook, and affects the stability and accuracy of data transmission between the CPU and the BMC, thereby leading to low stability of the equipment. The technical effect of improving the stability of the equipment is achieved. Further, as an example, the signal waveform diagram of the CPU reading the BMC after link optimization of the embodiment is shown in Figure 2 , Figure 2 In (a) of the waveform diagram before the improvement, Figure 2 In (b) of the waveform diagram after adding the series resistance at the node position, the improvement effect is obvious, and the backhook disappears. In the diagram, the horizontal coordinate is time unit nanosecond; the vertical coordinate is voltage, unit volt, and specifically represents the voltage level of the signal. The stability of the voltage waveform can be used to intuitively evaluate the improvement effect of the signal quality.
[0041] As an optional embodiment, the length of the signal line between the resistance and the signal branching point is less than or equal to the first length.
[0042] It should be noted that the resistance is a basic electrical element in a circuit, which is used to limit the size of the current or adjust the voltage in the circuit. The main parameter of the resistance is resistance, which is expressed in ohms (Ω).
[0043] Optionally, the branching point is a point where the signal line branches in the signal transmission path or is connected to other signal lines. This is a position where the signal quality may be affected.
[0044] It should be noted that the signal line is a conductor for transmitting signals. The characteristics and design of the signal line directly affect the quality of the signal.
[0045] Further, the first length refers to the maximum allowed length of the signal line between the resistance and the branch point, and the length limit is to ensure the quality of signal transmission. For example, the first length can be but is not limited to 1 inch.
[0046] By limiting the length of the signal line between the resistance and the signal branch point, the embodiment of the utility model ensures that the signal does not experience a long transmission path before reaching the resistance, reduces signal distortion and reflection, improves signal quality, especially in the application of the ESPI signal line, improves the integrity and transmission efficiency of the signal.
[0047] As an optional embodiment, the length of the signal line between the central microprocessor and the signal branch point is less than or equal to the second length.
[0048] It should be noted that the above-mentioned second length is the maximum allowed length of the signal line from the CPU to the branch point, and the setting of the length ensures the quality of the signal before reaching the branch point, avoiding the problems of signal attenuation and reflection caused by long-distance transmission.
[0049] As an optional embodiment, the length of the signal line between the programmable logic device and the signal branch point is less than or equal to the third length.
[0050] Optionally, the above-mentioned third length is used to represent the maximum limit of the length of the signal line between the programmable logic device and the branch point, and this limit is to ensure signal quality and avoid signal reflection and attenuation caused by too long signal line.
[0051] As an optional embodiment, the signal branch point is the branching point of the embedded serial presence interface signal.
[0052] As an optional embodiment, the signal line between the central microprocessor and the signal branch point is an embedded serial presence interface signal line, the signal line between the programmable logic device and the signal branch point is an embedded serial presence interface signal line, and the signal line between the resistance and the signal branch point is an embedded serial presence interface signal line.
[0053] Optionally, in the signal transmission path, the signal branch point is the point where the signal line is split into multiple transmission paths. In this embodiment, the signal branch point is the branching point of the ESPI signal line. The embedded serial presence interface (ESPI) is a low-speed interface standard used for communication between devices on the motherboard, replacing the traditional LPC (Low Pin Count) interface, providing higher speed and better signal quality.
[0054] As an optional embodiment, the signal line between the central microprocessor and the branch point is an embedded serial presence detect interface signal line, the signal line between the programmable logic device and the branch point is an embedded serial presence detect interface signal line, and the signal line between the resistor and the branch point is an embedded serial presence detect interface signal line.
[0055] Optionally, as an optional example, a server motherboard is assumed, which contains a central microprocessor (CPU) and a programmable logic device (CPLD). The two communicate through an ESPI signal line to control and manage low-speed peripherals in the server system. In the layout design of the motherboard, the ESPI signal line forms a branch point at a certain point, one signal line continues to extend on the motherboard to connect the CPLD, and the other signal line is connected to the baseboard management controller (BMC) on the independent management board through a resistor (R) with a matched resistance and characteristic impedance.
[0056] In this example, the signal lines between the CPU and the branch point, the CPLD and the branch point, and the resistor and the branch point are all part of the embedded serial presence detect interface (ESPI) signal line. This means that these signal lines are designed and signal-transmitted in compliance with the ESPI protocol, thereby ensuring high-speed transmission and low-power consumption characteristics of the signal. The addition of the resistor, especially in the design of the signal line between the resistor and the branch point, is to address the problem of increased signal line length due to the modular design of the BMC. By matching the resistance, the signal reflection is effectively reduced, ensuring the communication quality between the BMC and the CPU and the CPLD on the motherboard. Even if the signal line is as long as 10 inches, the integrity and stability of the signal can still be maintained, so that the server system can operate normally and stably.
[0057] As an optional embodiment, as shown in Figure 3 The motherboard management device 116 includes a motherboard 102 and a management board 112. The motherboard includes a central microprocessor 104, a programmable logic device 106, a signal branch point 108, and a resistor 110. The central microprocessor, the programmable logic device, and the resistor are connected to the signal branch point. The management board includes a baseboard management controller 114, which is connected to the signal branch point through the resistor. Figure 3 In the figure, L1 is the signal connection line between the central microprocessor and the signal branch point, L2 is the signal connection line between the programmable logic device and the signal branch point, and L3 is the signal connection line between the baseboard management controller and the resistor.
[0058] Optionally, the above-mentioned motherboard is used to represent the main circuit board of a computer system, which carries the CPU, memory, expansion slot, and other key components, and connects all hardware devices through buses and interfaces.
[0059] It should be noted that the central microprocessor includes one or more processor cores responsible for executing system instructions and processing data.
[0060] Further, the programmable logic device is a circuit for performing specific logic functions, such as a CPLD (Complex Programmable Logic Device) and an FPGA (Field-Programmable Gate Array).
[0061] It should be noted that the signal branching point includes the branching point of the ESPI signal line, i.e. the point where the signal line branches, for connecting multiple devices.
[0062] Further, the resistance is a circuit element for reducing signal reflection and improving signal quality, and its resistance value needs to match the characteristic impedance of the target signal line.
[0063] Optionally, the management board refers to a separate circuit board carrying a BMC (Baseboard Management Controller) for remote management and monitoring of the server.
[0064] Further, the baseboard management controller is used to manage the hardware resources of the server, providing remote management and monitoring capabilities, and communicating with the CPU on the mainboard through the ESPI signal line.
[0065] It should be noted that in this embodiment, a resistance is added near the signal branching point on the mainboard to connect the BMC on the management board, so as to optimize the quality of ESPI signal transmission. Specifically, the CPU and the CPLD on the mainboard are connected to the signal branching point and communicate through the ESPI signal line. The resistance is also connected to the signal branching point, but is connected to the BMC through the ESPI signal line. The addition of the resistance aims to reduce signal reflection during long-distance transmission of the signal line and improve signal integrity, thereby ensuring stable data transmission between the BMC and the CPU.
[0066] By adding a resistance near the signal branching point on the mainboard, the technical problem of low stability of the device caused by the decrease in ESPI signal quality, serious signal reflection and backhook phenomenon due to the increase in signal line length exceeding the length limit specified in the ESPI protocol when the management board is modularly designed (such as moving the BMC from the mainboard to other board cards), which affects the stability and accuracy of data transmission between the CPU and the BMC, is solved, and the technical effect of improving the stability of the device is achieved.
[0067] As an optional embodiment, the length of the signal line between the resistance and the baseboard management controller is less than or equal to the fourth length.
[0068] It should be noted that the fourth length is a specific length limit, which refers to the maximum allowed length of the signal line between the resistor and the BMC. For example, the fourth length can be but is not limited to 10 inches, which means that the length of the signal line between the resistor and the BMC cannot exceed 10 inches, so as to still be able to optimize the signal quality by increasing the series resistance when the length of the signal line is increased to be too long (such as exceeding 7 inches as specified in the conventional ESPI protocol).
[0069] Optionally, the length of the signal line between the resistor and the BMC needs to be controlled within a certain range to ensure that the signal quality is not affected by the increase in the length of the signal line. By limiting the length, the reflection and attenuation in the process of signal transmission can be reduced, and the signal integrity can be maintained.
[0070] By adopting the embodiment of the utility model, the length of the signal line between the resistor and the BMC is limited, which helps to maintain the quality of signal transmission when the BMC is migrated from the mainboard to the management board, avoids signal reflection and distortion caused by the increase in the length of the signal line, ensures that the signal quality is still optimized even in the case of long-distance signal transmission, and improves the flexibility of modular design and the reliability of signal transmission.
[0071] As an optional embodiment, the signal branching point is a branching point of an embedded serial presence interface signal.
[0072] Optionally, in the signal transmission path, the signal branching point is a point at which the signal line is split into multiple transmission paths. In this embodiment, the signal branching point is a branching point of an ESPI signal line. The embedded serial presence interface (ESPI) is a low-speed interface standard, which is used for communication between devices on the mainboard, and replaces the traditional LPC (Low Pin Count) interface to provide higher speed and better signal quality.
[0073] As an optional embodiment, the signal line between the baseboard management controller and the resistor is an embedded serial presence interface signal line.
[0074] As an optional embodiment, the resistance value of the resistor is matched with the characteristic impedance of the target signal line, and the target signal line is a signal line between the central microprocessor and the baseboard management controller.
[0075] It should be noted that the above characteristic impedance includes the impedance attribute of the signal line or transmission line when transmitting a signal in an ideal state, and is an important parameter of signal line design, which directly affects the quality of signal transmission.
[0076] Further, the target signal line refers to the part of the ESPI (Embedded Serial Presence Interface) signal line that transmits signals between the CPU and the BMC.
[0077] As an optional example, the present embodiment can be exemplarily explained by the following example, but is not limited thereto:
[0078] Suppose in a server motherboard design, the CPU communicates with the BMC through the ESPI signal line. With the transformation of the motherboard design towards miniaturization and modularization, the BMC is moved to a separate management board, resulting in an increase in the length of the signal line between the CPU and the BMC to 10 inches, exceeding the standard limit of 7 inches. With the increase in the length of the signal line, signal reflection becomes a serious problem, which can cause a significant decrease in signal quality and affect the accuracy of the CPU reading data from the BMC.
[0079] To solve this problem, a resistor is added near the branching point of the signal line, i.e., the place where the signal line branches off, one way to the CPLD and the other way to the BMC. For example, the resistance of this resistor can be set to 50 ohms, because the characteristic impedance of the ESPI signal line is generally around 50 ohms. By matching the resistance of the resistor to the characteristic impedance of the target signal line, the reflection of the signal generated during long-distance transmission can be effectively absorbed, thereby significantly improving the signal quality, eliminating or reducing the signal loopback phenomenon, and ensuring the accurate transmission of data.
[0080] In practical applications, the resistance of the resistor can be fine-tuned according to the actual test results of different signal lines to ensure the best signal quality. For example, if the test finds that signal reflection still exists, the resistance of the resistor may need to be adjusted to 45 ohms or 55 ohms until the optimal resistance is found. In this way, even if the length of the signal line reaches 10 inches or even longer, the integrity of the signal can be maintained, allowing the CPU to correctly read the data sent by the BMC, thereby ensuring the stable operation of the entire system of the server.
[0081] By adding a resistor with a matching characteristic impedance near the branching point of the ESPI signal line between the CPU and the BMC, the present utility model effectively solves the problem of signal quality caused by long-distance signal transmission without significantly increasing the cost, provides key technical support for the miniaturization and modularization design of servers, and improves the reliability and stability of the system.
[0082] The utility model discloses, through the resistance value of matching resistance and the characteristic impedance of signal line, reduced the reflection of signal at signal line end or branch point, improved the integrity of signal, improved the efficiency and stability of signal transmission, this is especially important for ESPI signal line because the characteristic impedance of ESPI signal line is one of the key factors of signal quality.
Claims
1. A motherboard, characterized in that: The mainboard includes a central microprocessor, a programmable logic device, a signal branch point and a resistor. The central microprocessor, the programmable logic device and the resistor are respectively connected to the signal branch point. The resistor is used to connect the signal branch point and the baseboard management controller on the management board.
2. The motherboard according to claim 1, wherein: The length of the signal line between the resistor and the signal branch point is less than or equal to a first length.
3. The motherboard according to claim 1, wherein: The length of the signal line between the central microprocessor and the signal branch point is less than or equal to the second length.
4. The mainboard according to claim 1, wherein: The length of the signal line between the programmable logic device and the signal branch point is less than or equal to a third length.
5. The motherboard according to any one of claims 1 to 4, characterized in that: The signal branch point is a bifurcation point of the embedded serial presence interface signal.
6. The motherboard according to any one of claims 1 to 4, characterized in that: The signal line between the central microprocessor and the signal branch point is an embedded serial field interface signal line, the signal line between the programmable logic device and the signal branch point is an embedded serial field interface signal line, and the signal line between the resistor and the signal branch point is an embedded serial field interface signal line.
7. A motherboard management device, characterized in that: include: Main board, management board, wherein the main board includes a central microprocessor, a programmable logic device, a signal branch point and a resistor, the central microprocessor, the programmable logic device and the resistor are respectively connected to the signal branch point, and the management board includes a baseboard management controller, and the baseboard management controller is connected to the signal branch point through the resistor.
8. The motherboard management device according to claim 7, characterized in that: A length of a signal line between the resistor and the baseboard management controller is less than or equal to a fourth length.
9. The motherboard management device according to any one of claims 7 to 8, characterized in that: The signal branch point is a bifurcation point of the embedded serial presence interface signal.
10. The motherboard management device according to any one of claims 7 to 8, characterized in that: The signal line between the baseboard management controller and the resistor is an embedded serial presence interface signal line.