OTP layout structure with high stability
By optimizing the OTP layout structure and using an isolation ground ring and high-precision component matching, the problems of large chip area and poor anti-interference ability were solved, achieving high-precision real-time temperature monitoring and improved stability, while reducing production costs.
Patent Information
- Application Number
- CN202421769492.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-25
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-07-25
AI Technical Summary
Existing OTP layout structures have large chip areas and poor anti-interference capabilities, resulting in high chip production costs and affecting module accuracy and performance.
Employing a compact layout design, using isolation ground rings and high-precision component matching, adding shielding rings to reduce parasitic resistance and capacitance interference, and combining 5V CMOS, VNPN transistors, poly resistors and NW capacitors into an integrated circuit, the component layout and connections are optimized.
It achieves high-precision real-time temperature monitoring, improves chip stability and reliability, extends device life, reduces chip area, and lowers production costs.
Smart Images
Figure CN223452331U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electrical element technical field, concretely relates to a high stability OTP layout structure. BACKGROUND
[0002] With the development of integrated circuits, the integration of chips is higher and higher, and the energy density is also larger and larger, and the energy consumption will cause the temperature of the chip to rise, causing thermal breakdown of the PN junction, thereby causing irreversible damage to the chip.
[0003] OTP refers to over temperature protection. The over temperature protection circuit can monitor the internal temperature of the chip in real time, and will automatically shut down the chip when the temperature exceeds a certain threshold, preventing large-area damage to the chip due to excessive temperature.
[0004] The existing OTP circuit layout technical scheme has the following disadvantages:
[0005] 1. The layout structure is complex, the chip area is large, and the chip production cost is increased.
[0006] 2. The internal components have low matching degree, the isolation and shielding are not perfect, the anti-interference ability is weak, and the precision and performance of the module are affected. SUMMARY
[0007] The utility model discloses to solve the OTP layout chip area is big, and the anti-interference ability is poor, provides a kind of high stability OTP layout structure, and the utility model discloses over temperature protection not only precision is high, realizes real-time temperature monitoring, improves the reliability and stability of chip itself, prolongs the service life of component, based on integrated technology, in module scheme, follow compact structure, important component is strictly matched, increase shielding ring, guarantee enough substrate contact, reduce parasitic resistance and parasitic capacitance and generate interference, reduce chip area, save chip manufacturing cost.
[0008] The utility model provides a kind of high stability OTP layout structure, including isolated ground ring and the power line VDD, ground line GND being connected in isolated ground ring inside, triode area being connected in isolated ground ring inside left side, capacitor area, first COMS tube area, second COMS tube area, voltage dividing resistor area and digital area being connected in first COMS tube area, second COMS tube area right side are arranged in order from top to bottom and are connected in triode area right side, capacitor area, first COMS tube area, second COMS tube area, voltage dividing resistor area and digital area are all located in isolated ground ring inside;
[0009] Triode area includes 2 rows 1 column triode Q0, Q1 arranged in common isolated ring;
[0010] Capacitor area includes capacitor C0.
[0011] The first COMS tube region comprises current mirror matching and is arranged as P-type 5V COMS tubes M11 and M12 in one row and four columns;
[0012] The second COMS tube region comprises current mirror matching and is arranged as N-type 5V COMS tubes M3 and M4 in one row and three columns;
[0013] The voltage division resistor region comprises common centroid matching and is arranged in a single row in sequence with voltage division resistors R5, R0, R1, R2 and R3 and a resistor R4 located at the left end of the resistor R5;
[0014] The resistors R4, R5, R0, R1, R2 and R3, the triode Q0 and the NMOS tube M2 form a temperature sensor circuit, one end of the resistor R4 inputs a reference voltage V REF ; the PMOS tubes M11 and M12, the NMOS tubes M3 and M4 and the triode Q1 form a comparison unit circuit; the PMOS tubes M14 and M18 in the digital region, the NMOS tubes M5 and M7, the PMOS tube M13, the NMOS tube M6 and the capacitor C0 form an inverter circuit; the PMOS tubes M16, M15 and M17 and the 5V NMOS tubes M8, M9 and M10 in the digital region form a Schmitt trigger; the inverters I1 and I6 in the digital region form a hysteresis control unit circuit; the input end of the inverter I1 is an enable end, and the output end of the inverter I6 is an output end of the OTP layout structure;
[0015] The temperature sensor circuit, the comparison unit circuit, the inverter circuit, the Schmitt trigger and the hysteresis control unit circuit are sequentially electrically connected, the inverter circuit is electrically connected with the inverter I1, and the Schmitt trigger is electrically connected with the temperature sensor circuit and the inverter I6.
[0016] The OTP layout structure with high stability, as a preferred mode, the triode region, the capacitor region, the first COMS tube region, the second COMS tube region, the voltage division resistor region and the digital region share an isolated ground ring with PW;
[0017] The triode region is connected with the capacitor region, the first COMS tube region, the second COMS tube region, the voltage dividing resistor region and the digital region through Metal2 and Metal3, the capacitor region is connected with the triode region and the digital region through Metal2 and Metal3, the first COMS tube region is connected with the triode region, the second COMS tube region and the digital region through Metal2 and Metal3, the second COMS tube region is connected with the triode region, the first COMS tube region and the digital region through Metal2 and Metal3, the voltage dividing resistor region is connected with the triode region and the digital region through Metal2 and Metal3, and the digital region is connected with the triode region, the capacitor region, the first COMS tube region, the second COMS tube region and the voltage dividing resistor region through Metal2 and Metal3.
[0018] The OTP layout structure with high stability, as a preferred mode, the Metal1, Metal2 and Metal3 metal line width is three-hole width.
[0019] The OTP layout structure with high stability, as a preferred mode, the triode Q0 and Q1 are both vnpn triodes and are both double-hole ground rings as isolation rings.
[0020] The OTP layout structure with high stability, as a preferred mode, the COMS tubes M11 and M12 are connected with the same type minimum channel length dum tubes at left and right ends and are double-hole power rings as substrate rings and isolation rings.
[0021] The COMS tubes M3 and M4 are connected with the same type minimum channel length dum tubes at left and right ends and are double-hole ground rings as substrate rings and isolation rings.
[0022] The OTP layout structure with high stability, as a preferred mode, the voltage dividing resistor region is connected with one same type and size dum resistor at each side.
[0023] The OTP layout structure with high stability, as a preferred mode, the line width of the power line VDD and the ground line GND is 3um.
[0024] The utility model discloses a high stability's OTP layout structure, as preferred mode, digital area includes the pipe M2 that the drain electrode is connected between resistance R2, R3, the source electrode ground and the grid pole is connected with pipe M17 grid pole, pipe M10 grid pole, inverter I6 input all, the pipe M2 that the grid pole is connected with inverter I1 output, the source electrode ground and the drain electrode is connected between pipe M12 drain electrode, pipe M13 grid pole of pipe M5, the source electrode connects power line VDD, the grid pole connects pipe M6 grid pole, and the drain electrode is connected with pipe M13 of pipe M13, the source electrode ground of pipe M6, the source electrode connects power line VDD, and the grid pole is connected with pipe M18, pipe M7 grid pole all, and the drain electrode is connected with pipe M14 of pipe M14 source electrode, and the drain electrode is connected with pipe M18 of pipe M18, and the source electrode ground, and the grid pole is connected with pipe M18 grid pole, pipe M14 grid pole, pipe M13 drain electrode, pipe M6 drain electrode all of pipe M7, the source electrode connects power line VDD, and the grid pole is connected with pipe M15, pipe M8, pipe M9 grid pole all, and the drain electrode is connected with pipe M5 source electrode, pipe M17 source electrode all of pipe M16, and the drain electrode is connected with pipe M17 grid pole, pipe M10 grid pole, pipe M8 drain electrode all of pipe M15, and the source electrode is connected with pipe M9 drain electrode, pipe M10 source electrode all of pipe M8, and the source electrode ground and the grid pole is connected with pipe M8 grid pole of pipe M9,
[0025] Capacitor C0 one end ground, the other end is connected between pipe M18 drain electrode and pipe M15 grid pole, pipe M17 drain electrode connects VSS, and the grid pole is connected with pipe M10 grid pole, pipe M10 source electrode is connected between pipe M8 source electrode and pipe M9 drain electrode, and the drain electrode connects VDD.
[0026] The utility model discloses a high stability's OTP layout structure, as preferred mode, the grid pole of three stage pipe Q0 is connected with resistance R4 one end, the drain electrode connects power line VDD, and the source electrode is connected with resistance R5, and resistance R4 other end connects reference voltage V REF ; The grid pole of three stage pipe Q1 is connected between resistance R1, R2, and the drain electrode connects pipe M11 drain electrode and grid pole, and the source electrode ground, resistance R5, R0, R1, R2, R3 are connected in series, and the other end of resistance R3 is grounded, and the both ends of resistance R5 are interconnected,
[0027] The grid pole of pipe M11 is connected with pipe M12 grid pole, and the source electrode connects power line VDD, and the drain electrode is connected with pipe M1 drain electrode after being connected with the grid pole, pipe M12 source electrode connects power line VDD, and the grid pole connects pipe M4 drain electrode, pipe M5 drain electrode, pipe M13 grid pole, pipe M6 grid pole,
[0028] The grid pole of pipe M3 is connected with pipe M4 grid pole, and the source electrode ground, and the drain electrode is connected with pipe M1 after being connected with the grid pole, and connects IBN, pipe M4 source electrode ground, inverter I1 input end connects enable end, and the output end connects pipe M5 grid pole.
[0029] The utility model provides a brand -new by 5V CMOS, vnpn triode, poly resistance, NW capacitor and digital logic circuit combined integrated circuit layout technical scheme scheme, has following several points advantages:
[0030] (1) the layout signal is reasonably planned, and component layout is compact, so that the chip area utilization rate is improved.
[0031] (2) according to the rule in the layout technical scheme, internal component current mirror, differential pair, matching resistance and the like are matched with high precision, ensure the consistency of surrounding environment, increase the isolation protection ring in the periphery, increase its strong anti-interference ability, improve its precision and performance.
[0032] The layout is according to the following contents:
[0033] 1. The overall internal component layout is compact, and the layout of the layout structure (current mirror, differential pair, voltage division sampling resistance and the like) needing to be matched is preferentially arranged, then the remaining components are arranged, and finally the digital logic part is arranged.
[0034] 2. about the layout of 5V CMOS tube:
[0035] (1) MOS tube is provided with substrate ring and isolation ground ring, which can greatly increase the chip area. In the technical scheme, the PMOS tubes of the same type and substrate potential share the NW double-hole substrate ring, and the NMOS tubes of the same type and substrate potential share the PW double-hole substrate ring, so that the same potential well is shared.
[0036] (2) the MOS device needs high-precision matching in the current mirror, differential pair and the like, and the current direction should be consistent, and the common centroid matching is preferably made to reduce the proportion of the adjustment, so as to ensure the consistency, symmetry, dispersion, compactness and directionality of the matching. The common centroid matching characteristic is superior to the interdigital matching.
[0037] (3) minimum channel length dummy devices dum are added on both sides of the matching MOS tube, so as to keep the consistency of the environment and prevent over-etching of the polysilicon.
[0038] (4) the substrate is made into a double-hole ring, which not only ensures that the internal device has sufficient substrate contact, prevents latch-up effect and reduces parasitic resistance, but also effectively plays an isolation role with the outside.
[0039] (5) the source and drain of the MOS tube can be reasonably combined to save the chip area.
[0040] 3. For the voltage division resistance part, the matching devices are matched in interdigital or common centroid, and the same type dummy devices are added on both sides as dum to keep the consistency of the environment and prevent over-etching of the polysilicon.
[0041] 4. Do not route traces on analog circuit devices that require high-precision matching to avoid parasitic resistance.
[0042] The utility model has the following advantages:
[0043] The over-temperature protection of this utility model is not only highly accurate and realizes real-time temperature monitoring, but also improves the reliability and stability of the chip itself and extends the service life of the device. Based on integrated process technology, the module solution follows the principles of compact structure, strict matching of important components, and the addition of shielding rings to ensure sufficient substrate contact, reduce interference caused by parasitic resistance and parasitic capacitance, reduce chip area, and save chip manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 This is a circuit diagram of an OTP layout structure with high stability;
[0045] Figure 2 A schematic diagram of the regional structure of an OTP layout structure with high stability;
[0046] Figure 3 It is a layout with a highly stable OTP layout structure;
[0047] Figure 4 It is a digital area layout with a highly stable OTP layout structure.
[0048] Reference numerals:
[0049] 110, transistor area; 120, capacitor area; 130, first COMS tube area; 140, second COMS tube area; 150, voltage divider resistor area; 160, digital area. DETAILED DESCRIPTION
[0050] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.
[0051] Example 1
[0052] like Figures 1 to 4 As shown, a highly stable OTP layout structure is based on Foundry's process manufacturing related files and Figure 1 The circuit is a combination of 5VCMOS tube, vnpn transistor, poly resistor, NW capacitor and digital logic circuit. The circuit structure diagram is as follows Figure 1 As shown in the figure, this OTP circuit is divided into three parts: temperature sensor, comparison unit, and hysteresis control unit.
[0053] like Figure 1As shown, V be With the increase of temperature, the current flowing through M12 increases with the increase of temperature, and when the current of M12 is greater than the current flowing through M4, the OTP outputs high level, triggering the over-temperature protection.
[0054] The simulation verification based on the HG0.35um BCD process in the technical solution in the technical solution is carried out, and the results are as follows:
[0055]
[0056] The layout of the utility model is as Figures 2 to 4 shown.
[0057] The detailed contents of the technical solution are as follows:
[0058] 1. As Figure 3 shown, a circle of isolation ground rings with PW is added to the outermost part of the overall layout of the module.
[0059] 2. As Figure 3 shown, the line width of the two bus lines (power line VDD and ground line GND) is 3um, which ensures the overcurrent capacity.
[0060] 3. As Figure 3 shown, in the 110 area, two transistors Q0 and Q1 are arranged in 2 rows and 1 column by the isolation ring layout, and the double-hole ground ring is used as the isolation ring.
[0061] 4. As Figure 3 shown, in the 120 area, there is a capacitor C0.
[0062] 5. As Figure 3 shown, in the 130 area, P-type 5V COMS tubes (M11 and M12) are matched by current mirrors, arranged in 1 row and 4 columns, and dum tubes with the same type and minimum channel length are added to the left and right ends, and the double-hole power ring is used as the substrate ring and the isolation ring.
[0063] 6. As Figure 3 shown, in the 140 area, N-type 5V COMS tubes (M3 and M4) are matched by current mirrors, arranged in 1 row and 3 columns, and dum tubes with the same type and minimum channel length are added to the left and right ends, and the double-hole ground ring is used as the substrate ring and the isolation ring.
[0064] 7. As Figure 3 shown, in the 150 area, the voltage dividing resistors (R0, R1, R2, R3 and R5) are arranged for common centroid matching, arranged in a single row, R4 is placed at the left end, and a dum resistor with the same type and size is added to each side.
[0065] 8. As Figure 3 shown, in the 160 area, it is a digital part layout.
[0066] poly resistors R4, R5, R0, R1, R2, R3, vnpn transistor Q0, and 5V NMOS M2 form a temperature sensor circuit; 5V PMOS M11, M12, 5V NMOS M3, M4, and vnpn transistor Q1 form a comparison unit circuit; 5V PMOS M14, M18, 5V NMOS M5, M7, NW capacitor C0, 5V PMOS M13, and 5V NMOS M6 form an inverter; 5V PMOS M16, M15, M17 and 5V NMOS M8, M9, M10 form a Schmitt trigger; and the digital logic circuit, i.e., inverters I1, I6, jointly form a hysteresis control unit circuit.
[0067] The temperature sensor circuit is connected to the comparison unit circuit and the hysteresis control unit circuit.
[0068] V be As the temperature increases, the current flowing through M12 increases, and when the current flowing through M12 is greater than the current flowing through M4, the OTP outputs a high level, triggering the over-temperature protection.
[0069] V REF The range of VDD is 1.2V-1.225V.
[0070] The digital logic circuit part is an important component of the hysteresis control unit circuit, and thus realizes the OTP function.
[0071] 110, 120, 130, 140, 150, 160 regions share an isolated ground ring. The 110 region is connected to the 120, 130, 140, 150, and 160 regions through Metal2 and Metal3, the 120 region is connected to the 110 and 160 regions through Metal2 and Metal3, the 130 region is connected to the 110, 140, and 160 regions through Metal2 and Metal3, the 140 region is connected to the 110, 130, and 160 regions through Metal2 and Metal3, the 150 region is connected to the 110 and 160 regions through Metal2 and Metal3, and the 160 region is connected to the 110, 120, 130, 140, and 150 regions through Metal2 and Metal3.
[0072] In the embodiment, the Metal1, Metal2, and Metal3 metal line width is 0.85um, i.e., single-hole width; the parallel metal trace spacing is 0.6um; the substrate ring Active layer is 1.7um, i.e., double-hole width; the Active layer between the two MOS transistors on the same substrate is 0.8um, i.e., minimum spacing; the MOS transistor Active layer to the substrate ring Active layer is 0.8um, i.e., minimum spacing; and the RIDH layer between the two resistors is 0.96um, i.e., minimum spacing.
[0073] The above merely describes a preferred embodiment of the present application, but the protection scope of the present application is not limited thereto, any skilled person in the art, according to the technical scheme and the inventive concept of the present application, makes equivalent replacement or change within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.
Claims
1. A highly stable OTP layout structure, characterized by: The invention comprises an isolation ground ring, a power line VDD and a ground line GND connected to the isolation ground ring, a transistor area (110) connected to the left side of the isolation ground ring, a capacitor area (120), a first CMOS transistor area (130), a second CMOS transistor area (140), a voltage divider resistor area (150) connected to the right side of the transistor area (110) and arranged in sequence from top to bottom, and a digital area (160) connected to the right side of the first CMOS transistor area (130) and the second CMOS transistor area (140), wherein the digital area (160) is located between the capacitor area (120) and the voltage divider resistor area (150), and the capacitor area (120), the first CMOS transistor area (130), the second CMOS transistor area (140), the voltage divider resistor area (150) and the digital area (160) are all located inside the isolation ground ring; The transistor region (110) includes transistors Q0 and Q1 arranged in two rows and one column with a common isolation ring; The capacitor region (120) includes a capacitor C0; The first COMS tube area (130) includes current mirror matching and is arranged in 1 row and 4 columns of P-type 5V COMS tubes M11 and M12; The second COMS tube area (140) includes current mirror matching and is arranged in 1 row and 3 columns of N-type 5V COMS tubes M3 and M4; The voltage-dividing resistor area (150) includes voltage-dividing resistors R5, R0, R1, R2, R3 that are matched with a common centroid and arranged in sequence in a single row, and a resistor R4 located at the left end of the resistor R5; Resistors R4, R5, R0, R1, R2, R3, transistor Q0 and NMOS tube M2 form a temperature sensor circuit. One end of resistor R4 inputs the reference voltage V REF The PMOS tubes M11 and M12, the NMOS tubes M3 and M4, and the triode Q1 constitute a comparison unit circuit; the PMOS tubes M14 and M18, the NMOS tubes M5 and M7, the PMOS tube M13, the NMOS tube M6, and the capacitor C0 of the digital area (160) constitute an inverter circuit; the PMOS tubes M16, M15, M17 and the 5V NMOS tubes M8, M9, and M10 of the digital area (160) constitute a Schmitt trigger; the inverters I1 and I6 of the digital area (160) constitute a hysteresis control unit circuit; the input end of the inverter I1 is an enable end, and the output end of the inverter I6 is an output end of the OTP layout structure; The temperature sensor circuit, the comparison unit circuit, the inverter circuit, the Schmitt trigger, and the hysteresis control unit circuit are electrically connected in sequence. The inverter circuit is electrically connected to the inverter I1, and the Schmitt trigger is electrically connected to the temperature sensor circuit and the inverter I6.
2. The OTP layout structure with high stability according to claim 1, wherein: The triode region (110), the capacitor region (120), the first CMOS region (130), the second CMOS region (140), the voltage divider resistor region (150), and the digital region (160) share an isolated ground ring with PW; The triode region (110) is connected to the capacitor region (120), the first COMS region (130), the second COMS region (140), the voltage divider resistor region (150) and the digital region (160) through Metal2 and Metal3; the capacitor region (120) is connected to the triode region (110) and the digital region (160) through Metal2 and Metal3; the first COMS region (130) is connected to the triode region (110), the second COMS region (140) and the digital region (160) through Metal2 and Metal3; The second COMS tube area (140) is connected to the triode area (110), the first COMS tube area (130), and the digital area (160) through Metal2 and Metal3; the voltage divider resistor area (150) is connected to the triode area (110) and the digital area (160) through Metal2 and Metal3; and the digital area (160) is connected to the triode area (110), the capacitor area (120), the first COMS tube area (130), the second COMS tube area (140), and the voltage divider resistor area (150) through Metal2 and Metal3.
3. The OTP layout structure with high stability according to claim 2, wherein: The metal line widths of Metal1, Metal2, and Metal3 are three hole widths.
4. The OTP layout structure with high stability according to claim 1, wherein: Transistors Q0 and Q1 are both vnpn transistors and both use double-hole ground rings as isolation rings.
5. The OTP layout structure with high stability according to claim 1, wherein: The left and right ends of COMS tubes M11 and M12 are connected to dum tubes of the same type with the smallest channel length and a double-hole power ring is used as the substrate ring and isolation ring; Dum tube double-hole ground rings of the same type with the minimum channel length are added to the left and right ends of the COMS tubes M3 and M4 as substrate rings and isolation rings.
6. The OTP layout structure with high stability according to claim 1, wherein: Two dum resistors of the same type and size are connected to each side of the voltage dividing resistor area (150).
7. The OTP layout structure with high stability according to claim 1, characterized in that: The line width of the power line VDD and the ground line GND is 3um.
8. The OTP layout structure with high stability according to claim 1, characterized in that: The digital area (160) includes a tube M2 whose drain is connected between resistors R2 and R3, whose source is grounded, and whose gate is connected to the gate of tube M17, the gate of tube M10, and the input end of inverter I6; a tube M5 whose gate is connected to the output end of inverter I1, whose source is grounded, and whose drain is connected between the drain of tube M12 and the gate of tube M13; The source is connected to the power line VDD, the gate is connected to the gate of the tube M6, and the drain is connected to the drain of the tube M6; the source of the tube M6 is grounded; The source of the transistor M14 is connected to the power line VDD, the gate is connected to the gates of the transistors M18 and M7, and the drain is connected to the source of the transistor M18; the drain of the transistor M18 is connected to the drain of the transistor M7; the source of the transistor M7 is grounded, and the gate is connected to the gate of the transistor M18, the gate of the transistor M14, the drain of the transistor M13, and the drain of the transistor M6; the source of the transistor M16 is connected to the power line VDD, the gate is connected to the gates of the transistors M15, M8, and M9, and the drain is connected to the source of the transistor M5 and the source of the transistor M17; the drain of the transistor M15 is connected to the gate of the transistor M17, the gate of the transistor M10, and the drain of the transistor M8; the source of the transistor M8 is connected to the drain of the transistor M9 and the source of the transistor M10; the source of the transistor M9 is grounded and connected to the gate of the transistor M8; One end of capacitor C0 is grounded, and the other end is connected between the drain of transistor M18 and the gate of transistor M15; the drain of transistor M17 is connected to VSS, and the gate is connected to the gate of transistor M10; the source of transistor M10 is connected between the source of transistor M8 and the drain of transistor M9, and the drain is connected to VDD.
9. The OTP layout structure with high stability according to claim 1, characterized in that: The gate of transistor Q0 is connected to one end of resistor R4, the drain is connected to the power line VDD, the source is connected to resistor R5, and the other end of resistor R4 is connected to the reference voltage V REF The gate of transistor Q1 is connected between resistors R1 and R2, the drain is connected to the drain and gate of transistor M11, and the source is grounded; resistors R5, R0, R1, R2, and R3 are connected in series, the other end of resistor R3 is grounded, and both ends of resistor R5 are interconnected; The gate of tube M11 is connected to the gate of tube M12, the source is connected to the power line VDD, the drain is connected to the gate and then to the drain of transistor Q1; the source of tube M12 is connected to the power line VDD, and the gate is connected to the drain of tube M4, the drain of tube M5, the gate of tube M13, and the gate of tube M6; The gate of tube M3 is connected to the gate of tube M4, the source is grounded, the drain is connected to the gate and then connected to IBN; the source of tube M4 is grounded; the input end of inverter I1 is connected to the enable end, and the output end is connected to the gate of tube M5.