Universal discrete device MOS and IGBT limit frequency test circuit
By designing a test circuit including a detection unit and a power management module and using PWM signals to adjust the frequency, the economic problem of MOS and IGBT frequency detection is solved, stable and continuously adjustable frequency detection is achieved, and the use of high-end test instruments is avoided.
Patent Information
- Application Number
- CN202422565956.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2034-10-23
AI Technical Summary
The market lacks efficient and economical universal discrete device MOS and IGBT extreme frequency test instruments. In particular, IGBT testing requirements are complex and professional, and existing high-end test instruments are expensive, bringing an economic burden to R&D and production units.
A test circuit including a detection unit, a power input module and a power management module was designed. By using a PWM transmitter chip, a test chip and various components such as resistors and diodes, the frequency of MOS and IGBT can be stably detected and continuously adjusted by adjusting the PWM signal to change the frequency.
It achieves stable detection of MOS and IGBT frequencies, eliminating the need for expensive high-end test instruments and providing a cost-effective and efficient frequency detection solution.
Smart Images
Figure CN223461662U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of circuit component limit frequency test, especially relates to a test circuit of general discrete device MOS and IGBT limit frequency. BACKGROUND
[0002] In the current market, the limit frequency test instrument for general discrete devices such as metal oxide semiconductor field effect transistor (MOS) and insulated gate bipolar transistor (IGBT) is relatively scarce. This phenomenon shows that although these devices play a crucial role in power electronics, automation control and high-frequency application fields, but the test equipment specially designed for measuring their frequency characteristics is not common. It is particularly prominent that for high-performance power semiconductor devices such as IGBT, the test demand is more complex and professional, and the instruments that can provide comprehensive test functions on the market are not only limited in number, but also expensive. These high-end test instruments usually integrate high-precision measurement, dynamic characteristic analysis and complex fault diagnosis and other functions, but due to the high research and development cost and technical threshold, the final product is expensive, which brings not small economic burden to the research and production units. CONTENT OF THE UTILITY MODEL
[0003] The embodiment of the application provides a test circuit of general discrete device MOS and IGBT limit frequency, which is used to solve the technical problem of discrete device MOS and IGBT limit frequency detection.
[0004] The embodiment of the application provides a test circuit of general discrete device MOS and IGBT limit frequency, which is used to solve the technical problem of discrete device MOS and IGBT limit frequency detection.
[0005] The detection unit comprises a PWM transmitting chip, a test chip, resistors R1, R3, R4, RC, RG1, RG2, a diode DC, a TVS diode DG, and a three-stage Darlington tube, a VIN+ pin and a VCC1 pin of the test chip are externally connected with +5V voltage, a VIN- pin of the test chip is externally connected with a PWM signal output pin of the PWM transmitting chip, the VIN- pin of the test chip is externally connected with +5V voltage through the resistor R1, a VE pin of the test chip is externally provided with an output end G through the resistor RG2 and the TVS diode DG in parallel, the VE pin is also directly externally provided with an output end E, a DESAT pin of the test chip is connected with the resistor RC, the resistor RC is sequentially connected with the three-stage Darlington tube and the diode DC, and an output end C is externally provided after the resistor RC, a VCC2 pin and a VC pin of the test chip are connected with the resistor RC through the resistor R3, a VOUT pin of the test chip is connected with the output end G through the resistor RG1, and a VEE pin of the test chip is connected with the output end G through the resistor R4 and the resistor RG1.
[0006] The power input module has a power output end.
[0007] The power management module has an input end electrically connected with the power output end and an output end electrically connected with the test chip.
[0008] The above embodiment has the beneficial effects that the circuit structure is stable, the frequency is adjustable, and the circuit is suitable for general discrete device MOS and IGBT frequency detection, the circuit can change the frequency by changing the size of the PWM, and the general discrete device MOS and IGBT frequency detection can be continuously adjusted, so that some expensive instruments are saved while meeting the general discrete device MOS and IGBT limit frequency detection.
[0009] On the basis of the above embodiment, the embodiment of the application can also be improved as follows:
[0010] In one of the embodiments of the present application: the power input module comprises: a first power chip, a second power chip, a capacitor C8, an inductor L1, a diode D1, a resistor R5, a resistor R6, a capacitor C12, an inductor L2, a diode D2, a resistor R7, a resistor R8, the VIN pin of the first power chip is externally connected to a power supply, the BOOT pin of the first power chip is externally connected to the output port P1 through the capacitor C8 and the inductor L1, the GND pin of the first power chip is grounded, and the resistor R5 and the resistor R6 are connected in series between the output port P1 and the GND pin of the first power chip; the VIN pin of the second power chip is externally connected to a power supply, the BOOT pin of the second power chip is externally connected to the ground through the capacitor C12 and the inductor L2, the GND pin of the second power chip is externally connected to the output port P4, and the resistor R7 and the resistor R8 are connected in series between the output port P4 and the BOOT pin of the second power chip.
[0011] In one of the embodiments of the present application: the power management module comprises: a power management chip, the VIN pin of the power management chip is electrically connected to the output port P1, the GND pin of the power management chip is electrically connected to the output port P2, the Vo- pin of the power management chip is connected to the output terminal G through the resistor R4 and the resistor RG1, the 0V pin of the power management chip is respectively connected to the VE pin of the test chip and the output terminal E, and the Vo+ pin of the power management chip is connected to the resistor RC through the resistor R3. BRIEF DESCRIPTION OF DRAWINGS
[0012] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.
[0013] Figure 1 Circuit diagram of the detection unit and the power management module;
[0014] Figure 2 Circuit diagram of the power input module. DETAILED DESCRIPTION
[0015] In the present application, unless otherwise explicitly specified and limited, the terms in the present application should be understood in a broad sense, which can be directly connected or indirectly connected through an intermediate medium, and if it involves power, electronic equipment, it can also be electrically connected or connected through communication signals. For ordinary skilled persons in the art, the specific meaning of different terms in the present application can be understood according to the specific situation, and the scope of the specific meaning should be limited to the function of the present application.
[0016] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0017] As shown in Figure 1 A universal discrete device MOS and IGBT limit frequency test circuit, comprising: a detection unit, a power input module, a power management module, the detection unit comprising: a PWM transmitting chip, a test chip, a resistor R1, a resistor R3, a resistor R4, a resistor RC, a resistor RG1, a resistor RG2, a diode DC, a TVS diode DG, a three-stage Darlington tube, the VIN+ pin of the test chip, the VCC1 pin are externally connected with +5V voltage, the VIN- pin of the test chip is externally connected with the PWM signal output pin of the PWM transmitting chip, the VIN- pin of the test chip is externally connected with +5V voltage through the resistor R1, the VE pin of the test chip is externally provided with an output end G through the parallel connection of the resistor RG2 and the TVS diode DG, and the VE pin is also directly externally provided with an output end E, the DESAT pin of the test chip is connected with the resistor RC, the three-stage Darlington tube and the diode DC are connected in sequence behind the resistor RC, and the output end C is externally provided behind the diode DC, the VCC2 pin and the VC pin of the test chip are connected with the resistor RC through the resistor R3, the VOUT pin of the test chip is connected with the output end G through the resistor RG1, and the VEE pin of the test chip is connected with the output end G through the resistor R4 and the resistor RG1; the power input module has a power output end; the input end of the power management module is electrically connected with the power output end, and the output end is electrically connected with the test chip, wherein the output end G, the output end E and the output end C form a port inserted into the device under test.
[0018] Specifically, as shown in Figure 1As shown, the detection unit further comprises: a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, the test chip adopts an A316J chip, a resistor R1 is connected in series between the VIN+ pin and the VIN- pin of the test chip, a capacitor C1 is connected in series between the VCC1 pin and the GND1 pin of the test chip, a resistor R2 is connected in series between the VCC1 pin and the FAULT pin, a capacitor C2 is connected in series between the VE pin and the VCC2 pin, the VC pin of the test chip, a capacitor C4 is connected in series between the VCC2 pin, the VC pin and the VEE pin, a capacitor C3 is connected in series between the VE pin and the VEE pin, a capacitor C5 is connected in series between the VE pin and the DESAT pin, a resistor R3 is connected in series between the DESAT pin and the VCC2 pin, the VC pin, a resistor R4 is connected in series between the VOUT pin and the VEE pin.
[0019] Specifically, as shown in the figure, Figure 2 The power input module comprises: a first power chip, a second power chip, a capacitor C8, an inductor L1, a diode D1, a resistor R5, a resistor R6, a capacitor C12, an inductor L2, a diode D2, a resistor R7, a resistor R8, the VIN pin of the first power chip is externally connected to a power supply, the BOOT pin of the first power chip is externally connected to the output port P1 through the capacitor C8 and the inductor L1, the PH pin of the first power chip is connected to the inductor L1, the GND pin of the first power chip is grounded, and the resistor R5 and the resistor R6 are connected in series between the output port P1 and the GND pin of the first power chip; the VIN pin of the second power chip is externally connected to a power supply, the BOOT pin of the second power chip is externally connected to the ground through the capacitor C12 and the inductor L2, the PH pin of the second power chip is connected to the inductor L2, the GND pin of the second power chip is externally connected to the output port P4, and the resistor R7 and the resistor R8 are connected in series between the output port P4 and the BOOT pin of the second power chip.
[0020] Specifically, as shown in the figure, Figure 2 The first power chip and the second power chip adopt TPS5430, and the power input module further comprises: a capacitor C6, a capacitor C7, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, and a capacitor C13. The capacitor C6 and the capacitor C7 are connected in parallel between the VIN pin of the first power chip and the ground, the capacitor C9 and the capacitor C10 are connected in parallel between the output port P1 and the ground, the capacitor C11 is connected in series between the VIN pin of the second power chip and the ground, and the capacitor C12 and the capacitor C13 are connected in parallel between the output port P4 and the ground.
[0021] The working principle of the power input module is as follows: after the input power is output to the two TPS5430 power chips, the voltage stabilizing tube, the freewheeling inductor, and the voltage filter output ±12V voltage respectively.
[0022] Specifically, as shown in the figure,Figure 1 As shown in the figure, the power management module comprises: a power management chip, a VIN pin of the power management chip is electrically connected with the output port P1, a GND pin of the power management chip is electrically connected with the output port P2, a Vo- pin of the power management chip is connected with the output end G through a resistor R4 and a resistor RG1, a 0V pin of the power management chip is respectively connected with a VE pin of the test chip and the output end E, and a Vo+ pin of the power management chip is connected with a resistor RC through a resistor R3.
[0023] Specifically, as shown in the figure, Figure 1 The power management chip adopts QA04, and the power management module further comprises: capacitors E1, E2 and E3, the capacitor E1 is connected in series between the VIN and GND pins of the power management chip, the capacitor E2 is connected in series between the Vo- and 0V pins of the power management chip, and the capacitor E3 is connected in series between the 0V and Vo+ pins of the power management chip.
[0024] The working principle of the power management module is as follows: the port inputs 12V voltage to the QA04 power management chip, the 0V pin outputs 0V reference voltage, the Vo- pin outputs -8.7V, and the Vo+ pin outputs +15V voltage.
[0025] As shown in the figure, the left side is the input end, the input signal is a frequency modulation pulse signal and a power input, the right side is the MOS or IGBT drive voltage output end, and the MOS or IGBT to be tested is installed, and the Vce voltage waveform is detected by an oscilloscope to judge the limit frequency of the MOS or IGBT.
[0026] The universal discrete device MOS and IGBT limit frequency test circuit works as follows: taking IGBT as an example, the IGBT to be tested is inserted into the port formed by the output end G, the output end E and the output end C, +5V voltage is given to the VIN+ pin of the A316J, the PWM signal is given to the VIN- pin of the A316J, the DESAT pin of the A316J does not detect the overcurrent signal, the output high level is given to the output end G, and the VCC2 pin-VE pin=24v, that is, the output forward drive voltage is normal, the VOUT pin of the A316J outputs a high level drive signal, and the FAULT pin of the A316J outputs a low level fault signal to the port. The output end C point is high level, the output end E point is low level to drive the three-stage Darlington tube to be turned on, and the IGBT is also turned on. The input and output signal frequencies are observed by an oscilloscope, so that the speed of the component frequency response is obtained, and the appropriate component is selected for use in the circuit of the appropriate frequency. If the IGBT appears an overcurrent signal (the DESAT pin of the A316J detects that the voltage on the collector of the IGBT = 7V), and the input drive signal continues to be added to the VIN+ pin, the under-voltage signal is low level, the output end E point is low level, and the three-stage Darlington tube is turned off.
[0027] The structure circuit is stable, the frequency is adjustable, is suitable for general discrete device MOS and IGBT frequency detection, changes the frequency size through changing the PWM duty ratio, and further realizes general discrete device MOS and IGBT frequency detection and continuous adjustment, so as to meet the general discrete device MOS and IGBT limit frequency detection, and save some expensive instruments.
[0028] The above is only the embodiment of the utility model, and the common knowledge such as specific structure and characteristics in the scheme is not described too much, the ordinary skilled person in the art knows all the ordinary technical knowledge in the technical field of the utility model before the application date or the priority date, can know all the prior art in the field, and has the ability to apply conventional experimental means before the date, and the ordinary skilled person in the art can improve and implement the scheme under the inspiration given in the application, and some typical known structures or known methods should not become the obstacle for the ordinary skilled person in the art to implement the application. It should be pointed out that, for the person skilled in the art, without departing from the structure of the utility model, a number of modifications and improvements can be made, which should also be considered as the protection scope of the utility model, and these will not affect the effect and practicality of the utility model.
Claims
1. A test circuit for general discrete device MOS and IGBT limit frequency, characterized in that, The detection unit comprises: a PWM transmitting chip, a test chip, resistors R1, R3, R4, RC, RG1, RG2, a diode DC, a TVS diode DG, and a three-stage Darlington tube; a VIN+ pin, a VCC1 pin of the test chip are externally connected with a +5V voltage; a VIN- pin of the test chip is externally connected with a PWM signal output pin of the PWM transmitting chip; the VIN- pin of the test chip is externally connected with a +5V voltage through the resistor R1; a VE pin of the test chip is externally provided with an output end G through the resistor RG2 and the TVS diode DG in parallel; the VE pin is also directly externally provided with an output end E; a DESAT pin of the test chip is connected with the resistor RC; the resistor RC is sequentially connected with the three-stage Darlington tube and the diode DC, and an output end C is externally provided after the resistor RC; a VCC2 pin, a VC pin of the test chip are connected with the resistor RC through the resistor R3; a VOUT pin of the test chip is connected with the output end G through the resistor RG1; a VEE pin of the test chip is connected with the output end G through the resistor R4 and the resistor RG1. The power input module has a power output end. The power management module is electrically connected with the power output end at the input end and is electrically connected with the test chip at the output end. The power input module comprises: a first power chip, a second power chip, a capacitor C8, an inductor L1, a diode D1, resistors R5, R6, a capacitor C12, an inductor L2, a diode D2, resistors R7, R8, a VIN pin of the first power chip is externally connected with a power supply, a BOOT pin of the first power chip is externally provided with an output port P1 after passing through the capacitor C8 and the inductor L1, a GND pin of the first power chip is grounded, and the resistor R5 and the resistor R6 are connected in series between the output port P1 and the GND pin of the first power chip; a VIN pin of the second power chip is externally connected with a power supply, a BOOT pin of the second power chip is grounded after passing through the capacitor C12 and the inductor L2, a GND of the second power chip is externally provided with an output port P4, and the resistor R7 and the resistor R8 are connected in series between the output port P4 and the BOOT pin of the second power chip.
2. The test circuit of claim 1, wherein, The power management module comprises: a power management chip, a VIN pin of the power management chip is electrically connected with the output port P1, a GND pin of the power management chip is electrically connected with the output port P2, a Vo- pin of the power management chip is connected with the output end G through the resistor R4 and the resistor RG1, a 0V pin of the power management chip is respectively connected with the VE pin of the test chip and the output end E, and a Vo+ pin of the power management chip is connected with the resistor RC through the resistor R3.
3. The test circuit of claim 2, wherein,