Chip and electronic equipment
By designing planar pins for contact connection with the PCB surface, the problem of point contact between the existing chip and the PCB limiting the conduction area is solved, achieving chip connection with a larger conduction area, lower thickness and higher reliability.
Patent Information
- Application Number
- CN202422535808.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2034-10-18
AI Technical Summary
The existing chip and PCB board are connected through solder ball point contact, which limits the conductive area and makes the connection inconvenient.
The first side of the pin is designed to be flush with or protruding from the chip body, and is arranged in a planar shape. It is connected to the PCB board using surface contact. The pins are made of different materials to improve reliability and heat dissipation capabilities.
The conductive area between the chip and the PCB is increased, the overall thickness of the chip is reduced, the impact resistance and heat dissipation capabilities are improved, and the reliability is enhanced.
Smart Images
Figure CN223462223U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the utility model relates to the field of semiconductor, especially a chip and electronic equipment. BACKGROUND
[0002] Chip plays a vital role in modern society, and its role is extensive and in-depth, covering data processing, storage, control, communication, sensing and other aspects. There are various packaging methods for chips, such as BGA packaging, WLCSP packaging, LGA packaging, etc. Among them, the pins of the chip made by adopting BGA packaging method and WLCSP packaging method are usually solder balls, which contact with the PCB board to realize the communication connection between the chip and the PCB board. However, the solder balls contact with the PCB board through point contact, which limits the conductive area, thereby causing inconvenience. SUMMARY
[0003] In order to solve the above technical problems, the embodiment of the utility model provides a chip and electronic equipment which can increase the conduction area.
[0004] The embodiment of the utility model solves its technical problems by adopting the following technical scheme:
[0005] A chip, comprising a chip main body and a plurality of pins, the plurality of pins are connected to a first surface of the chip main body and are arrayed on the first surface, wherein a first surface of the pin is flush with or protrudes from the first surface of the chip main body, and the first surface is arranged in a planar shape.
[0006] In some embodiments, the pins are made of tin, gold, nickel gold or nickel palladium gold.
[0007] In some embodiments, the pins protrude from the first surface, and the pins comprise a first conductive part and a second conductive part connected to each other, one end of the first conductive part is connected to the chip main body, and the other end of the first conductive part is connected to the second conductive part.
[0008] In some embodiments, the melting point of the first conductive part is higher than that of the second conductive part.
[0009] In some embodiments, the first conductive part is made of metal copper, and the second conductive part is made of tin, tin silver, nickel tin silver, gold, nickel gold or nickel palladium gold.
[0010] In some embodiments, as viewed in a direction perpendicular to the first surface, the shape of the projection of the pin comprises a square, an oval or a circle.
[0011] In some embodiments, the size of the pin protruding from the first surface is d, which satisfies 60 μm≤d≤150 μm.
[0012] In some embodiments, the plurality of pins are divided into series pins and parallel pins, the series pins and the parallel pins are arranged at intervals, the series pins are used for connecting a plurality of connection points of a circuit board of the chip body in series, and the parallel pins are used for connecting a plurality of connection points of the circuit board of the chip body in parallel.
[0013] In some embodiments, the chip body comprises a package shell, a core and a circuit board, the core is connected with the circuit board, the package shell covers the core and the circuit board, and the plurality of pins are connected with the circuit board.
[0014] The embodiment of the utility model solves its technical problem still adopts following technical scheme:
[0015] An electronic device comprises the chip.
[0016] The chip provided by the embodiment of the application has the following beneficial effects: the chip comprises a chip body and a plurality of pins, the plurality of pins are connected to a first surface of the chip body and are arranged in an array on the first surface, wherein the first surface of the pin is flush with the first surface of the chip body or protrudes from the first surface, and the first surface is arranged in a planar manner. In this way, when the chip with the structure is connected to a PCB, the first surface of the pin is arranged in a planar manner, the pin and the PCB are connected in a surface contact manner, compared with the scheme in which the pin is designed as a solder ball and connected to the PCB in a point contact manner, the surface contact manner is conducive to increasing the area of conduction. BRIEF DESCRIPTION OF DRAWINGS
[0017] One or more embodiments are exemplarily illustrated by pictures in the drawings corresponding to the embodiments, and the exemplarily illustrations do not constitute a limitation on the embodiments, elements with the same reference numerals in the drawings represent similar elements, unless otherwise specified, and the drawings do not constitute a proportional limitation.
[0018] Figure 1 is a structural schematic view of the chip of one embodiment of the application;
[0019] Figure 2 is a side view of Figure 1 ;
[0020] Figure 3 is a structural schematic view of the chip of another embodiment of the application;
[0021] Figure 4 is a side view of Figure 3 ;
[0022] Figure 5 is a structural schematic view of the chip of another embodiment of the application;
[0023] Figure 6 is a side view of Figure 5
[0024] Figure 7 is a top view of a chip according to one embodiment of the present application;
[0025] Figure 8 is a sectional view of a chip according to one embodiment of the present application;
[0026] In the figure: 1, chip; 2, pin; 3, chip body;
[0027] 21, first conductive part; 22, second conductive part; 21a, series pin; 21b, parallel pin; 31, package shell; 32, core; 33, circuit board; 201, first face; 301, first surface. DETAILED DESCRIPTION
[0028] For the purpose of facilitating the understanding of the present application, the present application will be described in more detail below in conjunction with the drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element or one or more intervening elements can be present therebetween. When an element is described as being "connected to" another element, it can be directly connected to the other element or one or more intervening elements can be present therebetween. The terms "upper", "lower", "inner", "outer", "vertical", "horizontal", and the like as used in the present specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are merely for the purpose of facilitating the description of the present application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and the like are merely for the purpose of description and cannot be understood as indicating or implying relative importance.
[0029] Unless otherwise defined, all technical and scientific terms used in the present specification have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used in the present specification includes any and all combinations of one or more related listed items.
[0030] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0031] As Figures 1-6 As shown, the chip 1 provided by one of the embodiments of the present application comprises a plurality of pins 2 and a chip body 3, the plurality of pins 2 are connected to the first surface 301 of the chip body 3 and are arranged in an array on the first surface 301, wherein the first surface 201 of the pin 2 is flush with or protrudes from the first surface 301 of the chip body 3, and the first surface 201 is arranged in a planar manner. In this way, when the chip 1 with this structure is connected to the PCB, since the first surface 201 of the pin 2 is arranged in a planar manner, the pin 2 and the PCB are connected by surface contact, which is beneficial to increase the area of conduction compared with the scheme in which the pin 2 is designed as a solder ball and connected to the PCB by point contact.
[0032] It should be noted that the arrangement manner of the plurality of pins 2 can be selected as needed, for example, the plurality of pins 2 are distributed at equal intervals along the first direction X and / or the second direction Y shown in Figure 1 、 Figure 3 or Figure 5 . Among them, the position and size of the basic pin 2 (i.e. the pin of the basic unit of the array) can be set as needed, for example, the basic pin 2 can be located at the middle position of the first surface 301 of the chip body 3 as shown in Figure 1 、 Figure 3 or Figure 5 , or can be located near the edge of the first surface 301 of the chip body 3.
[0033] It should be understood that the first surface 201 arranged in a planar manner means that the first surface 201 of the pin 2 is a flat plane and is not inclined relative to the first surface 301, so as to facilitate the chip 1 to be in surface contact with the PCB when connected to the PCB, thereby helping to increase the area of conduction.
[0034] It can be understood that the pin 2 can have different heights relative to the first surface 301 of the chip body 3, which can be selected and set as needed.
[0035] For example, in some embodiments, the pin 2 does not protrude from the first surface 301 of the chip body 3, that is, the first surface 201 of the pin 2 is flush with the first surface 301 of the chip body 3, as shown in Figure 1 and Figure 2 , which is beneficial to reduce the overall thickness of the chip 1 compared with the scheme in which the pin 2 is designed as a solder ball and connected to the PCB by point contact, and the structure of the flat pin 2 can improve the impact resistance and heat dissipation capacity of the chip 1, which is beneficial to improve the reliability of the chip 1.
[0036] For another example, in some embodiments, as shown in Figures 4 to 6As shown, the pin 2 is protruded relative to the first surface 301 of the chip body 3, that is, the first surface 201 of the pin 2 exceeds the first surface 301 of the chip body 3, so that the chip body 3 has a heat dissipation space with the PCB when the chip 1 is connected to the PCB, which is beneficial to the timely heat dissipation of the chip 1, and the electrical elements on the PCB can also be arranged at the heat dissipation space, thereby reducing the mounting space reserved for the chip 1, which is beneficial to the mounting of the chip 1 on the PCB with limited specifications, and increases the applicable scenarios of the chip 1. The size of the pin 2 protruding the first surface 301 can be set as needed, and preferably, the size of the pin 2 protruding the first surface 201 is d, which satisfies 60 μm≤d≤150 μm.
[0037] The pin 2 can be made of a single metal material including but not limited to tin, gold, nickel gold, or nickel palladium gold, or can be made of different metal materials in different parts, which can be selected and set as needed. In the embodiment, as shown in Figure 5 As shown in Figure 6 The pin 2 includes a first conductive part 21 and a second conductive part 22 connected together, one end of the first conductive part 21 is connected with the chip body 3, and the other end of the first conductive part 21 is connected with the second conductive part 22. The first conductive part 21 and the second conductive part 22 can be made of the same material, for example, made of tin, gold, nickel gold, or nickel palladium gold. Of course, the first conductive part 21 and the second conductive part 22 can also be made of different materials, for example, the first conductive part 21 is made of metal copper, and the second conductive part 22 is made of tin, tin silver, nickel tin silver, gold, nickel gold, or nickel palladium gold.
[0038] In some embodiments, the first conductive part 21 and the second conductive part 22 are made of different materials, and the melting point of the first conductive part 21 is greater than that of the second conductive part 22, which reduces the risk of the first conductive part 21 and the second conductive part 22 being melted at the same time due to the temperature rise of the chip 1 during work. In the embodiment, the first conductive part 21 is made of metal copper, and the second conductive part 22 is formed in the form of a tin plating layer. In this way, under extreme conditions, when the temperature of the chip 1 rises to the melting point of the metal tin due to work, the second conductive part 22 made of the tin plating layer is melted, while the first conductive part 21 made of metal copper still maintains a solid state, avoiding the first conductive part 21 and the second conductive part 22 being melted together during use, which affects the connection between the chip 1 and the PCB.
[0039] It can be understood that, as viewed in the direction perpendicular to the first surface 301, the shape of the projection of the pin 2 on the first surface 301 can be a square, an ellipse, or a circle, or can be other shapes such as a polygon, which can be set as needed. Of course, the shapes of the plurality of pins 2 can be the same or different, for example, Figure 7As shown, for example, a portion of the pins 2 are square, and another portion of the pins 2 are circular or elliptical. In this embodiment, the projection of the pins 2 on the first surface 301 is square, which can be a rectangle or a square.
[0040] In some embodiments, as Figure 1 、 Figure 3 or Figure 5 As shown, the multiple pins 2 are divided into series pins 21a and parallel pins 21b. The series pins 21a and the parallel pins 21b are spaced apart. The series pins 21a are used to connect multiple connection points on the circuit board 33 of the chip body 3 in series, and the parallel pins 21b are used to connect multiple connection points on the circuit board 33 of the chip body 3 in parallel. It can be understood that the circuit board 33 of the chip body 3 has multiple connection points for circuits. The pins 2 connect to multiple connection points to achieve series or parallel connection of different circuits on the circuit board 33. The pins 2 are divided into series pins 21a or parallel pins 21b according to the series connection function or parallel connection function they implement. In this way, the series pins 21a and the parallel pins 21b help reduce the parasitic impedance of the chip 1 package.
[0041] In some embodiments, as Figure 8 As shown, the chip body 3 includes a package 31, a core 32, and a circuit board 33. The core 32 is connected to the circuit board 33. The package 31 covers the core 32 and the circuit board 33, and a plurality of pins 2 are connected to the circuit board 33. Among them, the pins 2 are used to connect to at least two connection points of the circuit board of the chip body 3 to achieve series or parallel connection between the pins 2 and the circuit board.
[0042] It is understood that the first surface 301 of the package housing 31 needs to be clear of air in the area where the plurality of pins 2 are located, so that the plurality of pins 2 can pass through the package housing 31 and connect to the connection points of the circuit board 33. In other words, during the chip 1 packaging process, a mounting area for the plurality of pins 2 must be reserved in advance so that the pins 2 can connect to the circuit board 33 through the reserved mounting area after packaging is completed.
[0043] In some embodiments, the package shell 31 covers six surfaces of the core 32 and the circuit board 33 , which helps to improve the mechanical strength of the chip 1 and reduces the risk of cracks in the chip 1 due to external forces.
[0044] In some embodiments, the package shell 31, the core 32 and the circuit board 33 are packaged by an LGA (Land Grid Array) packaging technology to form the chip 1, which is advantageous to improve the single-layer yield and reduce the packaging cost compared with a traditional round crystal level packaging. Of course, the package shell 31, the core 32 and the circuit board 33 can also be packaged by other packaging manners, which are not limited to the LGA packaging mentioned in the embodiment.
[0045] The chip 1 provided by the embodiment of the present application comprises a plurality of pins 2 and a chip body 3, the plurality of pins 2 are connected to the first surface 301 of the chip body 3 and are arranged in an array, and the first surface 201 of the pin 2 is flush with or protrudes from the first surface 301 of the chip body 3, and the first surface 201 is arranged in a planar manner. In this way, when the chip 1 with the structure is connected to a PCB, the pin 2 is connected to the PCB in a surface contact manner due to the planar arrangement of the first surface 201 of the pin 2, which is advantageous to increase the conduction area compared with a scheme in which the pin 2 is designed as a solder ball and connected to the PCB in a point contact manner, reduce the overall thickness of the chip 1, improve the impact resistance and heat dissipation capacity of the chip 1, and improve the reliability of the chip 1.
[0046] The electronic device provided by another embodiment of the present application comprises the chip 1 of the above-mentioned embodiment. The electronic device can be a vehicle such as a car, an airplane or a ship, or an electronic product such as a mobile phone, a notebook computer, a smart screen, a sound box or a router, or a medical instrument such as a diagnostic instrument or a treatment device, and of course can be other electronic devices requiring the chip 1.
[0047] The above-mentioned is only the implementation manner of the present application, and does not limit the patent range of the present application, and any equivalent structure or equivalent flow conversion according to the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection range of the present application.
Claims
1. A chip, characterized by The chip comprises: a chip body; a plurality of pins connected to a first surface of the chip body and arranged in an array on the first surface, wherein a first face of the pins protrudes from the first surface, the first face is planar, the pins comprise a first conductive part and a second conductive part connected to each other, one end of the first conductive part is connected to the chip body, the other end of the first conductive part is connected to the second conductive part, and the melting point of the first conductive part is higher than that of the second conductive part.
2. The chip according to claim 1, characterized in that, The pins are made of tin, gold, nickel gold or nickel palladium gold.
3. The chip of claim 1, wherein, The first conductive part is made of metal copper, and the second conductive part is made of tin, tin silver, nickel tin silver, gold, nickel gold or nickel palladium gold.
4. The chip of claim 1, wherein The shape of the projection of the pins in the direction perpendicular to the first surface comprises a square, an oval or a circle.
5. The chip according to any one of claims 1 to 4, wherein The size of the pins protruding from the first surface is d, and 60 μm≤d≤150 μm is satisfied.
6. The chip according to any one of claims 1 to 4, wherein The plurality of pins are divided into series pins and parallel pins, the series pins and the parallel pins are arranged at intervals, the series pins are used for connecting a plurality of connection points of a circuit board of the chip body in series, and the parallel pins are used for connecting a plurality of connection points of the circuit board of the chip body in parallel.
7. The chip according to any one of claims 1 to 4, wherein The chip body comprises a packaging shell, a core and a circuit board, the core is connected to the circuit board, the packaging shell covers the core and the circuit board, and the plurality of pins are connected to the circuit board.
8. An electronic device, comprising: The chip comprises any one of claims 1-7.