Stacked circuit structure and integrated circuit

Abstract

The embodiment of the utility model discloses a stacked circuit structure and an integrated circuit, a magnetic through hole is formed in the stacked circuit structure, and a metal through hole is formed in the magnetic through hole to enable the metal through hole to surround a magnetic material layer, so that an inductance element in a vertical direction is formed at a through hole structure of the stacked circuit structure; the inductance value and the quality factor of the inductor are improved, the paths of the inductance element and the chip are shortened, the power consumption loss is reduced, the power supply efficiency is improved, the conductive material loss on the paths is reduced, meanwhile, the circuit structure and the manufacturing process are simple, the inductance element does not occupy redundant physical resources, and the overall performance of the system is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, more particularly, a kind of stacked circuit structure and integrated circuit. BACKGROUND

[0002] With the iteration evolution of high algorithm power high power consumption of chip, it needs enough large space layout in physics, carries out the interconnection of power supply and signal, therefore will adopt three-dimensional chip stacking mode to carry out physical layout, with it brings the loss on circuit path, and inductance component is generally used on circuit path, how to form inductance circuit structure will influence the overall performance of chip. SUMMARY

[0003] Therefore, the utility model embodiment provides a kind of stacked circuit structure and integrated circuit, to form inductance component in the vertical direction at the via structure of stacked circuit structure, to improve inductance inductance and quality factor, shorten the path of inductance component and chip, reduce power consumption loss, improve power supply efficiency, reduce the loss of conductive material on path, simultaneously, circuit structure and manufacturing process are simple and make inductance component not occupy extra physical resources, improve the overall performance of system.

[0004] In a first aspect, the utility model embodiment provides a kind of stacked circuit structure, the stacked circuit structure includes:

[0005] via array formed in the longitudinal direction of the stacked circuit structure;

[0006] Wherein, the via array includes at least one first via structure, and the first via structure includes magnetic via and metal via formed in magnetic via.

[0007] Optionally, the via array includes second via structure, and the second via structure is metal via structure.

[0008] Optionally, the first via structure and the second via structure are evenly distributed.

[0009] Optionally, the diameter of the first end of the metal via is greater than the diameter of the second end.

[0010] Optionally, the diameter of the metal via is less than the diameter of the magnetic via, and the diameter of the metal via, the diameter of the magnetic via and / or the diameter difference between the magnetic via and the metal via is determined according to predetermined inductance parameters.

[0011] Optionally, the stacked circuit structure is a chip structure, including a substrate layer, a device layer and a metal layer.

[0012] Optionally, the stacked circuit structure is an interposer structure, including a substrate layer and a metal layer.

[0013] In a second aspect, the utility model discloses an integrated circuit, and the integrated circuit comprises:

[0014] An interposer structure is provided.

[0015] At least one chip structure is provided on the interposer structure.

[0016] The interposer structure and the at least one chip structure comprise a first via structure, and the first via structure comprises a magnetic via and a metal via formed in the magnetic via.

[0017] In a third aspect, the utility model discloses a via structure, and the via structure comprises:

[0018] A magnetic via is provided.

[0019] A metal via is formed in the magnetic via.

[0020] The utility model discloses a magnetic via is formed in the stacked circuit structure, and a metal via is formed in the magnetic via, so that the metal via surrounds the magnetic material layer, thereby forming an inductance element in the vertical direction at the via structure of the stacked circuit structure, improving the inductance value and the quality factor, shortening the path of the inductance element and the chip, reducing the power consumption loss, improving the power supply efficiency, reducing the loss of the conductive material on the path, and the circuit structure and the manufacturing process are simple, and the inductance element does not occupy the excess physical resources, thereby improving the overall system performance. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and other objects, features and advantages of the utility model will become more apparent from the following description of the utility model embodiments with reference to the accompanying drawings, in which:

[0022] Figures 1-2 It is a three-dimensional integrated circuit structure profile drawing of a comparative example;

[0023] Figure 3 It is a formation method flow chart of the stacked circuit structure of the utility model embodiment;

[0024] Figure 4 It is a formation process schematic view of the stacked circuit structure of the utility model embodiment;

[0025] Figure 5 It is another formation process schematic view of the stacked circuit structure of the utility model embodiment;

[0026] Figure 6 It is a schematic view of the integrated circuit of the utility model embodiment. DETAILED DESCRIPTION

[0027] The present application is described herein below with reference to examples, but the present application is not limited to these examples. In the following detailed description of the present application, some specific details are described in order to provide a thorough understanding of the present application. The present application can be fully understood without these detailed descriptions. In order to avoid obscuring the essence of the present application, well-known methods, procedures, processes, elements and circuits are not described in detail.

[0028] In addition, it should be understood that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0029] Meanwhile, it should be understood that, in the following description, "circuitry" refers to a conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is said to be "connected to" another element or said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0030] Unless otherwise clearly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly limited. For ordinary skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0031] For ease of description, spatially relative terms such as "inner", "outer", "below", "lower", "bottom", "top", "upper", and the like, can be used herein for describing an element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0032] Unless the context clearly requires otherwise, throughout the application, the general term "comprise", "comprising" or "comprises" is to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

[0033] In the description of the present application, it should be understood that the terms "first", "second" and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise stated.

[0034] Under the three-dimensional stacked circuit structure, the longitudinal via structure is used to realize the circuit connection structure, which usually increases the circuit connection path (such as power supply path) of the chip (especially the top chip), the parasitic electric signal on the link becomes larger, thereby affecting the quality of the circuit structure of the chip (such as the power supply quality of the power supply circuit, etc.).

[0035] Figures 1-2 is a cross-sectional view of a three-dimensional integrated circuit structure of a comparative example. Taking the three-dimensional integrated circuit structure as a power supply structure as an example, as shown in the longitudinal cross-sectional view of the power supply circuit of the top chip of the comparative example shown in Figure 1 , the three-dimensional integrated circuit structure 1 includes a silicon interposer 11, chips die1-die4. Among them, the silicon interposer 11 is used to provide high-performance electrical interconnection between multiple chips or dies, including a substrate layer 111 and a metal layer (topside metal layer). The silicon interposer 11, that is, a complex wiring and via structure (such as TSV, Through Silicon Via) is integrated on the substrate layer silicon wafer through the metal layer to connect different chips, which allows multiple chips to be stacked or arranged side by side in a more compact manner within one package, thereby greatly improving the integration and performance, while reducing signal delay and power consumption. The chips die1-die4 are arranged side by side on the silicon interposer 11, and the chips die1-die4 each include a substrate layer 211, a device layer 212, and a metal layer (faceside metal layer) 213. Among them, the via structure 214 is formed on the chips die1 and die3 to realize the circuit connection between the chips or with other devices.

[0036] Further, as shown in Figure 2The cross-sectional view of the power supply circuit structure of the comparative example shown in FIG. 2 shows a transistor (such as a CMOS transistor) connected to a silicon substrate 21. The through-hole structure of the silicon substrate 21 includes a first dielectric layer (Dielectric Layer) 22, a metal copper layer (Copper) 23, a second dielectric layer 24, and a magnetic core 25 (Magnetic Core) surrounded by the second dielectric layer 24. Thus, the comparative example can form an inductor element of the power supply circuit structure through the magnetic core 25. It can be seen that the comparative example adopts a horizontal magnetic inductor layout, which occupies more physical implementation resources. Based on the above-mentioned three-dimensional stacked circuit structure and the problems existing in the comparative example, the embodiment of the present invention provides a stacked circuit structure and its formation method, a through-hole structure and an integrated circuit to form an inductor element in a vertical direction at the through-hole structure of the stacked circuit structure, thereby improving the inductance value and quality factor, shortening the path of the inductor element and the chip, reducing power consumption loss, improving power supply efficiency, and reducing the loss of conductive materials on the path. At the same time, the circuit structure and manufacturing process are simple and the inductor element does not occupy extra physical resources, thereby improving the overall performance of the system.

[0037] In the embodiment of the present invention, a vertical magnetic inductor element is formed when a through-hole structure is formed in a three-dimensional stacked circuit structure. The magnetic inductor element can be applied to a power supply circuit structure, and can also be applied to other stacked circuit structures that require a magnetic inductor element. This embodiment is mainly described in detail with respect to the power supply circuit structure, but it should be understood that the embodiment of the present invention is not limited to this.

[0038] Figure 3 It is a flow chart of a method for forming a stacked circuit structure according to an embodiment of the present invention. Figure 4 Schematic diagram of the formation process of the stacked circuit structure of the embodiment of the present utility model. Figure 3 As shown, the method for forming a stacked circuit structure according to an embodiment of the present invention includes the following steps:

[0039] Step S110: drilling the initial stacked structure to form at least one first through hole. Figure 4 As shown, taking the formation of a through hole carrying magnetic material on the chip die as an example, the initial stacked structure 4 includes a substrate layer 41 (Substrate Layer), a device layer 42 (Device Layer), and a metal layer 43 (Metal Layer). In this embodiment, the initial stacked structure 4 is drilled to form a first through hole 44. This embodiment uses one first through hole 44 as an example, but it should be understood that this embodiment does not limit the number of first through holes 44, which can be set according to the actual number of inductance elements and / or inductance element parameters (such as inductance value, etc.).

[0040] Optionally, the substrate layer 41 may be a semiconductor substrate or a dielectric substrate. When formed of a semiconductor, the substrate layer 41 may be a silicon substrate. When formed of a dielectric, the substrate layer 41 may be formed of silicon oxide, silicon nitride, glass, or a combination of materials including silicon oxide, silicon nitride, glass, etc. This embodiment does not limit the materials and processes for forming the substrate layer 41.

[0041] Step S120: Fill the first through hole with magnetic material to form a magnetic through hole. Figure 4 As shown, a magnetic material is filled in the first through hole 44 to form a magnetic through hole 45 filled with magnetic material. It should be understood that this embodiment does not limit the magnetic material and filling method filled in the first through hole 44. It can be filled with any magnetic material that can form a magnetic inductor element and any existing or future possible process. For example, the magnetic material can be a ferrite material, such as iron (Fe), manganese (Mn), zinc (Zn), cobalt (Co), nickel (Ni), etc. or their alloys. The magnetic material can also be a soft magnetic alloy, such as iron-nickel alloy, iron-silicon-aluminum alloy, and iron-cobalt-vanadium alloy. The magnetic material can also be magnetic powder, magnetic film, carbonyl ferromagnetic glue, magnetostrictive material (such as nickel-based magnetostrictive material), superconducting material, magnetic nanocomposite material (such as magnetic nanoparticles composed of iron, manganese, zinc, cobalt, nickel, etc. and a non-magnetic matrix). It should be understood that the magnetic material of this embodiment can be a single metal material, an alloy material, or a combination of multiple magnetic materials. The type of magnetic material is not limited here, as long as it can meet the corresponding requirements.

[0042] Step S130: Drilling is performed in the magnetic through hole to form a second through hole. Figure 4 As shown, a second through-hole 46 is formed by drilling in the magnetic through-hole 45. The diameter of the second through-hole is smaller than the diameter of the first through-hole. Specifically, the diameter of the first end a1 of the second through-hole 46 is smaller than the diameter of the first end b1 of the first through-hole 44, and the diameter of the second end a2 of the second through-hole 46 is smaller than the diameter of the second end b2 of the first through-hole 44. In this embodiment of the present invention, the diameter of the magnetic through-hole (i.e., the diameter of the first through-hole), the diameter of the metal through-hole formed in the magnetic through-hole (i.e., the diameter of the second through-hole), and the difference in diameter between the second through-hole and the first through-hole formed in the magnetic through-hole are determined based on the desired predetermined inductance parameters and / or circuit connection requirements. This embodiment does not limit the specific dimensions.

[0043] Furthermore, this embodiment drills a hole at the center of magnetic via 45, ensuring that the retained magnetic material is evenly distributed within the via structure. In other optional implementations, this embodiment may also drill a hole outside the center of magnetic via 45, as long as the retained magnetic material can form an inductor element that meets specific circuit requirements. This embodiment does not limit the drilling location.

[0044] In an alternative implementation, the diameters of the two ends of the first via hole can be the same or different. Further alternatively, the diameter of the first end a1 of the second via hole 46 can be larger than the diameter of the second end a2, so as to form an included angle a less than 90° at the second end a2, thereby facilitating the drilling and subsequent filling of the conductive material. In other alternative implementations, the diameter of the first end a1 of the second via hole 46 can also be smaller than or equal to the diameter of the second end a2, which can be implemented in the manufacturing process, and the present embodiment is not limited thereto.

[0045] In step S140, the second via hole is filled with the conductive material to form the stacked circuit structure. As shown in FIG. 4, the conductive material is filled in the second via hole 46 to form a via hole structure 47 with the magnetic material, thereby obtaining a stacked circuit structure including the via hole structure with the magnetic material. Figure 4 In an alternative implementation, the present embodiment also drills the second via hole in the area other than the magnetic via hole. As shown in FIG. 5, the present embodiment also drills the second via hole in the area other than the magnetic via hole 45, and fills the conductive material in all the second via holes in step S140. Further alternatively, the forming operation of each second via hole of the present embodiment can be performed simultaneously or sequentially, and the filling operation of the conductive material in each via hole of the present embodiment can also be performed simultaneously or sequentially, and the present embodiment is not limited thereto.

[0046] Figure 4 Further alternatively, the sizes of each second via hole of the present embodiment are the same and uniformly distributed. In other alternative implementations, the sizes of each second via hole (i.e., the sizes of the metal via hole structure) can also be different, which can be set according to the specific process and specific requirements.

[0047] In another alternative implementation, the present embodiment can also form a dielectric layer outside the magnetic material to further ensure the reliability of the circuit structure.

[0048] In another alternative implementation, the present embodiment can also form a dielectric layer outside the magnetic material to further ensure the reliability of the circuit structure.

[0049] Figure 5 is another schematic diagram of the forming process of the stacked circuit structure of the present embodiment. As shown in FIG. 6, the present embodiment also drills the second via hole in the area other than the magnetic via hole 45, and fills the conductive material in all the second via holes in step S140. Figure 5 ​As shown in the figure, taking the example of forming the via carrying the magnetic material on the interposer structure 5, the initial interposer structure 5 includes a substrate layer 51 and a metal layer 52. The embodiment drills the initial interposer structure 5 to form a first via 53 on the substrate layer 51. The embodiment takes one first via 53 as an example, but it should be understood that the embodiment does not limit the number of the first via 53, which can be set according to the actual required number and / or inductance element parameters (such as inductance value, etc.) of the inductance element. The magnetic material is filled in the first via 53 to form a magnetic via 54 full of the magnetic material. The second via 55 is formed by drilling in the magnetic via 54. The conductive material is filled in the second via 55 to form a via structure 56 with the magnetic material, and then a stacked circuit structure including the via structure carrying the magnetic material is obtained. In an optional implementation manner, the embodiment also drills the second via in the area other than the magnetic via. As shown in the figure, the embodiment also drills the second via in the area other than the magnetic via 54, and fills the conductive material in all the second vias. Further optionally, the embodiment can also form a dielectric layer outside the magnetic material to further ensure the reliability of the circuit structure. It should be understood that the forming process of the via structure with the magnetic material of the interposer is similar to that of the chip die, which will not be described in detail here. Figure 5 Figure 4 The chip die is similar to that shown in the figure, which will not be described in detail here.

[0050] In an optional implementation manner, the via of the embodiment of the utility model can adopt a TDV via structure (Through Diamond Via, through diamond via technology), or a TSV via structure (Through Silicon Via, silicon through hole technology), or a PTH via structure (Plated Through Hole, plated through hole). It should be understood that the embodiment does not limit the specific via technology adopted, which can realize the formation of the via structure on the three-dimensional stacked circuit structure.

[0051] The embodiment of the utility model forms at least one first via by drilling the initial stacked structure, fills the magnetic material in the first via to form a magnetic via, drills the second via in the magnetic via, and fills the conductive material in the second via, so that the metal via of the stacked circuit structure is surrounded by the magnetic material. Therefore, the embodiment of the utility model can form the inductance element in the vertical direction at the via structure of the stacked circuit structure, improve the inductance value and the quality factor, shorten the path of the inductance element and the chip, reduce the power loss, improve the power supply efficiency, reduce the loss of the conductive material on the path, at the same time, the circuit structure and the manufacturing process are simple and the inductance element does not occupy the excess physical resources, and the overall performance of the system is improved.​

[0052] Another embodiment of the utility model provides a kind of integrated circuit, which can include at least one stacked circuit structure using the forming method of the above-mentioned stacked circuit structure.The stacked circuit structure includes via array formed in the longitudinal direction of stacked circuit structure.The via array includes at least one first via structure, and the first via structure includes magnetic via and metal via formed in the magnetic via.Further optionally, the via array includes second via structure, and the second via structure is metal via structure.The first via structure and the second via structure are uniformly distributed.The diameter of the first end of the metal via is greater than the diameter of the second end, and the diameter of the metal via is less than the diameter of the magnetic via, and the diameter of the metal via, the diameter of the magnetic via and / or the diameter difference between the magnetic via and the metal via is determined according to predetermined inductance parameter.

[0053] Optionally, as shown in Figure 4 The stacked circuit structure can be a chip structure, including substrate layer, device layer and metal layer. Figure 5 The stacked circuit structure can also be an interposer structure, including substrate layer and metal layer.

[0054] Figure 6 The utility model embodiment is a schematic diagram of an integrated circuit. In this embodiment, the power supply circuit structure of the top chip is taken as an example, as shown in Figure 6 The integrated circuit 6 includes a plurality of stacked circuit structures using the forming method of the above-mentioned stacked circuit structure, and further, the plurality of stacked circuit structures include an interposer structure 61 and at least one chip structure arranged on the interposer structure 61. In this embodiment, four chip structures, die1'-die4', are taken as an example, and the chip structures die1'-die4' are arranged side by side.

[0055] The interposer structure 61 includes substrate layer and metal layer. The substrate layer of the interposer structure 61 also has via array formed thereon to realize the interconnection between different chips. In this embodiment, the via array in the interposer structure 61 includes at least one first via structure 611. The first via structure 611 includes magnetic via 611a and metal via 611b formed in the magnetic via. It should be understood that the forming process of the first via structure 611 can refer to the embodiments shown in Figure 3 and Figure 5 The forming process of the first via structure 611 can refer to the embodiments shown in

[0056] In an optional implementation, the via array in the interposer structure 61 can further include at least one second via structure 612. The second via structure 612 is a metal via structure to realize electrical connection of different chips or other structures. Further optionally, the first via structure and the second via structure in the via array in the interposer structure 61 are uniformly distributed or non-uniformly distributed. It should be understood that the present embodiment does not limit the distribution positions of the first via structure and the second via structure, which can be set according to the requirements of a specific integrated circuit.

[0057] In the present embodiment, the chip structures die1'-die4' are arranged side by side on the interposer structure 61, and each of the chip structures die1'-die4' includes a substrate layer, a device layer and a metal layer. The chip structures die1' and die3' are formed with a via array to realize electrical connection between the chips or between the chips and other devices.

[0058] As shown in FIG. 6, the via array of the chip structure die1' includes at least one first via structure 621. The first via structure 621 includes a magnetic via and a metal via formed in the magnetic via. It should be understood that the forming process of the first via structure 621 can refer to the embodiments shown in FIGS. 1-5, which will not be described herein again. Figure 6 Figure 3 Figure 4

[0059] In an optional implementation, the via array in the chip structure die1' can further include at least one second via structure 622. The second via structure 622 is a metal via structure to realize electrical connection of different chips or other structures. Further optionally, the first via structure and the second via structure in the via array in the chip structure die1' are uniformly distributed or non-uniformly distributed. It should be understood that the present embodiment does not limit the distribution positions of the first via structure and the second via structure, which can be set according to the requirements of a specific integrated circuit.

[0060] Further, as shown in FIG. 8, the via array of the chip structure die3' includes at least one first via structure 631. The first via structure 631 includes a magnetic via and a metal via formed in the magnetic via. It should be understood that the forming process of the first via structure 631 can refer to the embodiments shown in FIGS. 1-5, which will not be described herein again. Figure 6 Figure 3 Figure 4

[0061] ​​​​​​In an alternative implementation, the via array in the chip structure die3' can further include at least one second via structure 632. The second via structure 632 is a metal via structure to realize electrical connection of different chips or other structures. Further alternatively, the first via structure and the second via structure in the via array in the chip structure die3' are uniformly distributed or non-uniformly distributed. It should be understood that the present embodiment does not limit the distribution positions of the first via structure and the second via structure, which can be set according to the requirements of a specific integrated circuit.

[0062] Further alternatively, the setting positions of the first via structure in the plurality of stacked circuit structures in the integrated circuit 6 can be adjusted based on the requirements of a specific circuit to further reduce the power supply path of the power supply circuit structure.

[0063] The embodiment of the present application forms the via structure including the magnetic via and the metal via formed in the magnetic via in at least one stacked circuit structure in the integrated circuit to form the inductance element in the vertical direction, improves the inductance value and the quality factor, shortens the path of the inductance element and the chip, reduces the power consumption loss, improves the power supply efficiency, reduces the loss of the conductive material on the path, and improves the overall system performance.

[0064] The embodiment of the present application forms the via structure including the magnetic via and the metal via formed in the magnetic via in at least one stacked circuit structure in the integrated circuit to form the inductance element in the vertical direction, improves the inductance value and the quality factor, shortens the path of the inductance element and the chip, reduces the power consumption loss, improves the power supply efficiency, reduces the loss of the conductive material on the path, and improves the overall system performance.

[0065] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A stacked circuit structure, characterized by, The stacked circuit structure comprises: a via array formed in the longitudinal direction of the stacked circuit structure; wherein the via array comprises at least a first via structure and a second via structure, the first via structure and the second via structure are uniformly distributed, the first via structure comprises a magnetic via and a metal via formed in the magnetic via, the diameter of the magnetic via, the diameter of the metal via formed in the magnetic via, and the difference between the diameter of the magnetic via and the diameter of the metal via formed in the magnetic via are determined according to the required predetermined inductance parameter and / or circuit connection requirement, and the second via structure is a metal via structure to realize the electrical connection of different chips or other structures. If the stacked circuit structure is a chip structure, the magnetic via is formed by filling a magnetic material in a first via formed by drilling on an initial chip structure comprising a substrate layer, a device layer and a metal layer.

2. The stacked circuit structure of claim 1, wherein, The diameter of the first end of the metal via is greater than the diameter of the second end.

3. The stacked circuit structure of claim 1, wherein, The diameter of the metal via is smaller than the diameter of the magnetic via, and the diameter of the metal via, the diameter of the magnetic via, and / or the difference between the diameter of the magnetic via and the diameter of the metal via are determined according to the predetermined inductance parameter.

4. The stacked circuit structure of claim 1, wherein, The stacked circuit structure is an interposer structure comprising a substrate layer and a metal layer.

5. An integrated circuit, characterized by The integrated circuit comprises: an interposer structure; at least one chip structure disposed on the interposer structure; the interposer structure and at least one chip structure comprise a first via structure and a second via structure, the first via structure and the second via structure are uniformly distributed, the first via structure comprises a magnetic via and a metal via formed in the magnetic via, the diameter of the magnetic via, the diameter of the metal via formed in the magnetic via, and the difference between the diameter of the magnetic via and the diameter of the metal via formed in the magnetic via are determined according to the required predetermined inductance parameter and / or circuit connection requirement, and the second via structure is a metal via structure to realize the electrical connection of different chips or other structures. In the chip structure, the magnetic via is formed by filling a magnetic material in a first via formed by drilling on an initial chip structure comprising a substrate layer, a device layer and a metal layer.

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