Signal shaping circuit, clock signal generating circuit, chip and electronic equipment
By generating a reference voltage and adjusting the offset voltage of the oscillation signal, and using a comparison module to cancel out power supply voltage jitter, the problem of the crystal oscillator clock signal duty cycle not being 50% is solved, and a stable clock signal output is achieved.
Patent Information
- Application Number
- CN202422640062.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2034-10-30
AI Technical Summary
The clock signal duty cycle of a crystal oscillator is not 50% due to power supply voltage jitter, which is difficult to solve effectively with existing technology.
A reference voltage is generated by the reference voltage output module, the offset voltage adjustment module adjusts the offset voltage of the oscillation signal, and the comparison module compares the reference voltage and the adjusted oscillation signal to cancel the low-frequency jitter caused by power supply voltage jitter and ensure the stability of the clock signal duty cycle.
It effectively offsets the impact of power supply voltage jitter on the clock signal, ensuring a 50% duty cycle for the clock signal and improving signal stability and accuracy.
Smart Images
Figure CN223472247U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a signal shaping circuit, a clock signal generation circuit, a chip and an electronic device. BACKGROUND
[0002] As a clock frequency source, compared with other types of oscillators, crystal oscillators are widely used in military and consumer electronics fields due to their excellent frequency accuracy and stability. Taking a Pierce oscillator as an example, the Pierce oscillator mainly includes a bias current generation circuit, a crystal oscillation circuit and a shaping output circuit. The bias current generation circuit can provide a bias current for the crystal oscillation circuit, so that the crystal oscillation circuit vibrates based on the bias current and outputs an oscillation signal. The shaping output circuit can shape the oscillation signal to output a clock signal with a duty cycle of 50%.
[0003] In related technologies, the shaping output circuit mainly compares the voltage signals at both ends of the crystal oscillator through a comparator to output a clock signal. However, since there is a low-frequency jitter phenomenon in the power supply voltage VDD, the voltage signals at both ends of the crystal oscillator also have a low-frequency voltage jitter phenomenon, and the low-frequency jitter voltage change trends contained in the voltage signals at both ends of the crystal oscillator are opposite, which leads to the problem that the duty cycle of the clock signal is not 50%. CONTENT OF THE INVENTION
[0004] In view of the above problems, the embodiments of the present application provide a signal shaping circuit, a clock signal generation circuit, a chip and an electronic device to solve the above technical problems.
[0005] In a first aspect, the embodiments of the present application provide a signal shaping circuit, which shapes a first oscillation signal to output a clock signal, and the signal shaping circuit comprises:
[0006] a reference voltage output module configured to generate a reference voltage according to a power supply voltage;
[0007] an offset voltage adjustment module configured to adjust an offset voltage of the first oscillation signal to output a second oscillation signal after the offset voltage is adjusted;
[0008] a comparison module, a first input end of the comparison module is connected with the reference voltage output module to access the reference voltage, and a second input end of the comparison module is connected with the offset voltage adjustment module to access the second oscillation signal, so that the comparison module compares the second oscillation signal and the reference voltage and outputs the clock signal.
[0009] In a second aspect, the embodiments of the present application provide a clock signal generation circuit, comprising:
[0010] a crystal oscillation circuit configured to output a first oscillation signal;
[0011] The signal shaping circuit of the first aspect is connected with the crystal oscillation circuit, so that the signal shaping circuit shapes the first oscillation signal and outputs the clock signal.
[0012] In a third aspect, an embodiment of the present application further provides a chip comprising the signal shaping circuit.
[0013] In a fourth aspect, an embodiment of the present application further provides an electronic device comprising the chip or the clock signal generation circuit.
[0014] The reference voltage output module generates the reference voltage according to the power supply voltage, and the offset voltage adjustment module outputs the second oscillation signal after adjusting the offset voltage according to the first oscillation signal, because the first oscillation signal, the second oscillation signal and the reference voltage follow the power supply voltage to jitter, and the offset voltage of the second oscillation signal is equal to the reference voltage, so the low-frequency jitter voltage contained in the second oscillation signal and the reference voltage is the same, the low-frequency jitter voltage contained in the second oscillation signal and the reference voltage accessed by the comparison module is common-mode canceled, and the comparison module actually outputs the clock signal according to the positive and negative of the alternating component in the second oscillation signal, so the influence of the power supply voltage jitter on the duty cycle of the clock signal can be avoided.
[0015] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0017] Figure 1 A schematic diagram of a Pierce oscillator in the related art is shown.
[0018] Figure 2 A signal schematic diagram of a Pierce oscillator in the related art is shown.
[0019] Figure 3 A schematic diagram of a signal shaping circuit in an embodiment of the present application is shown.
[0020] Figure 4 A schematic diagram of a signal shaping circuit in an embodiment of the present application is shown.
[0021] Figure 5 Another schematic diagram of a signal shaping circuit in an embodiment of the present application is shown.
[0022] Figure 6 Another schematic diagram of signals related to the signal shaping circuit in the embodiment of the application is shown.
[0023] Figure 7 Another schematic diagram of the signal shaping circuit in the embodiment of the application is shown.
[0024] Figure 8 Another schematic diagram of the signal shaping circuit in the embodiment of the application is shown.
[0025] Figure 9 Another schematic diagram of the signal shaping circuit in the embodiment of the application is shown.
[0026] Figure 10 Another schematic diagram of the signal shaping circuit in the embodiment of the application is shown.
[0027] Figure 11 Another schematic diagram of the signal shaping circuit in the embodiment of the application is shown.
[0028] Figure 12 Another schematic diagram of the signal shaping circuit in the embodiment of the application is shown.
[0029] wherein 100 is a signal shaping circuit, 200 is a crystal oscillation circuit, 10 is a reference voltage output module, 20 is an offset voltage adjustment module, 21 is a direct current filtering unit, 22 is an offset voltage compensation unit, 30 is a comparison module;
[0030] a first oscillation signal Vxi1, a clock signal CLK, a second oscillation signal Vxi2, and an alternating voltage Vac of the first oscillation signal;
[0031] a first capacitor C1, a first resistor R1, a second capacitor C2, a second resistor R2, a third resistor R3, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. DETAILED DESCRIPTION
[0032] The embodiments of the application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary only, and are used only to explain the application, and cannot be understood as a limitation of the application.
[0033] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application, so that those skilled in the art can better understand the solutions in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.
[0034] It should be noted that in the embodiments of the present application, in this document, the terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations.
[0035] Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.
[0036] In the description of the embodiments of the present application, the words "example" or "for example" are used to represent example, illustration or description. Any embodiment or design scheme described as "example" or "for example" in the embodiments of the present application is not interpreted as more preferred or having more advantages than another embodiment or design scheme. The words "example" or "for example" are intended to present the relative concept in a clear manner.
[0037] In addition, "multiple" in the embodiments of the present application means two or more, and therefore "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C, which can include A, B, C, A and B, A and C, B and C, or A and B and C.
[0038] It should be noted that in the embodiments of the present application, the association relationship of the associated objects described by "and / or" represents that there can be three relationships, for example, A and / or B can represent that there are three cases of A alone, A and B together, and B alone. In addition, the character " / ", if not specially specified, generally represents that the associated objects before and after it are in a "or" relationship.
[0039] It should be noted that the "connection" in the embodiments of the present application can be understood as an electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.
[0040] The control end of each transistor in the embodiments of the present application is a gate, the first pole / first end of each transistor is one of a source and a drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be indistinguishable in structure. For example, in the case of a P-type transistor, the first pole / first end of the transistor is a source, and the second pole / second end of the transistor is a drain; for example, in the case of an N-type transistor, the first pole / first end of the transistor is a source, and the second pole / second end of the transistor is a drain.
[0041] In the circuit structure provided by the embodiments of the present application, the nodes such as the first node and the second node are not actual components, but are convergence points of relevant couplings in a circuit diagram, that is, these nodes are nodes equivalent to convergence points of relevant couplings in a circuit diagram.
[0042] At present, as a clock frequency source, the crystal oscillator is widely used in the military and consumer electronics fields due to its excellent frequency accuracy and stability compared with other types of oscillators. Taking a Pierce oscillator as an example, refer to Figure 1 , Figure 1 A circuit schematic diagram of a Pierce oscillator in the related art is shown, wherein the Pierce oscillator mainly includes a current source I0 providing a bias current through a power supply end VDD, a crystal oscillator circuit composed of a crystal oscillator Y0, a capacitor C01, a capacitor C02, a feedback resistor Rf, and a transistor M0, and a comparator COMP outputting a square wave clock signal CLK0 by comparing the voltage across the crystal oscillator Y0.
[0043] During the operation of the Pierce oscillator, due to the negative gain from the gate to the drain of the transistor M0, the gate voltage VG and the drain voltage VD (i.e. the voltage across the crystal oscillator Y0) of the transistor M0 are respectively:
[0044] VG = V0 - V1Cosωt
[0045] VD = V0 + V1cosωt
[0046] Wherein, V0 is an offset voltage, V1 is the amplitude of the oscillation signal output by the crystal oscillator Y0, and ω is the oscillation frequency of the crystal oscillator Y0.
[0047] It can be seen that the gate voltage VG of the transistor M0 and the drain voltage VD change in opposite directions, so the comparator COMP can compare the voltages across the crystal Y0, thereby outputting a square wave clock signal CLK0.
[0048] However, referring to Figure 2 , Figure 2 A signal diagram of a Pierce oscillator in the related art is shown. Due to the low-frequency jitter phenomenon of the power supply voltage VDD, the voltage signals VG and VD across the crystal Y0 also have low-frequency voltage jitter phenomenon, and the low-frequency jitter voltage change trend contained in the voltage signals VD and VG across the crystal Y0 is opposite, which leads to the phenomenon that the voltage of the voltage signal VG is smaller than the voltage of the voltage signal VD for a longer time in the same period, and the voltage of the voltage signal VG is greater than the voltage of the voltage signal VD for a shorter time in the same period, thereby making the high-level duration and the low-level duration of the clock signal CLK0 output by the signal shaping circuit not equal, and finally leading to the problem that the duty cycle of the clock signal CLK0 is not 50%.
[0049] To this end, the present application provides a signal shaping circuit, a clock signal generation circuit, a chip and an electronic device, which are described in detail below.
[0050] First, referring to Figure 3 , Figure 3 A schematic diagram of a signal shaping circuit in an embodiment of the present application is shown, which shapes a first oscillation signal Vxi1 to output a clock signal CLK, wherein the signal shaping circuit includes a reference voltage output module 10, an offset voltage adjustment module 20 and a comparison module 30.
[0051] Specifically, the first oscillation signal Vxi1 can be, but is not limited to, a sine signal, a cosine signal, a triangular wave signal or a sawtooth wave signal, etc. For example, the first oscillation signal Vxi1 can be a sine signal at one end of a crystal in a crystal oscillation circuit or a cosine signal at the other end of the crystal.
[0052] The reference voltage output module 10 can generate a reference voltage Vref according to the power supply voltage VDD, so that the comparison module 30 outputs the clock signal CLK according to the reference voltage Vref. For example, the reference voltage output module 10 can include a plurality of series resistors, and the reference voltage Vref is generated by series resistance voltage division. It can be understood that the implementation of the reference voltage output module 10 outputting the reference voltage Vref is not limited to this, for example, the reference voltage output module 10 can also output the reference voltage Vref according to the power supply voltage through BOOST voltage boosting, BUCK voltage reduction circuit, etc.
[0053] The offset voltage adjustment module 20 is configured to adjust the offset voltage of the first oscillation signal Vxil and output the second oscillation signal Vxil after the adjustment of the offset voltage, so that the comparison module 30 compares the reference voltage Vref and the second oscillation signal Vxil and outputs the clock signal CLK. For example, taking the first oscillation signal Vxil as a cosine signal, the first oscillation signal Vxil can be expressed by the following formula:
[0054] Vxil = Vx1 + Vy cos ωt
[0055] In the above formula, Vx1 is the offset voltage of the first oscillation signal Vxil, Vy is the amplitude of the first oscillation signal, and ω is the oscillation frequency of the first oscillation signal. After the adjustment of the offset voltage by the offset voltage adjustment module 20, the second oscillation signal Vxil can be expressed by the following formula:
[0056] Vxil = Vx2 + Vy cos ωt
[0057] In the above formula, Vx2 is the offset voltage of the second oscillation signal Vxil, and Vx2 is not equal to Vx1, so that the offset voltage adjustment module 20 can adjust the offset voltage of the first oscillation signal Vxil and output the second oscillation signal Vxil after the adjustment of the offset voltage.
[0058] The first input end of the comparison module 30 is connected with the reference voltage output module 10 to access the reference voltage Vref, and the second input end of the comparison module 30 is connected with the offset voltage adjustment module 20 to access the second oscillation signal Vxil, so that the comparison module 30 can compare the second oscillation signal Vxil and the reference voltage Vref, thereby outputting the clock signal CLK. Exemplarily, the comparison module 30 can include but is not limited to a single limit comparator or a hysteresis comparator.
[0059] It should be noted that, referring to Figure 4 , Figure 4 A schematic diagram of related signals in the signal shaping circuit in the embodiment of the present application is shown. In the embodiment of the present application, the power supply voltage VDD has a jitter phenomenon. The jitter (or voltage ripple) phenomenon of the power supply voltage VDD can be an alternating current component superimposed in a direct current power supply after rectification and voltage stabilization, or a direct current voltage fluctuation caused by the alternation of opening and closing of a switching direct current power supply. Since the first oscillation signal Vxil, the second oscillation signal Vxil and the reference voltage Vref are all generated by the power supply voltage VDD, the first oscillation signal Vxil, the second oscillation signal Vxil and the reference voltage Vref all follow the jitter of the power supply voltage VDD.
[0060] Meanwhile, since the first oscillation signal Vxil, the second oscillation signal Vxi2 and the reference voltage Vref in the embodiment of the present application follow the power supply voltage VDD to jitter, and the offset voltage of the second oscillation signal Vxi2 is equal to the reference voltage Vref, the low-frequency jitter voltage contained in the second oscillation signal Vxi2 and the reference voltage Vref is the same.
[0061] For example, taking the above second oscillation signal Vxi2 satisfying Vxi2=Vx2+Vycosωt as an example, since the offset voltage of the second oscillation signal Vxi2 is equal to the reference voltage Vref, the second oscillation signal Vxi2 can be expressed by the following formula:
[0062] Vxi2=Vref+Vycosωt
[0063] It can be seen that for the second oscillation signal Vxi2 and the reference voltage Vref input to the comparison module 30, the common-mode voltage of the second oscillation signal Vxi2 and the reference voltage Vref is equal, so the low-frequency jitter voltage caused by the power supply voltage jitter can be offset by the common mode in the comparison module, and thus the comparison module 30 actually judges the positive and negative of the term Vycosωt in the above formula, which makes the output clock signal of the comparison module 30 not affected by the low-frequency jitter voltage caused by the power supply voltage jitter, and finally avoids the influence of the power supply voltage jitter on the duty cycle of the clock signal CLK.
[0064] In some embodiments of the present application, referring to Figure 5 , Figure 5 Another schematic diagram of the signal shaping circuit in the embodiment of the present application is shown, wherein the offset voltage adjustment module 20 comprises a DC filtering unit 21 and an offset voltage compensation unit 22; the input end of the DC filtering unit 21 is connected to the first oscillation signal Vxil, and the output end of the DC filtering unit 21 is connected to the second input end of the comparison module 30, so as to filter the offset voltage of the first oscillation signal Vxil and output the alternating voltage Vac of the first oscillation signal Vxil; the input end of the offset voltage compensation unit 22 is connected to the first input end of the comparison module 30, and the output end of the offset voltage compensation unit 22 is connected to the output end of the DC filtering unit 21, so as to compensate the reference voltage Vref as the offset voltage of the alternating voltage of the first oscillation signal Vxil and generate the second oscillation signal Vxi2.
[0065] For example, referring to Figure 6 , Figure 6Another schematic diagram of the signals related to the signal shaping circuit in the embodiment of the present application is shown, taking the first oscillation signal Vxi1 as a cosine signal Vxi1 = Vx1 + Vycosωt for example. After the first oscillation signal Vxi1 is filtered by the DC filter unit 21, the first oscillation signal Vxi1 only retains its alternating voltage Vac, and the output alternating voltage Vac satisfies the following relationship:
[0066] Vac = Vycosωt
[0067] Since the offset voltage compensation unit 22 outputs the reference voltage Vref to the output end of the DC filter unit 21, the reference voltage Vref can be compensated as an offset voltage to the alternating voltage of the first oscillation signal Vxi1, and the second oscillation signal Vxi2 with an offset voltage equal to the reference voltage Vref is generated, and the second oscillation signal Vxi2 after compensation satisfies the following relationship:
[0068] Vxi2 = Vref + Vycosωt
[0069] That is, in the above embodiment, the low-frequency alternating voltage is generated by filtering the DC voltage and the power supply voltage jitter of the first oscillation signal Vxi1, and only the alternating voltage Vac is retained, and finally the reference voltage Vref following the power supply voltage jitter is superimposed to generate the second oscillation signal Vxi2 following the power supply voltage jitter and the offset voltage equal to the reference voltage Vref, so that the low-frequency jitter voltage caused by the reference voltage Vref and the second oscillation signal Vxi2 caused by the power supply voltage jitter can be common-mode canceled in the comparison module 30.
[0070] As an exemplary embodiment of the DC filter unit 21, refer to Figure 7 , Figure 7 Another schematic diagram of the signal shaping circuit in the embodiment of the present application is shown, wherein the DC filter unit 21 includes a first capacitor C1; the first end of the first capacitor C1 is connected to the first oscillation signal Vxi1, and the second end of the first capacitor C1 is connected to the second input end of the comparison module 30. Specifically, since the first capacitor C1 has the characteristic of passing alternating current and blocking direct current, the first capacitor C1 can filter the DC component and the low-frequency jitter voltage in the first oscillation signal Vxi1, and output the alternating voltage Vac of the high frequency in the first oscillation signal Vxi1, so as to superimpose the reference voltage Vref on the alternating voltage Vac of the first oscillation signal Vxi1, and generate the second oscillation signal Vxi2 with an offset voltage equal to the reference voltage Vref.
[0071] As can be understood by those skilled in the art, the implementation of the DC filter unit 21 is not limited thereto, for example, the DC filter unit 21 can also use a plurality of capacitors in series and / or in parallel.
[0072] As an exemplary embodiment of the offset voltage compensation unit 22, refer to Figure 8 , Figure 8 Another schematic diagram of the signal shaping circuit in the embodiments of the present application is shown, wherein the offset voltage compensation unit 22 comprises a first resistor R1 and a second capacitor C2; a first end of the first resistor R1 is connected with the first input end of the comparison module 30, and a second end of the first resistor R1 is connected with the second input end of the comparison module 30; a first end of the second capacitor C2 is connected with the first end of the first resistor R1, and a second end of the second capacitor C2 is connected with the ground end GND.
[0073] It should be noted that the first resistor R1 and the second capacitor C2 constitute a low-pass filter, which not only prevents the high-frequency alternating voltage in the first oscillation signal Vxi1 from being input to the first input end of the comparison module 30, but also inputs the low-frequency jittered reference voltage Vref to the second input end of the comparison module 30, so that the alternating voltage Vac of the first oscillation signal Vxi1 is superimposed with the reference voltage Vref, and the second oscillation signal Vxi2 with an offset voltage equal to the reference voltage Vref is generated.
[0074] It can be understood that Figure 8 The embodiment shown in the above is an example of implementing the function of the offset voltage compensation unit 22 (i.e., the offset voltage compensation unit 22 inputs the low-frequency jittered reference voltage Vref at the first input end of the comparison module 30 to the second input end of the comparison module 30, and prevents the high-frequency jittered alternating voltage Vac at the second input end of the comparison module 30 from being input to the first input end of the comparison module 30) by using a first-order low-pass filter. In some possible embodiments, the function of the offset voltage compensation unit 22 can also be implemented by using a second-order low-pass filter or a third-order low-pass filter.
[0075] In some embodiments of the present application, for example, for the embodiment in which the reference voltage output module 10 comprises a resistor divider circuit, refer to Figure 9 , Figure 9 Another schematic diagram of the signal shaping circuit in the embodiments of the present application is shown, wherein the reference voltage output module 10 comprises a second resistor R2 and a third resistor R3; a first end of the second resistor R2 is connected with the power supply end VDD, a second end of the second resistor R2 is connected with a first end of the third resistor R3, a second end of the third resistor R3 is connected with the ground end GND, and a first node m1 between the second resistor R2 and the third resistor R3 is connected with the first input end of the comparison module 30. That is, the second resistor R2 and the third resistor R3 are connected in series between the power supply end and the ground end GND, so that the reference voltage Vref output at the first node satisfies: Vref=VDD*R3 / (R2+R3). Since the resistance values of the second resistor R2 and the third resistor R3 are constant, the reference voltage Vref output at the first node can follow the jitter of the power supply voltage VDD.
[0076] It can be understood that the reference voltage output module 10 can further include a plurality of resistors connected in series and in parallel, and output the reference voltage Vref at a certain node in the plurality of resistors connected in series and in parallel.
[0077] As an exemplary embodiment of the comparison module 30, refer to Figure 10 , Figure 10 Another schematic diagram of the signal shaping circuit in the embodiment of the application is shown, wherein the comparison module 30 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; the first end of the first transistor M1 is connected with a power supply end, the second end of the first transistor M1 is connected with the first end of the second transistor M2, the second end of the first transistor M1 is connected with the first end of the third transistor M3, and the control end of the first transistor M1 is connected with a preset bias voltage VB; the second end of the second transistor M2 is connected with the second end of the fourth transistor M4, and the control end of the second transistor M2 is connected with a reference voltage Vref; the second end of the third transistor M3 is connected with the second end of the fifth transistor M5, and the control end of the third transistor M3 is connected with a second oscillation signal Vxi2; the first end of the fourth transistor M4 is connected with a ground end GND, the control end of the fourth transistor M4 is connected with the second end of the fourth transistor M4; the first end of the fifth transistor M5 is connected with the ground end GND, and the control end of the fifth transistor M5 is connected with the second end of the fifth transistor M5; the second end of the sixth transistor M6 is connected with the second end of the third transistor M3, the first end of the sixth transistor M6 is connected with the ground end GND, and the control end of the sixth transistor M6 is connected with the control end of the fourth transistor M4; the second end of the seventh transistor M7 is connected with the second end of the fourth transistor M4, the first end of the seventh transistor M7 is connected with the ground end GND, and the control end of the seventh transistor M7 is connected with the control end of the fifth transistor M5.
[0078] For example, when the voltage of the second oscillation signal Vxi2 is greater than the reference voltage Vref, the current outputted by the second transistor M2 is greater than the current outputted by the third transistor M3, and due to the current mirroring effect of the sixth transistor M6 and the fourth transistor M4, the current outputted by the third transistor M3 is greater than the current inputted into the sixth transistor M6, so the drain voltage of the third transistor M3 is pulled up, thereby a low-level signal can be outputted at the drain of the third transistor M3 when the voltage of the second oscillation signal Vxi2 is greater than the reference voltage Vref; conversely, when the voltage of the second oscillation signal Vxi2 is less than the reference voltage Vref, the current outputted by the second transistor M2 is less than the current outputted by the third transistor M3, and due to the current mirroring effect of the sixth transistor M6 and the fourth transistor M4, the current outputted by the third transistor M3 is less than the current inputted into the sixth transistor M6, so the drain voltage of the third transistor M3 is pulled down, thereby a high-level signal can be outputted at the drain of the third transistor M3 when the voltage of the second oscillation signal Vxi2 is greater than the reference voltage Vref, so the comparison module 30 according to the above embodiment can finally output a clock signal CLK which periodically changes.
[0079] As another embodiment of the comparison module 30, refer to Figure 11 , As another embodiment of the comparison module 30, refer to Figure 11 Another schematic diagram of the signal shaping circuit in the embodiment of the application is shown, wherein the comparison module 30 comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5; the first end of the first transistor M1 is connected with a power supply end, the second end of the first transistor M1 is connected with the first end of the second transistor M2, the second end of the first transistor M1 is connected with the first end of the third transistor M3, and the control end of the first transistor M1 is connected with a preset bias voltage; the second end of the second transistor M2 is connected with the second end of the fourth transistor M4, and the control end of the second transistor M2 is connected with a reference voltage Vref; the second end of the third transistor M3 is connected with the second end of the fifth transistor M5, and the control end of the third transistor M3 is connected with a second oscillation signal Vxi2; the first end of the fourth transistor M4 is connected with a ground end GND, and the control end of the fourth transistor M4 is connected with the second end of the fourth transistor M4; the first end of the fifth transistor M5 is connected with the ground end GND, and the control end of the fifth transistor M5 is connected with the control end of the fourth transistor M4.
[0080] Similarly, when the voltage of the second oscillation signal Vxi2 is greater than the reference voltage Vref, the current outputted by the second transistor M2 is greater than the current outputted by the third transistor M3, due to the current mirroring effect of the fifth transistor M5 and the fourth transistor M4, the current outputted by the third transistor M3 is less than the mirroring current of the fifth transistor M5, thus the drain voltage of the third transistor M3 is pulled down, so that a low level signal can be outputted at the drain of the third transistor M3 when the voltage of the second oscillation signal Vxi2 is greater than the reference voltage Vref; conversely, when the voltage of the second oscillation signal Vxi2 is less than the reference voltage Vref, the current outputted by the second transistor M2 is less than the current outputted by the third transistor M3, due to the current mirroring effect of the fifth transistor M5 and the fourth transistor M4, the current outputted by the third transistor M3 is greater than the current inputted to the fifth transistor M5, thus the drain voltage of the third transistor M3 is pulled up, so that a high level signal can be outputted at the drain of the third transistor M3 when the voltage of the second oscillation signal Vxi2 is greater than the reference voltage Vref, thus the comparison module 30 of the above embodiment can finally output a clock signal CLK which periodically changes.
[0081] It should be noted that the above content about the signal shaping circuit is intended to clearly illustrate the implementation and verification process of the present application, and those skilled in the art can also make equivalent modifications and designs under the guidance of the present application. For example, the above Figure 10 and Figure 11 is a pair of PMOS transistors as the differential input pair of the second oscillation signal Vxi2 and the reference voltage Vref, in some possible embodiments, a pair of NMOS transistors can also be used as the differential input pair of the second oscillation signal Vxi2 and the reference voltage Vref, or a pair of NMOS transistors and a pair of PMOS transistors can also be used as the differential input pair of the second oscillation signal Vxi2 and the reference voltage Vref.
[0082] In order to better implement the signal shaping circuit 100 in the embodiments of the present application, on the basis of the signal shaping circuit 100, the present application further provides a clock signal generating circuit, which comprises a crystal oscillation circuit 200 for outputting a first oscillation signal Vxi1 and the signal shaping circuit 100 described in any of the above embodiments, the signal shaping circuit 100 is connected with the crystal oscillation circuit 200, so that the signal shaping circuit 100 shapes the first oscillation signal Vxi1 and outputs a clock signal CLK.
[0083] For example, referring to Figure 12 , Figure 12A schematic diagram of the clock signal generation circuit in the embodiment of the present application is shown. The crystal oscillator circuit 200 includes a current source I0, a crystal oscillator Y0, a feedback resistor Rf, a capacitor C01, a capacitor C02, and a transistor M0. When the current source I0 inputs a bias current, the crystal oscillator Y0 starts oscillating. Due to the transconductance of the transistor M0, the two ends of the crystal oscillator Y0 can output oscillation signals XO and XI with a phase difference of 180°, respectively. Therefore, the signal shaping circuit 100 can shape the oscillation signal XO (i.e., the drain voltage of the sixth transistor M6) and output the clock signal CLK.
[0084] It can be understood that the signal shaping circuit 100 can shape the oscillation signal XI (i.e., the gate voltage of the sixth transistor M6) and output the clock signal CLK.
[0085] Since the clock signal generation circuit of the present application has the signal shaping circuit 100 described in the above embodiment, the clock signal CLK output by the clock signal generation circuit of the present application will not be affected by the power supply voltage jitter, so that a clock signal CLK with a duty cycle of 50% can be output.
[0086] The embodiment of the present application also provides a chip including the above-mentioned signal shaping circuit 100. The chip (IC) is also called a chip, which can be but is not limited to a SOC (System on Chip) chip, a SIP (system in package) chip. Since the chip of the present application has the signal shaping circuit 100 described in the above embodiment, it has all the beneficial effects of the signal shaping circuit 100 described in the above embodiment, which will not be repeated here.
[0087] The embodiment of the present application also provides an electronic device including a device main body and a chip as described above arranged in the device main body. The electronic device can be but is not limited to a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle-mounted charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car control panel, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes but is not limited to a smart watch, a smart bracelet, a cervical vertebra massage instrument. The mobile terminal includes but is not limited to a smart phone, a notebook computer, a tablet computer, a POS (point of sales terminal) machine. The smart home device includes but is not limited to a smart socket, a smart rice cooker, a smart sweeper, a smart lamp.
[0088] The above merely describes the preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some more changes or modifications to the equivalent embodiments with the disclosed technical content, as long as the changes or modifications do not deviate from the technical solution of the present application. Any brief modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still falls within the scope of the technical solution of the present application.
Claims
1. A signal shaping circuit, characterized by, The signal shaping circuit shapes the first oscillation signal to output a clock signal, and the signal shaping circuit comprises: a reference voltage output module for generating a reference voltage according to a power supply voltage; an offset voltage adjustment module for adjusting an offset voltage of the first oscillation signal to output a second oscillation signal after the offset voltage is adjusted; a comparison module, a first input end of the comparison module is connected with the reference voltage output module to access the reference voltage, and a second input end of the comparison module is connected with the offset voltage adjustment module to access the second oscillation signal, so that the comparison module compares the second oscillation signal and the reference voltage and outputs the clock signal.
2. The signal shaping circuit of claim 1, wherein, The offset voltage adjustment module comprises a DC filter unit and an offset voltage compensation unit; an input end of the DC filter unit accesses the first oscillation signal, and an output end of the DC filter unit is connected with the second input end of the comparison module to filter the offset voltage of the first oscillation signal and output an alternating voltage of the first oscillation signal; an input end of the offset voltage compensation unit is connected with the first input end of the comparison module, and an output end of the offset voltage compensation unit is connected with the output end of the DC filter unit to compensate the alternating voltage of the first oscillation signal with the reference voltage as an offset voltage and generate the second oscillation signal.
3. The signal shaping circuit of claim 2, wherein, The DC filter unit comprises a first capacitor; a first end of the first capacitor accesses the first oscillation signal, and a second end of the first capacitor is connected with the second input end of the comparison module.
4. The signal shaping circuit of claim 2, wherein, The offset voltage compensation unit comprises a first resistor and a second capacitor; a first end of the first resistor is connected with the first input end of the comparison module, and a second end of the first resistor is connected with the second input end of the comparison module; a first end of the second capacitor is connected with the first end of the first resistor, and a second end of the second capacitor is connected with a ground end.
5. The signal shaping circuit of claim 1, wherein, The reference voltage output module comprises a second resistor and a third resistor; a first end of the second resistor is connected with a power supply end, a second end of the second resistor is connected with a first end of the third resistor, a second end of the third resistor is connected with a ground end, and a first node between the second resistor and the third resistor is connected with the first input end of the comparison module.
6. The signal shaping circuit of claim 1, wherein The comparison module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; a first end of the first transistor is connected with a power supply end, a second end of the first transistor is connected with a first end of the second transistor, a second end of the first transistor is connected with a first end of the third transistor, and a control end of the first transistor accesses a preset bias voltage; a second end of the second transistor is connected with a second end of the fourth transistor, and a control end of the second transistor accesses the reference voltage; a second end of the third transistor is connected with a second end of the fifth transistor, and a control end of the third transistor accesses the second oscillation signal; The first end of the fourth transistor is connected with a ground end, and the control end of the fourth transistor is connected with the second end of the fourth transistor. The first end of the fifth transistor is connected with a ground end, and the control end of the fifth transistor is connected with the second end of the fifth transistor. The second end of the sixth transistor is connected with the second end of the third transistor, the first end of the sixth transistor is connected with a ground end, and the control end of the sixth transistor is connected with the control end of the fourth transistor. The second end of the seventh transistor is connected with the second end of the fourth transistor, the first end of the seventh transistor is connected with a ground end, and the control end of the seventh transistor is connected with the control end of the fifth transistor.
7. The signal shaping circuit of claim 1, wherein The comparison module comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor. The first end of the first transistor is connected with a power supply end, the second end of the first transistor is connected with the first end of the second transistor, the second end of the first transistor is connected with the first end of the third transistor, and the control end of the first transistor is connected with a preset bias voltage. The second end of the second transistor is connected with the second end of the fourth transistor, and the control end of the second transistor is connected with the reference voltage. The second end of the third transistor is connected with the second end of the fifth transistor, and the control end of the third transistor is connected with the second oscillation signal. The first end of the fourth transistor is connected with a ground end, and the control end of the fourth transistor is connected with the second end of the fourth transistor. The first end of the fifth transistor is connected with a ground end, and the control end of the fifth transistor is connected with the control end of the fourth transistor.
8. A clock signal generating circuit, characterized by comprising: It comprises: a crystal oscillation circuit for outputting a first oscillation signal; The signal shaping circuit according to any one of claims 1 to 7 is connected with the crystal oscillation circuit, so that the signal shaping circuit shapes the first oscillation signal and outputs a clock signal.
9. A chip, characterized by It comprises the signal shaping circuit according to any one of claims 1 to 7.
10. An electronic device, comprising: It comprises the chip according to claim 9.