Via hole structure, integrated circuit board and electronic device

Abstract

The utility model belongs to the field of circuit board design, and particularly discloses a via hole structure, an integrated circuit board and an electronic device, the via hole structure is arranged on a circuit integrated board, the circuit integrated board comprises a plurality of signal layers, and the via hole structure comprises a hole column and at least two bonding pads; the bore log penetrates through at least two signal layers of the circuit integrated board; the at least two bonding pads are arranged at the positions, penetrated by the hole columns, in the at least two signal layers one by one; the areas of adjacent bonding pads in the at least two bonding pads are not overlapped in the length direction of the bore log, and the area of each bonding pad is smaller than a preset value. According to the utility model, on the basis of via hole design and pad optimization, the parasitic capacitance of the via hole can be effectively reduced so as to compensate the via hole impedance, so that the value of the via hole impedance is closer to the on-line impedance, and the insertion loss at the via hole structure is greatly reduced.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the field of circuit board design, more particularly, relate to a via structure, integrated circuit board and electronic device. BACKGROUND

[0002] High-speed signal line via is a hole that signal needs to pass through when transmitting from an interconnection line on one layer to another interconnection line on another layer in a multi-layer signal board of high-speed printed circuit board (PCB). When the frequency is below 1GHz, the via can play a good connecting role, and its parasitic capacitance and inductance can be ignored. However, when the frequency is higher than 1GHz, the parasitic effect of the via on signal integrity cannot be ignored. At this time, the via behaves as a discontinuous breakpoint in the transmission path, which can cause signal reflection, delay, attenuation and other signal integrity problems.

[0003] In order to ensure the integrity of the signal and reduce noise interference, it is necessary to design the impedance continuity of the high-speed signal line via. In high-speed circuits, if the impedance of the signal line changes, it will cause problems such as signal reflection and crosstalk, which will affect the quality and stability of the signal. Therefore, when designing the high-speed signal line via, special attention should be paid to the impedance continuity to reduce signal reflection and crosstalk, so as to ensure the integrity of the signal and reduce noise interference. SUMMARY

[0004] In view of the defects of the prior art, the purpose of the utility model is to provide a via structure, integrated circuit board and electronic device, which aims to solve the problem of discontinuous via impedance in the existing circuit board.

[0005] To achieve the above purpose, in a first aspect, the utility model provides a via structure, which is arranged on a circuit integrated board, the circuit integrated board comprises a plurality of signal layers, and the via structure comprises a hole column and at least two pads.

[0006] The hole column penetrates at least two signal layers of the circuit integrated board.

[0007] The at least two pads are arranged one by one at the positions penetrated by the hole column in the at least two signal layers respectively.

[0008] The areas of adjacent pads in the at least two pads do not overlap in the length direction of the hole column, and the area of each pad is less than a preset value.

[0009] In one possible implementation, each pad is distributed on only one side of the hole column in the corresponding signal layer.

[0010] In one possible implementation, the pad is a long strip.

[0011] In a possible implementation, adjacent pads among the at least two pads are at an obtuse angle in the length direction.

[0012] In a possible implementation, adjacent pads among the at least two pads are at an angle of 180 degrees in the length direction.

[0013] In a possible implementation, the area of the pad is less than a preset proportion of the area of a preset disc-shaped pad; and a difference between the inner diameter and the outer diameter of the disc-shaped pad is close to the length of the pad.

[0014] Preferably, the preset proportion can be 1 / 3, 1 / 4, or the like.

[0015] It can be understood that the difference between the inner diameter and the outer diameter of the disc-shaped pad is close to the length of the improved pad, which means that the ratio of the difference between the inner diameter and the outer diameter to the length is close to 1:1.

[0016] In a second aspect, the present application provides an integrated circuit board comprising the via structure described in the first aspect or any possible implementation of the first aspect.

[0017] In a third aspect, the present application provides an electronic device comprising the via structure described in the first aspect or any possible implementation of the first aspect.

[0018] Overall, compared with the prior art, the above technical scheme conceived by the present application mainly has the following technical advantages:

[0019] The present application provides a via structure, an integrated circuit board and an electronic device. By optimizing the via pad, the pad area is reduced, and the formation of capacitance between the upper and lower pads of the reduced area and between the pad and the surrounding conductor is avoided. The pad areas between the upper and lower signal layers do not overlap, which can completely avoid the overlap between the pads and can prevent the formation of capacitance between the pads. The above improvement reduces the parasitic capacitance of the via, correspondingly increases the impedance of the via, and effectively improves the integrity of the signal flowing through the via. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a schematic diagram of an existing via structure provided by an embodiment of the present application;

[0021] Figure 2A is a schematic diagram of a pad of an existing via structure provided by an embodiment of the present application;

[0022] Figure 2B is a schematic diagram of a pad of an improved via structure provided by an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of an improved via structure provided by an embodiment of the present application;

[0024] Figure 4 is a simulation result schematic diagram of an existing via structure impedance provided by the embodiment of the present application;

[0025] Figure 5 is a simulation result schematic diagram of an improved via structure impedance provided by the embodiment of the present application.

[0026] In all the drawings, the same reference signs are used to represent the same elements or structures, wherein:

[0027] 100 is a hole column, and 200 is a solder pad. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0029] The present application is applicable to the design of various digital signal boards, mainly aiming at the signal reflection problem caused by the impedance mutation of high-speed digital signal via, and can effectively reduce the parasitic capacitance of the via and further compensate the via impedance through reasonable hole design and solder pad optimization.

[0030] Figure 1 is a schematic diagram of an existing via structure provided by the embodiment of the present application; as shown in Figure 1 , the existing via structure includes: a hole column 100 and a plurality of solder pads 200.

[0031] As shown in Figure 1 , it can be seen that the plurality of solder pads 200 of the existing via structure are disc-shaped, and the plurality of solder pads overlap each other in the hole column length direction, and the disc-shaped solder pads have a large area. Therefore, the parasitic capacitance between adjacent solder pads in the adjacent hole column length direction and between the solder pads and the surrounding circuit is large, so that the impedance of the via structure is small. At this time, the impedance transmission path at the via structure shows a discontinuous breakpoint in impedance, which will cause signal integrity problems such as signal reflection, delay and attenuation.

[0032] Figure 2A is a schematic diagram of a solder pad of an existing via structure, Figure 2B is a schematic diagram of a solder pad of an improved via structure; as shown in Figure 2A and attached Figure 2B , it can be seen that the solder pad of the existing via is a disc-shaped structure, which has a large area, and adjacent solder pads in the hole column direction must overlap each other, which will produce a large parasitic capacitance. The improved via provided by the present application has a small area of the solder pad, and each solder pad is distributed on one side of the hole column in the corresponding signal layer.

[0033] as attachedFigure 2B In an example, the pad is a long strip shape, and the length of the long strip shape pad is close to the difference between the inner diameter and the outer diameter of the disc-shaped pad, so as to ensure the basic function of the pad.

[0034] Figure 3 It is an improved via structure schematic diagram provided by the embodiment of the utility model; as Figure 3 Indicated, the pad provided by the application includes: hole column 100 and at least two pads 200.

[0035] Among them, the via structure is arranged on the circuit integration board, and the circuit integration board includes multiple signal layers.

[0036] Preferably, the hole column 100 penetrates at least two signal layers of the circuit integration board;

[0037] The at least two pads 200 are respectively arranged at the positions penetrated by the hole column 100 in the at least two signal layers;

[0038] The area of adjacent pads 200 in the at least two pads 200 does not overlap in the length direction of the hole column 100, and the area of each pad 200 is less than a preset value.

[0039] From Figure 3 It can be seen that each pad 200 is only distributed on one side of the hole column 100 in the corresponding signal layer.

[0040] Optionally, the pad 200 is a long strip shape, for example Figure 2B And Figure 3 The runway type shown in the figure.

[0041] Further optionally, the included angle of adjacent pads 200 in the length direction of the at least two pads 200 is an obtuse angle.

[0042] In an embodiment, as Figure 3 Indicated, the included angle of adjacent pads 200 in the length direction is 180 degrees.

[0043] In an example, the area of the pad 200 is less than a preset proportion of the area of a preset disc-shaped pad; the difference between the inner diameter and the outer diameter of the disc-shaped pad is close to the length of the pad. The disc-shaped pad mentioned above is the pad used in the prior art, which can also be seen from Figure 1 And Figure 2A Indicated.

[0044] Preferably, the preset proportion can be 1 / 3, 1 / 4, etc.

[0045] Further optionally, the signal layer located in the first layer among the multiple signal layers can be referred to as a surface signal layer, and the corresponding pad can be referred to as a surface pad. The signal layer below the first layer can be referred to as an internal signal layer, and the corresponding pad can be referred to as an internal pad.

[0046] Figure 4 and Figure 5 is a simulation result schematic diagram of an existing via structure impedance and an improved via structure impedance provided by the embodiment of the present application; as shown in Figure 4 , the impedance value of the existing via is about 47.5 ohms, as shown in Figure 5 , the impedance value of the improved via is about 49.5 ohms. The on-line impedance on the integrated circuit board is 50 ohms, and the Figure 4 and Figure 5 m1 represents impedance; it can be seen that the impedance of the improved via is closer to the on-line impedance. Therefore, the via provided by the present application will be more continuous in the transmission path, which can greatly avoid the problems of signal reflection, delay, attenuation and the like, and ensures the integrity of the signal.

[0047] The skilled in the art can understand that in the PCB design, the impedance at the via is low, in the high-speed design, the slight mutation of the impedance will cause large insertion loss, and in severe cases, will affect the eye height and eye width of the eye diagram, in the existing design, the formation of the parasitic capacitance is reduced by removing the middle useless pads to compensate the impedance, but the parasitic capacitance still exists between the surface layer signal and the middle layer signal. Because there is a pressure difference between the two electrical conductors, the electric charge moves under the force in the electric field to form a capacitor, and there is a small pressure difference between the pads and the surrounding layer copper foil of the via, and a capacitor is formed. The present application optimizes the via pad and removes part of the pad area, which avoids the formation of the capacitor between the upper and lower pads and between the pad and the surrounding conductor. The pad angle of the upper and lower signal layers is an obtuse angle, such as 180 degrees, which completely avoids the overlapping between the pads, so that the formation of the capacitor between the pads can be eliminated. In this way, there is no overlapping between the signal layer pads of the via, thereby further reducing the parasitic capacitance, and when the parasitic capacitance is reduced, the impedance of the via is improved, and the signal integrity is effectively improved.

[0048] Further, the via structure provided by the present application can be applied to the corresponding integrated circuit board and / or electronic device.

[0049] It should be understood that the expressions such as "include" and "may include" used in the present application represent the existence of the disclosed functions, operations or constituent elements, and do not limit one or more additional functions, operations and constituent elements. In the present application, terms such as "include" and / or "have" can be interpreted to represent a specific characteristic, number, operation, constituent element, component or combination thereof, but cannot be interpreted to exclude the existence or addition possibility of one or more other characteristics, numbers, operations, constituent elements, components or combinations thereof.

[0050] It should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0051] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0052] In the present application, unless otherwise specifically defined and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0053] Those skilled in the art will readily understand that the above description is only a preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A via structure provided on a circuit integration board including a plurality of signal layers, characterized by, The via structure comprises a via pillar and at least two pads; The via pillar penetrates at least two signal layers of the circuit integration board; The at least two pads are respectively arranged one by one at positions where the via pillar penetrates the at least two signal layers; Areas of adjacent pads in the at least two pads do not overlap in a length direction of the via pillar, and an area of each pad is less than a preset value.

2. The via structure of claim 1, wherein, Each pad is distributed on only one side of the via pillar in a corresponding signal layer.

3. The via structure of claim 1 or 2, wherein, The pad is long strip-shaped.

4. The via structure of claim 3, wherein, Adjacent pads in the at least two pads have an obtuse angle in the length direction.

5. The via structure of claim 4, wherein, Adjacent pads in the at least two pads have an angle of 180 degrees in the length direction.

6. The via structure of claim 1, wherein, An area of the pad is less than a preset proportion of an area of a preset disc-shaped pad; a difference between an inner diameter and an outer diameter of the disc-shaped pad is similar to a length of the pad.

7. An integrated circuit board, characterized by The via structure of any one of claims 1 to 6.

8. An electronic device, comprising: The via structure of any one of claims 1 to 6.

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