Optical chip packaging structure

Abstract

The utility model provides an optical chip packaging structure. The optical chip packaging structure comprises a first chip; one end of the waveguide wire is connected with the first chip; one end of the optical channel is connected with the waveguide wire, the other end of the optical channel is communicated with the outside, and an external optical signal enters the waveguide wire through the optical channel; and the mold sealing layer wraps the first chip and the waveguide wire, and the optical channel penetrates through the mold sealing layer. The advantages are that optical signals are directly guided into the waveguide wire through the optical channel, the problems of poor optical performance and the like caused by installation errors of optical components can be avoided, and the yield of products is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more specifically, to an optical chip packaging structure. Background Technology

[0002] In existing optical chip packaging structures, component bonding problems often occur in light sources or reflectors, causing the component mounting positions to shift, which in turn causes the propagation path of the optical signal to shift, affecting the performance of the packaging structure.

[0003] Figure 1 A schematic diagram of a prior art optical chip packaging structure is shown. Figure 1 As shown, the existing optical chip packaging structure includes a chip 901, a substrate 902, an adhesive layer 903, a light source 904, and a reflective unit 905. The chip 901 is provided with an optical pad 901a for receiving optical signals, and the substrate 902 is provided with a circuit layer 902a. The dashed rectangle and dashed triangle in the figure represent the designed installation positions of the light source 904 and the reflective unit 905, respectively. It can be seen that there is an error between the actual installation positions of the solid light source 904 and the designed installation positions of the dashed lines. This leads to a difference between the designed optical signal path of the dashed arrow and the actual optical signal path of the solid line. As a result, the optical signal emitted by the light source 904 cannot enter the optical pad 901a correctly, which will cause poor product performance and reduce the yield of the product manufacturing process.

[0004] In summary, there is a need in the art to provide a packaging structure that can overcome the shortcomings of the prior art. Utility Model Content

[0005] This application provides a packaging structure that can solve the problems of the prior art. The objective of this application is achieved through the following technical solution.

[0006] One embodiment of this application provides an optical chip packaging structure, which includes: a first chip; a waveguide, one end of which is connected to the first chip; an optical channel, one end of which is connected to the waveguide and the other end of which is connected to the outside, through which an external optical signal enters the waveguide; and a molding layer, which covers the first chip and the waveguide, through which the optical channel passes.

[0007] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes an optical channel comprising a reflective layer disposed on the inner surface of the optical channel.

[0008] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of this application has a cross-sectional area of ​​the optical channel that gradually decreases from the side communicating with the outside to the side communicating with the waveguide.

[0009] In some optional embodiments, the optical chip packaging structure provided according to one of the above embodiments of this application, wherein the first chip is a photonic integrated circuit (PIC) or an electronic integrated circuit (EIC).

[0010] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes a waveguide including a protective layer with an opening, the protective layer covering the outside of the waveguide, and the optical channel communicating with the opening.

[0011] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application further includes a second chip, and the two ends of the waveguide are respectively connected to the first chip and the second chip.

[0012] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application, wherein the second chip is a photonic integrated circuit (PIC) or an electronic integrated circuit (EIC).

[0013] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application further includes a substrate, and the two ends of the waveguide are respectively connected to the first chip and the substrate.

[0014] In some alternative embodiments, according to the optical chip packaging structure provided by one embodiment of the present application, the first chip includes a first optical pad, and the waveguide is connected to the first chip through the first optical pad.

[0015] In some alternative embodiments, according to the optical chip packaging structure provided by one embodiment of the present application, the second chip includes a second optical pad, and the waveguide is connected to the second chip through the second optical pad.

[0016] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes a substrate comprising a third optical pad, and a waveguide is connected to the substrate through the third optical pad.

[0017] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of this application above includes a waveguide that is an optical lead.

[0018] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application, wherein the first chip is a thin optical chip.

[0019] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application, wherein the second chip is a thin optical chip.

[0020] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes multiple optical channels, one end of each optical channel is connected to the same waveguide, and the other end of each optical channel is connected to the outside, so that external optical signals can enter the waveguide through different optical channels.

[0021] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes multiple optical channels, one end of each optical channel is connected to different waveguides, and the other end of each optical channel is connected to the outside, so that external optical signals can enter different waveguides through different optical channels.

[0022] The advantages of the optical chip packaging structure according to the embodiments of this application are: by directly guiding optical signals into the waveguide through the optical channel, it can avoid problems such as poor optical performance caused by installation errors of optical components, thereby improving the product yield. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0024] Figure 1 A schematic diagram of a prior art optical chip packaging structure is shown;

[0025] Figure 2 A schematic diagram of an optical chip packaging structure according to an embodiment of this application is shown;

[0026] Figure 3 As shown Figure 2 An enlarged schematic diagram of portion A in an optical chip packaging structure according to an embodiment of this application is shown;

[0027] Figure 4-1 A schematic diagram of the manufacturing process of the first chip in an optical chip packaging structure according to an embodiment of this application is shown;

[0028] Figure 4-2 A schematic diagram of the manufacturing process of the first chip in the optical chip packaging structure according to the second embodiment of this application is shown;

[0029] Figure 5-1 , Figure 5-2 and Figure 5-3 As shown Figure 2 The diagram shown is a manufacturing process diagram of an optical chip packaging structure according to an embodiment of this application;

[0030] Figure 6 A schematic diagram of an optical chip packaging structure according to a second embodiment of this application is shown;

[0031] Figure 7 A schematic diagram of an optical chip packaging structure according to a third embodiment of this application is shown;

[0032] Figure 8 A perspective view of an optical chip packaging structure according to an embodiment of this application is shown;

[0033] Figure 9 A side view schematic diagram of an optical chip packaging structure according to an embodiment of the present application is shown, showing the side having an optical channel.

[0034] Figure 10 A side view schematic diagram of an optical chip packaging structure according to another embodiment of this application is shown, showing the side with the optical channel.

[0035] Figure 11 A schematic diagram of an optical chip packaging structure using panel-level (PNL) packaging according to one embodiment of this application is shown.

[0036] Figure 12 A schematic diagram of an optical chip packaging structure using wafer-level (WL) packaging according to one embodiment of this application is shown.

[0037] Labels and component names:

[0038] 1-First chip, 2-Waveguide, 3-Optical channel, 4-Molding layer, 5-Second chip, 6-Substrate, 7-Electrical connector, 8-Wire bonding, 11-First optical pad, 12-First electrical pad, 13-First adhesive layer, 21-Protective layer, 22-Opening, 51-Second optical pad, 52-Second electrical pad, 53-Second adhesive layer, 61-Third optical pad, 62-Third electrical pad, 63-Connecting pad, 100-Optical chip assembly, 101-First chip, 101a-First optical pad, 101b 102-First electrical pad, 201-Substrate, 201a-Second optical pad, 201b-Second electrical pad, 202-Second adhesive layer, 203-Second chip, 204-Wire bonding, 205-Waveguide, 206-Molding layer, 206a-Optical channel, 206b-Reflective layer, 207-Electrical connector, 901-Chip, 901a-Optical pad, 902-Substrate, 902a-Circuit layer, 903-Adhesive layer, 904-Light source, 905-Reflective unit, B-Optical chip. Detailed Implementation

[0039] The specific embodiments of this application are described below with reference to the accompanying drawings and examples. Through the content described in this specification, those skilled in the art can clearly and completely understand the technical solution, the technical problem solved, and the resulting technical effects of this application. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, for ease of description, only the parts related to this application are shown in the accompanying drawings.

[0040] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0041] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0042] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0043] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0044] The term "electrical connector" as used in this article can refer to a pad or a bump. A bump can be, for example, a gold bump (usually rectangular and made of gold), a solder bump (usually round and made of copper and tin), or a pillar bump (usually octagonal or polygonal and made of copper and tin or lead and tin).

[0045] The term "molding compound" as used herein includes, but is not limited to, epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0046] As used herein, the terms "wire bonding," "electrical pad," and "connector pad" can refer to materials composed of conductive materials. It should be noted that the fabrication process can employ currently known or future-developed forming technologies, and this disclosure does not specifically limit this. For example, electrical pads and connector pads can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. The conductive material can be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0047] The term "adhesive layer" as used in this article can refer to liquid or thin-film organic materials, such as: non-conductive paste (NCP), non-conductive film (NCF), anisotropic conductive paste (ACP), anisotropic conductive film (ACF), polyimide (PI), epoxy resin, resin, PP (Prepreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), adhesives, etc.

[0048] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] Figure 2 A schematic diagram of an optical chip packaging structure according to an embodiment of this application is shown. Figure 3 As shown Figure 2 The diagram shown is an enlarged view of portion A in an optical chip packaging structure according to an embodiment of this application. Figures 2 to 3 As shown, the optical chip packaging structure includes: a first chip 1; a waveguide 2, one end of which is connected to the first chip 1; and an optical channel 3, one end of which is connected to the waveguide 2, and the other end of which is connected to the outside. External optical signals enter the waveguide 2 through the optical channel 3.

[0050] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application, wherein the first chip 1 is a photonic integrated circuit (PIC) or an electronic integrated circuit (EIC).

[0051] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes an optical channel 3 comprising a reflective layer disposed on the inner surface of the optical channel 3.

[0052] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application, wherein the included angle B between the sidewalls of the optical channel 3 is greater than or equal to 0° and less than 60°.

[0053] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application has a cross-sectional area of ​​the optical channel 3 that tapers from the side communicating with the outside to the side connecting the waveguide 2, and this taper shape is generated by a laser etching process.

[0054] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application further includes a molding layer 4, which covers the first chip 1 and the waveguide 2, and the optical channel 3 passes through the molding layer 4.

[0055] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes a waveguide 2 including a protective layer 21, an opening 22 on the protective layer 21, the protective layer 21 covering the outside of the waveguide 2, and the optical channel 3 communicating with the opening 22.

[0056] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application further includes a second chip 5, and the two ends of the waveguide 2 are respectively connected to the first chip 1 and the second chip 5.

[0057] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application, wherein the second chip 5 is a photonic integrated circuit (PIC) or an electronic integrated circuit (EIC).

[0058] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application further includes a substrate 6, and the two ends of the waveguide 2 are respectively connected to the first chip 1 and the substrate 6.

[0059] In some optional embodiments, according to the optical chip packaging structure provided by one embodiment of the present application, the first chip 1 includes a first optical pad 11, and the waveguide 2 is connected to the first chip 1 through the first optical pad 11.

[0060] In some optional embodiments, according to the optical chip packaging structure provided by one embodiment of the present application, the second chip 5 includes a second optical pad 51, and the waveguide 2 is connected to the second chip 5 through the second optical pad 51.

[0061] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes a substrate 6 comprising a third optical pad 61, and a waveguide 2 connected to the substrate 6 via the third optical pad 61.

[0062] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application above, wherein the waveguide 2 is an optical lead.

[0063] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application, wherein the first chip 1 is a thin optical chip.

[0064] In some alternative embodiments, the optical chip packaging structure provided according to one embodiment of the present application, wherein the second chip 5 is a thin optical chip.

[0065] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application further includes an electrical connector 7, which is connected to the substrate 6 via a connecting pad 63.

[0066] In some alternative embodiments, according to the optical chip packaging structure provided by one embodiment of the present application, the first chip 1 is connected to the second chip 5 through the first adhesive layer 13, and the second chip 5 is connected to the substrate 6 through the second adhesive layer 53.

[0067] In some optional embodiments, the optical chip packaging structure provided according to one embodiment of the present application includes a first chip 1 further comprising a first electrical pad 12, a second chip 5 further comprising a second electrical pad 52, a substrate 6 comprising a third electrical pad 63, and the third electrical pad 63 being connected to the second electrical pad 52 and the third electrical pad 63 respectively via wire bonding 8.

[0068] like Figure 3 As shown, the light signal emitted by the external light source is reflected on the reflective layer within the light channel 3 and then enters the waveguide 2. The light signal then passes through the waveguide 2 and enters the first chip 1 and the second chip 5 connected at both ends of the waveguide 2. It should be noted that the components connected at both ends of the waveguide 2 determine the components through which the light signal propagates. For example, when the two ends of the waveguide 2 are connected to an optical chip and a substrate 6, respectively, the light signal entering the waveguide 2 from the light channel 3 will pass through the waveguide 2 and enter the optical chip and the substrate 6 at both ends of the waveguide 2.

[0069] Figure 4-1 A schematic diagram illustrating the manufacturing process of the first chip in an optical chip packaging structure according to an embodiment of this application is shown. Figure 4-1 As shown, the manufacturing process of the optical chip packaging structure includes multiple steps:

[0070] Step 1001: Provide an optical chip assembly 100, wherein the upper surface of the optical chip assembly 100 is provided with a first optical pad 101a and a first electrical pad 101b;

[0071] Step 1002: Flip the optical chip assembly 100 and thin the optical chip assembly 100;

[0072] Step 1003: Cutting the thinned optical chip assembly 100; and

[0073] Step 1004: Obtain the first chip 101.

[0074] Figure 4-2 A schematic diagram illustrating the manufacturing process of the first chip in the optical chip packaging structure according to a second embodiment of this application is shown. Figure 4-2 As shown, the manufacturing process of the first chip in the optical chip packaging structure of the second embodiment includes multiple steps:

[0075] Step 1005: Provide an optical chip assembly 100, wherein the upper surface of the optical chip assembly 100 is provided with a first optical pad 101a and a first electrical pad 101b;

[0076] Step 1006: Flip the optical chip assembly 100 and thin the optical chip assembly 100;

[0077] Step 1007: Deposit a first adhesive layer 102 on the upper surface of the thinned chip assembly 100;

[0078] Step 1008: Cutting the thinned optical chip assembly 100; and

[0079] Step 1009: Obtain the first chip 101; wherein, the first chip 101 has a first adhesive layer 102 on the side opposite to the first optical pad 101a and the first electrical pad 101b.

[0080] Figure 5-1 , Figure 5-2 and Figure 5-3 As shown Figure 2 The diagram shown illustrates the manufacturing process of an optical chip packaging structure according to an embodiment of this application. Figure 5-1 , Figure 5-2 and Figure 5-3 As shown, the manufacturing process of the optical chip packaging structure includes multiple steps:

[0081] Step 2001: Provide a substrate 201, and provide a second adhesive layer 202 on the upper surface of the substrate 201; wherein, the upper surface of the substrate 201 is provided with one or more second optical pads 201a and one or more second electrical pads 201b, and the lower surface of the substrate 201 is provided with a plurality of connecting pads 201c.

[0082] Step 2002: A second chip 203 is disposed on the upper surface of the substrate 201 by means of the second adhesive layer 202; wherein, the upper surface of the second chip 203 is provided with a third optical pad 203a and a third electrical pad 203b;

[0083] Step 2003: The first chip 102 is disposed on the upper surface of the second chip 203; wherein the first chip 102 is connected to the second chip 203 through the first adhesive layer 102;

[0084] Step 2004: Connect the second electrical pad 201b and the third electrical pad 203b using a punch wire 204; wherein, during installation, the outside of the punch wire 204 is provided with a sleeve 204a;

[0085] Step 2005: Connect the second optical pad 201a and the third optical pad 203a using waveguide 205;

[0086] Step 2006: Connect the first optical pad 101a and the third optical pad 203a using waveguide 205;

[0087] Step 2007: Connect the first electrical pad 101b and the second electrical pad 201b using the bonding wire 204;

[0088] Step 2008: A molding layer 206 is formed on the upper surface of the substrate 201, so that the molding layer 206 covers the first chip 101, the second chip 203, the wire bonding 204 and the waveguide 205;

[0089] Step 2009: Flip the product obtained in step 2008 and install the electrical connector 207 on the connecting gasket 201c;

[0090] Step 2010: Flip and cut the product obtained in step 2009;

[0091] Step 2011: Drill holes in the sealing layer 206;

[0092] Step 2012: A reflective material is deposited on the inner surface of the light channel 206a formed by drilling; wherein one end of the light channel 206a is connected to the waveguide 205, and the other end of the light channel 206a is connected to the outside of the molding layer 206. The process of depositing the reflective material includes, but is not limited to: printing, lamination, potting, coating; and

[0093] Step 2013: A reflective layer 206b is formed on the inner surface of the light channel 206 by a reflective material; wherein, the light signal emitted by the external light source can be reflected on the reflective layer 206b and then enter the waveguide 205.

[0094] Figure 6 A schematic diagram of an optical chip packaging structure according to a second embodiment of this application is shown. Figure 6 As shown, the optical chip packaging structure of the second embodiment includes multiple optical channels 3. One end of each optical channel 3 is connected to the same waveguide 2, and the other end of each optical channel 3 is connected to the outside. External optical signals can enter the waveguide 2 through different optical channels 3.

[0095] Figure 7 A schematic diagram of an optical chip packaging structure according to a third embodiment of this application is shown. Figure 7 As shown, the optical chip packaging structure of the third embodiment includes multiple optical channels 3. One end of each optical channel 3 is connected to different waveguides 2, and the other end of each optical channel 3 is connected to the outside. External optical signals can enter different waveguides 2 through different optical channels 3.

[0096] Figure 8 A perspective view of an optical chip packaging structure according to an embodiment of this application is shown. Figure 9 A side view of the optical chip packaging structure according to an embodiment of this application, showing the side with optical channel 3, is shown. Figure 8 and Figure 9 As shown, the optical chip packaging structure includes an optical channel 3, and the outlet of the optical channel 3 is a continuous rectangle.

[0097] Figure 10 A side view of the optical chip packaging structure according to another embodiment of this application, showing the side with optical channel 3, is shown. Figure 10 As shown, the optical chip packaging structure includes multiple optical channels 3, and the outlets of the multiple optical channels 3 are linearly arranged on one side of the molding layer 4.

[0098] Figure 11 A schematic diagram of an optical chip packaging structure using panel-level (PNL) packaging according to one embodiment of this application is shown. Figure 11 As shown, the optical chip packaging structure is rectangular, and the optical chip B is disposed on the optical chip packaging structure. The optical chip may include the first chip and / or the second chip in the aforementioned embodiments.

[0099] Figure 12 A schematic diagram of an optical chip packaging structure using wafer-level (WL) packaging according to one embodiment of this application is shown. Figure 12 As shown, the optical chip packaging structure is rectangular, and the optical chip B is disposed on the optical chip packaging structure. The optical chip may include the first chip and / or the second chip in the aforementioned embodiments.

[0100] The advantages of the optical chip packaging structure according to the embodiments of this application are: by directly guiding optical signals into the waveguide through the optical channel, it can avoid problems such as poor optical performance caused by installation errors of optical components, thereby improving the product yield.

[0101] Although this application has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not intended to limit the application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the scope of protection of this application as defined by the claims. Differences may exist between the technical representation in this application and actual devices due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The specification and illustrations should be considered illustrative rather than restrictive, and modifications can be made to suit the purpose and spirit of this application, all of which are within the scope of the claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be rearranged, subdivided, or arranged to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the application.

Claims

1. A light chip packaging structure, characterized in that, include: First chip; A waveguide, one end of which is connected to a first chip; An optical channel, one end of which is connected to the waveguide, and the other end of which is connected to the outside, through which external optical signals enter the waveguide; A molding layer covers the first chip and the waveguide, and the optical channel passes through the molding layer.

2. The optical chip packaging structure according to claim 1, characterized in that, The optical channel includes a reflective layer disposed on the inner surface of the optical channel.

3. The optical chip packaging structure according to claim 1, characterized in that, The first chip is a photonic integrated circuit (PIC) or an electronic integrated circuit (EIC).

4. The optical chip packaging structure according to claim 1, characterized in that, The waveguide includes a protective layer with an opening. The protective layer covers the outside of the waveguide, and the optical channel communicates with the opening.

5. The optical chip packaging structure according to claim 1, characterized in that, The optical chip packaging structure also includes a second chip, and the two ends of the waveguide are respectively connected to the first chip and the second chip.

6. The optical chip packaging structure according to claim 1, characterized in that, The optical chip packaging structure also includes a substrate, and the two ends of the waveguide are respectively connected to the first chip and the substrate.

7. The optical chip packaging structure according to claim 1, characterized in that, The first chip includes a first optical pad, and the waveguide is connected to the first chip through the first optical pad.

8. The optical chip packaging structure according to claim 5, characterized in that, The second chip includes a second optical pad, and the waveguide is connected to the second chip through the second optical pad.

9. The optical chip packaging structure according to claim 1, characterized in that, The optical chip packaging structure includes multiple optical channels, one end of each optical channel is connected to the same waveguide, and the other end of each optical channel is connected to the outside. External optical signals can enter the waveguide through different optical channels.

10. The optical chip packaging structure according to claim 1, characterized in that, The optical chip packaging structure includes multiple optical channels, one end of each optical channel is connected to different waveguides, and the other end of each optical channel is connected to the outside. External optical signals can enter different waveguides through different optical channels.

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